Hi Peng,
On 11/17/18 8:22 PM, Peng Hao wrote:
> In match function it should not call OBJECK_CHECK. When there is
> a mismatch, we should continue to match rather than assert().
Normally this issue should have been fixed by
e9ac8e84f0 "hw/arm/sysbus-fdt: Only call match_fn callback if the type
ma
Hi Thomas,
On 11/20/18 12:05 PM, Thomas Huth wrote:
> On 2018-11-20 11:19, Peter Maydell wrote:
>> On 19 November 2018 at 19:57, Thomas Huth wrote:
>>> I apparently missed some more files and even a complete machine (the
>>> "imx25-pdk") in my previous patch... but now we should hopefully have
>>
Hi Peter,
On 10/8/18 8:47 AM, Peter Xu wrote:
> There are two callers for vtd_sync_shadow_page_table_range(): one
> provided a valid context entry and one not. Move that fetching
> operation into the caller vtd_sync_shadow_page_table() where we need to
> fetch the context entry.
>
> Meanwhile, r
Hi Peter,
On 10/8/18 8:47 AM, Peter Xu wrote:
> We should handle VTD_FR_CONTEXT_ENTRY_P properly when synchronizing
> shadow page tables. Having invalid context entry there is perfectly
> valid when we move a device out of an existing domain. When that
> happens, instead of posting an error we i
Hi Peter,
On 10/9/18 9:45 AM, Peter Xu wrote:
> We should handle VTD_FR_CONTEXT_ENTRY_P properly when synchronizing
> shadow page tables. Having invalid context entry there is perfectly
> valid when we move a device out of an existing domain. When that
> happens, instead of posting an error we i
Hi Igor,
On 7/18/18 4:08 PM, Igor Mammedov wrote:
> On Tue, 3 Jul 2018 09:19:43 +0200
> Eric Auger wrote:
>
>> This series aims at supporting PCDIMM/NVDIMM intantiation in
>> machvirt at 2TB guest physical address.
>>
>> This is achieved in 3 steps:
>> 1) support more than 40b IPA/GPA
> will it
Hi Yi,
On 10/18/18 12:30 PM, Liu, Yi L wrote:
> Hi Eric,
>
>> From: Eric Auger [mailto:eric.au...@redhat.com]
>> Sent: Friday, September 21, 2018 4:18 PM
>> Subject: [RFC v2 00/28] vSMMUv3/pSMMUv3 2 stage VFIO integration
>>
>> Up to now vSMMUv3 has not been integrated with VFIO. VFIO
>> integrat
Hi Richard,
On 10/19/18 4:58 AM, Richard Henderson wrote:
> On 10/18/18 7:30 AM, Eric Auger wrote:
>> +#define SZ_1G (1024ULL * 1024 * 1024)
>
> already defines GiB.
noted
thanks!
Eric
>
>
> r~
>
Hi Suzuki,
On 10/19/18 10:49 AM, Suzuki K Poulose wrote:
> Hi Eric,
>
> On 10/18/2018 03:30 PM, Eric Auger wrote:
>> This is a header update against kvmarm next branch
>>
>> git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm kvmarm/next
>>
>> to get the KVM_ARM_GET_MAX_VM_PHYS_SHIFT ioct
Hi,
On 10/19/18 7:20 AM, Li Qiang wrote:
> Signed-off-by: Li Qiang
> ---
> hw/vfio/platform.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/vfio/platform.c b/hw/vfio/platform.c
> index ba03dcd..5992fe7 100644
> --- a/hw/vfio/platform.c
> +++ b/hw/vfio/platform.
Hi Li,
On 10/19/18 7:20 AM, Li Qiang wrote:
> Signed-off-by: Li Qiang
> ---
> hw/vfio/platform.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/vfio/platform.c b/hw/vfio/platform.c
> index ba19143..e9d9e80 100644
> --- a/hw/vfio/platform.c
> +++ b/hw/vfio/platfor
Hi Greg,
On 10/22/18 4:39 PM, Greg Kurz wrote:
> On Fri, 21 Sep 2018 10:17:58 +0200
> Eric Auger wrote:
>
>> To prepare for testing yet another extension, let's
>> refactor the code. We introduce vfio_iommu_get_type()
>> helper which selects the richest API (v2 first). Then
>> vfio_init_container
Hi Thomas,
On 11/5/18 10:17 AM, Thomas Huth wrote:
> On 2018-09-27 13:54, Geert Uytterhoeven wrote:
>> From: Auger Eric
>>
>> Up to now we have relied on the device type to identify a device tree
>> node creation function. Since we would like the vfio-platform device
Hi Hongbo,
On 10/23/18 12:21 PM, Hongbo Zhang wrote:
> Well, after checking manually, the header files
> "hw/arm/primecell.h"
> "qapi/visitor.h"
> "hw/arm/smmuv3.h"
> are really not used in virt.c, still can be removed.
>
> On 22 October 2018 at 18:17, Hongbo Zhang wrote:
>> On 22 October 2018 a
Hi Igor,
On 10/22/18 3:40 PM, Igor Mammedov wrote:
> On Thu, 18 Oct 2018 16:30:38 +0200
> Eric Auger wrote:
>
>> From: Shameer Kolothum
>>
>> Generate Memory Affinity Structures for PC-DIMM ranges.
>>
>> Signed-off-by: Shameer Kolothum
>> Signed-off-by: Eric Auger
>>
>> ---
>> v3 -> v4:
>> -
Hi Geert,
On 9/13/18 5:44 PM, Geert Uytterhoeven wrote:
> From: Auger Eric
>
> Up to now we have relied on the device type to identify a device tree
> node creation function. Since we would like the vfio-platform device to
> be instantiatable with different compatible strings w
Hi Geert,
On 9/13/18 5:44 PM, Geert Uytterhoeven wrote:
> Allow the instantation of generic dynamic vfio-platform devices again,
> without the need to create a new device-specific vfio type.
>
> This is more or less a partial revert of commit 6f2062b9758ebc64
> ("hw/arm/virt: Allow only supported
On 9/13/18 5:44 PM, Geert Uytterhoeven wrote:
> From: Auger Eric
>
> Up to now the vfio-platform device has been abstract and could not be
> instantiated. The integration of a new vfio platform device required
> creating a dummy derived device which only set the co
Hi Peter,
On 9/25/18 12:25 PM, Peter Maydell wrote:
> On 21 September 2018 at 08:01, Eric Auger wrote:
>> The event queue management is broken today. Event records
>> are not properly written as EVT_SET_* macro was not updating
>> the actual event record. Also the event queue interrupt
>> is not
Hi Peter,
On 9/25/18 4:09 PM, Peter Maydell wrote:
> On 21 September 2018 at 08:01, Eric Auger wrote:
>> At the point smmu_find_add_as() gets called, the bus number might
>> not be computed. Let's change the name of IOMMU memory region and
>> just use the devfn and an incrementing index.
>>
>> Th
Hi Peter,
On 9/25/18 4:24 PM, Peter Maydell wrote:
> On 25 September 2018 at 15:16, Auger Eric wrote:
>> Hi Peter,
>>
>> On 9/25/18 4:09 PM, Peter Maydell wrote:
>>> On 21 September 2018 at 08:01, Eric Auger wrote:
>>>> At the point smmu_find_add_as()
Hi Peter,
On 9/7/18 4:46 AM, Peter Xu wrote:
> QEMU is not handling the global DMAR switch well, especially when from
> "on" to "off".
>
> Let's first take the example of system reset.
>
> Assuming that a guest has IOMMU enabled. When it reboots, we will drop
> all the existing DMAR mappings to
Hi David,
On 9/26/18 11:41 AM, David Hildenbrand wrote:
> We're plugging/unplugging a PCDIMMDevice, so directly pass this type
> instead of a more generic DeviceState.
>
> Signed-off-by: David Hildenbrand
Reviewed-by: Eric Auger
Thanks
Eric
> ---
> hw/i386/pc.c | 6 +++---
> hw/
Hi David,
On 9/26/18 11:42 AM, David Hildenbrand wrote:
> Let's properly forward the errors, so errors from get_region_size() /
> get_plugged_size() can be handled.
>
> Users right now call both functions after the device has been realized,
> which is will never fail, so it is fine to continue usi
Hi David,
On 9/26/18 11:42 AM, David Hildenbrand wrote:
> Document the functions and when to not expect errors.
>
> Reviewed-by: David Gibson
> Signed-off-by: David Hildenbrand
> ---
> include/hw/mem/memory-device.h | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/i
Hi David,
On 9/26/18 11:42 AM, David Hildenbrand wrote:
> To be able to factor out address asignment of memory devices, we will
s/asignment/assignment
> have to read (get_addr()) and write (set_addr()) the address.
>
> We can't use properties for this purpose, as properties are device
> specific.
Hi David,
On 9/26/18 11:42 AM, David Hildenbrand wrote:
> With the new memory device functions in place, we can factor out
> plugging of memory devices completely.
>
> Reviewed-by: David Gibson
> Reviewed-by: Igor Mammedov
> Signed-off-by: David Hildenbrand
> ---
> hw/mem/memory-device.c
Hi David,
On 9/26/18 11:42 AM, David Hildenbrand wrote:
> With the new memory device functions in place, we can factor out
> unplugging of memory devices completely.
>
> Reviewed-by: David Gibson
> Reviewed-by: Igor Mammedov
> Signed-off-by: David Hildenbrand
> ---
> hw/mem/memory-device.c
Hi David,
On 9/26/18 11:42 AM, David Hildenbrand wrote:
> Let's trace the address when pre_pluggin/plugging/unplugging a memory device.
>
> Trace it when pre_plugging as well as when plugging, so we really know
> when a specific address is actually used.
>
> Reviewed-by: David Gibson
> Reviewed
Hi David,
On 9/26/18 11:42 AM, David Hildenbrand wrote:
> When reporting the id of virtio-based memory devices, we always have to
> take the one of the proxy device (parent), not the one of the memory
> device directly.
>
> Let's generalize this by allowing memory devices to specify an optional
>
Hi David,
On 10/1/18 10:13 AM, David Hildenbrand wrote:
> On 30/09/2018 16:43, Auger Eric wrote:
>> Hi David,
>>
>> On 9/26/18 11:42 AM, David Hildenbrand wrote:
>>> Document the functions and when to not expect errors.
>>>
>>> Reviewed-by: Da
Hi Peter,
On 9/29/18 5:36 AM, Peter Xu wrote:
> v4:
> - add a patch to introduce vtd_reset_caches()
> - reset the caches in the two places where GCMD update happens [Eric]
>
> Please review, thanks.
For the series
Reviewed-by: Eric Auger
Thanks
Eric
>
> Peter Xu (2):
> intel_iommu: intro
Hi Peter,
On 9/13/18 9:55 AM, Peter Xu wrote:
> There are two callers for vtd_sync_shadow_page_table_range(), one
> provided a valid context entry and one not. Move that fetching
> operation into the caller vtd_sync_shadow_page_table() where we need to
> fetch the context entry.
>
> Meanwhile, we
Hi,
On 7/3/18 9:19 AM, Eric Auger wrote:
> This series aims at supporting PCDIMM/NVDIMM intantiation in
> machvirt at 2TB guest physical address.
>
> This is achieved in 3 steps:
> 1) support more than 40b IPA/GPA
> 2) support PCDIMM instantiation
> 3) support NVDIMM instantiation
While respinni
Hi Dave,
On 10/3/18 4:13 PM, Dr. David Alan Gilbert wrote:
> * Auger Eric (eric.au...@redhat.com) wrote:
>> Hi,
>>
>> On 7/3/18 9:19 AM, Eric Auger wrote:
>>> This series aims at supporting PCDIMM/NVDIMM intantiation in
>>> machvirt at 2TB guest physical
Hi Igor,
On 10/4/18 1:11 PM, Igor Mammedov wrote:
> On Wed, 3 Oct 2018 15:49:03 +0200
> Auger Eric wrote:
>
>> Hi,
>>
>> On 7/3/18 9:19 AM, Eric Auger wrote:
>>> This series aims at supporting PCDIMM/NVDIMM intantiation in
>>> machvirt at 2TB guest
Hi David,
On 10/4/18 2:02 PM, David Hildenbrand wrote:
Alternative to have a split model is having a floating RAM base for a
contiguous initial + device memory (contiguity actually depends on
initial RAM size alignment too). This requires significant changes in FW
and also pote
Hi Bharat,
On 11/22/18 10:15 AM, Bharat Bhushan wrote:
> Hi Eric,
>
>
>> -Original Message-
>> From: Eric Auger
>> Sent: Friday, November 9, 2018 5:00 PM
>> To: eric.auger@gmail.com; eric.au...@redhat.com; qemu-
>> de...@nongnu.org; qemu-...@nongnu.org; peter.mayd...@linaro.org;
>>
Hi Bharat,
On 11/23/18 7:38 AM, Bharat Bhushan wrote:
> Hi Eric,
>
>> -Original Message-
>> From: Eric Auger
>> Sent: Thursday, November 22, 2018 10:45 PM
>> To: eric.auger@gmail.com; eric.au...@redhat.com; qemu-
>> de...@nongnu.org; qemu-...@nongnu.org; peter.mayd...@linaro.org;
>>
Hi Philippe,
On 11/22/18 11:33 PM, Philippe Mathieu-Daudé wrote:
> Hi Eric,
>
> On 22/11/18 19:01, Eric Auger wrote:
>> Add a new ARM SMMU section and set Eric Auger as the maintainer
>> for ARM SMMU emulation sources.
>>
>> Signed-off-by: Eric Auger
>> Suggested-by: Peter Maydell
>> ---
>> MA
Hi Bharat,
On 11/23/18 10:14 AM, Bharat Bhushan wrote:
> Hi Eric,
>
>> -Original Message-----
>> From: Auger Eric
>> Sent: Friday, November 23, 2018 1:23 PM
>> To: Bharat Bhushan ;
>> eric.auger@gmail.com; qemu-devel@nongnu.org; qemu-
>> a.
Hi Shameer,
On 11/23/18 5:28 PM, Shameerali Kolothum Thodi wrote:
>
>
>> -Original Message-
>> From: Qemu-devel [mailto:qemu-devel-
>> bounces+shameerali.kolothum.thodi=huawei@nongnu.org] On Behalf Of
>> Eric Auger
>> Sent: 21 September 2018 09:18
>> To: eric.auger@gmail.com; eri
Hi Shameer,
On 11/23/18 5:28 PM, Shameerali Kolothum Thodi wrote:
>
>
>> -Original Message-
>> From: Qemu-devel [mailto:qemu-devel-
>> bounces+shameerali.kolothum.thodi=huawei@nongnu.org] On Behalf Of
>> Eric Auger
>> Sent: 21 September 2018 09:18
>> To: eric.auger@gmail.com; eri
Hi Shameer,
On 11/26/18 6:04 PM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>> -Original Message-
>> From: Eric Auger [mailto:eric.au...@redhat.com]
>> Sent: 26 November 2018 15:46
>> To: eric.auger@gmail.com; eric.au...@redhat.com; qemu-
>> de...@nongnu.org; qemu-...@nongnu.org; pe
Hi Shannon,
On 11/26/18 4:46 PM, Eric Auger wrote:
> The AcpiIortSmmu3 misses 2 32b fields corresponding to the
> proximity domain and the device id mapping index.
I fail to understand how we currently track the evolutions of the IORT
structures:
Looking at the smmuv3 node in kernel include/acpi/
Hi Shannon,
On 11/28/18 5:39 PM, Shannon Zhao wrote:
>
>
> On 2018/11/27 13:53, Auger Eric wrote:
>> Hi Shannon,
>>
>> On 11/26/18 4:46 PM, Eric Auger wrote:
>>> The AcpiIortSmmu3 misses 2 32b fields corresponding to the
>>> proximity domain
Hi Peter,
On 11/27/18 2:32 PM, Peter Maydell wrote:
> On Mon, 26 Nov 2018 at 15:46, Eric Auger wrote:
>>
>> The AcpiIortSmmu3 misses 2 32b fields corresponding to the
>> proximity domain and the device id mapping index.
>>
>> Also let's report IO-coherent access is supported for
>> translation ta
Hi Shannon,
On 11/29/18 3:24 AM, Shannon Zhao wrote:
>
>
> On 2018/11/29 1:26, Auger Eric wrote:
>>>>> struct AcpiIortSmmu3 {
>>>>> ACPI_IORT_NODE_HEADER_DEF
>>>>> uint64_t base_address;
>>>>> @@ -
Hi Drew,
On 12/17/18 5:02 PM, Andrew Jones wrote:
> On Thu, Dec 06, 2018 at 06:07:32PM +0100, Eric Auger wrote:
>> Let's report IO-coherent access is supported for translation
>> table walks, descriptor fetches and queues by setting the COHACC
>> override flag. Without that, we observe wrong comma
Hi Drew,
On 12/17/18 5:27 PM, Andrew Jones wrote:
> On Thu, Dec 06, 2018 at 06:07:33PM +0100, Eric Auger wrote:
>> Let's update the structs according to revision D of the IORT
>> specification and set the IORT node revision fields.
>>
>> In IORT smmuv3 node: the new proximity field is not used as
Hi Drew,
On 12/17/18 7:25 PM, Andrew Jones wrote:
> On Mon, Dec 17, 2018 at 05:49:02PM +0100, Auger Eric wrote:
>> Hi Drew,
>>
>> On 12/17/18 5:27 PM, Andrew Jones wrote:
>>> On Thu, Dec 06, 2018 at 06:07:33PM +0100, Eric Auger wrote:
>>>> Let's up
Hi Drew,
On 12/18/18 3:31 PM, Andrew Jones wrote:
> On Tue, Dec 18, 2018 at 11:54:32AM +0100, Auger Eric wrote:
>> Hi Drew,
>>
>> On 12/17/18 7:25 PM, Andrew Jones wrote:
>>> On Mon, Dec 17, 2018 at 05:49:02PM +0100, Auger Eric wrote:
>>>> Hi Drew,
&
Hi Alexey,
On 1/14/19 7:32 AM, Alexey Kardashevskiy wrote:
>
>
> On 12/01/2019 03:45, Eric Auger wrote:
>> In vfio_connect_container() the code that selects the
>> iommu type can benefit from helpers such as
>> vfio_iommu_get_type() and vfio_init_container(). As
>> a result we end up with a swit
Hi,
On 1/12/19 3:30 AM, Heyi Guo wrote:
> Hi folks,
>
> I have some questions about vfio_msix_vector_do_use() in hw/vfio/pci.c,
> could you help to explain?
>
> We can see that when guest tries to enable one specific MSIX vector by
> unmasking MSIX Vector Control, the access will be trapped and
Hi Cornelia,
On 1/15/19 1:03 PM, Cornelia Huck wrote:
> On Fri, 11 Jan 2019 17:58:00 +0100
> Eric Auger wrote:
>
>> The code used to attach the eventfd handler for the ERR and
>> REQ irq indices can be factorized into a helper. In subsequent
>> patches we will extend this helper to support other
Hi Cornelia,
On 1/15/19 1:12 PM, Cornelia Huck wrote:
> On Fri, 11 Jan 2019 17:58:01 +0100
> Eric Auger wrote:
>
>> We can also use vfio_register_event_notifier() helper in
>> vfio_intx_enable_kvm to set the signalling associated to
>> VFIO_PCI_INTX_IRQ_INDEX.
>>
>> Signed-off-by: Eric Auger
>>
Hi Alexey, Cornelia,
On 1/17/19 4:46 AM, Alexey Kardashevskiy wrote:
>
>
> On 12/01/2019 03:58, Eric Auger wrote:
>> The code used to attach the eventfd handler for the ERR and
>> REQ irq indices can be factorized into a helper. In subsequent
>> patches we will extend this helper to support othe
Hi Alexey,
On 1/18/19 5:51 AM, Alexey Kardashevskiy wrote:
>
>
> On 18/01/2019 08:02, Eric Auger wrote:
>> In vfio_connect_container() the code that selects the
>> iommu type can benefit from helpers such as
>> vfio_iommu_get_type() and vfio_init_container(). As
>> a result we end up with a swit
Hi Alexey,
On 1/18/19 5:14 AM, Alexey Kardashevskiy wrote:
>
>
> On 17/01/2019 20:16, Auger Eric wrote:
>> Hi Alexey, Cornelia,
>>
>> On 1/17/19 4:46 AM, Alexey Kardashevskiy wrote:
>>>
>>>
>>> On 12/01/2019 03:58, Eric Auger wrote:
>&g
Hi Geert,
On 1/3/19 10:42 AM, Geert Uytterhoeven wrote:
> Add a fallback for instantiating generic devices without a type-specific
> or compatible-specific instantiation method. This will be used when no
> other match is found.
>
> Generic device instantiation avoids having to write device-speci
Hi Geert,
On 1/9/19 4:55 PM, Auger Eric wrote:
> Hi Geert,
>
> On 1/3/19 10:42 AM, Geert Uytterhoeven wrote:
>> Add a fallback for instantiating generic devices without a type-specific
>> or compatible-specific instantiation method. This will be used when no
&g
Hi Geert,
On 1/9/19 5:15 PM, Geert Uytterhoeven wrote:
> Hi Eric,
>
> Thanks for your comments!
>
> On Wed, Jan 9, 2019 at 4:56 PM Auger Eric wrote:
>> On 1/3/19 10:42 AM, Geert Uytterhoeven wrote:
>>> Add a fallback for instantiating generic devices without a t
Hi Peter,
On 05/14/2018 06:23 PM, Peter Maydell wrote:
> On 4 May 2018 at 18:15, Peter Maydell wrote:
>> From: Eric Auger
>>
>> Let's introduce a helper function aiming at recording an
>> event in the event queue.
>
>> +void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info)
>> +{
>> +
Hi Paolo,
On 04/17/2018 04:07 PM, Paolo Bonzini wrote:
> MemoryRegionCache was reverted to "normal" address_space_* operations
> for 2.9, due to lack of support for IOMMUs. This series reinstates
> optimizations, caching only the IOMMU translation but not the IOMMU
> lookup and target AddressSpac
Hi Paolo
On 05/16/2018 12:42 PM, Paolo Bonzini wrote:
> On 16/05/2018 12:41, Auger Eric wrote:
>> This patch seems to cause a regression with ARM vsmmu +
>> virtio-blk-pci. Reverting it looks to fix the issue. Otherwise I
>> get:
>
> What's the command li
Hi Paolo,
On 05/16/2018 03:38 PM, Auger Eric wrote:
> Hi Paolo
>
> On 05/16/2018 12:42 PM, Paolo Bonzini wrote:
>> On 16/05/2018 12:41, Auger Eric wrote:
>>> This patch seems to cause a regression with ARM vsmmu +
>>> virtio-blk-pci. Reverting it looks to f
Hi Peter,
On 05/08/2018 06:25 PM, Peter Maydell wrote:
> On 1 May 2018 at 16:53, Auger Eric wrote:
>> Hi Peter,
>>
>> On 05/01/2018 05:00 PM, Peter Maydell wrote:
>>> On 1 May 2018 at 15:32, Auger Eric wrote:
>>>> Hi Peter,
>>>
Hi Philippe,
On 05/16/2018 10:01 PM, Philippe Mathieu-Daudé wrote:
> On 05/16/2018 01:23 PM, Peter Maydell wrote:
>> On 16 May 2018 at 16:16, Philippe Mathieu-Daudé wrote:
>>> Hi Eric,
>>>
>>> On 05/16/2018 03:03 PM, Eric Auger wrote:
Coverity points out that this can overflow if n > 31,
Hi Peter,
On 05/16/2018 06:18 PM, Peter Maydell wrote:
> On 16 May 2018 at 15:33, Auger Eric wrote:
>> On 05/08/2018 06:25 PM, Peter Maydell wrote:
>>> This runs into something I found when I was implementing the Arm
>>> Memory Protection Controller -- at the point whe
Hi Peter,
On 05/16/2018 08:31 PM, Eric Auger wrote:
> Let's cache config data to avoid fetching and parsing STE/CD
> structures on each translation. We invalidate them on data structure
> invalidation commands.
You may remember that initially I was taking a QemuMutex to protect
IOTLB/cache struct
Hi Peter,
On 05/04/2018 05:08 AM, Peter Xu wrote:
> That is not really necessary. Removing that node struct and put the
> list entry directly into VTDAddressSpace. It simplfies the code a lot.
>
> Signed-off-by: Peter Xu
> ---
> include/hw/i386/intel_iommu.h | 9 ++--
> hw/i386/intel_iom
Hi Peter,
On 05/17/2018 12:02 PM, Peter Xu wrote:
> On Thu, May 17, 2018 at 11:46:22AM +0200, Auger Eric wrote:
>> Hi Peter,
>>
>> On 05/04/2018 05:08 AM, Peter Xu wrote:
>>> That is not really necessary. Removing that node struct and put the
>>> list e
Hi Peter,
On 05/04/2018 05:08 AM, Peter Xu wrote:
> For UNMAP-only IOMMU notifiers, we don't really need to walk the page
s/really// ;-)
> tables. Fasten that procedure by skipping the page table walk. That
> should boost performance for UNMAP-only notifiers like vhost.
>
> Signed-off-by: Peter
Hi Peter,
On 05/04/2018 05:08 AM, Peter Xu wrote:
> We pass in the VTDAddressSpace to replace the aw bits when doing page
> walk. The VTDAddressSpace contains the aw bits information, meanwhile
> we'll need to do something more in the follow up patches regarding to
> the address spaces.
>
> Sign
Hi Peter,
On 05/04/2018 05:08 AM, Peter Xu wrote:
> Add a per-iommu big lock to protect IOMMU status. Currently the only
> thing to be protected is the IOTLB/context cache, since that can be
> accessed even without BQL, e.g., in IO dataplane.
As discussed together, Peter challenged per device mu
Hi Peter,
On 05/04/2018 05:08 AM, Peter Xu wrote:
> During the recursive page walking of IOVA page tables, some stack
> variables are constant variables and never changed during the whole page
> walking procedure. Isolate them into a struct so that we don't need to
> pass those contants down the
Hi Peter,
On 05/04/2018 05:08 AM, Peter Xu wrote:
> During IOVA page table walking, there is a special case when the PSI
> covers one whole PDE (Page Directory Entry, which contains 512 Page
> Table Entries) or more. In the past, we skip that entry and we don't
> notify the IOMMU notifiers. This
Hi Peter,
On 05/04/2018 05:08 AM, Peter Xu wrote:
> IOMMU replay was carried out before in many use cases, e.g., context
> cache invalidations, domain flushes. We used this mechanism to sync the
> shadow page table by firstly (1) unmap the whole address space, then
> (2) walk the page table to re
Hi Peter,
On 05/18/2018 07:59 AM, Peter Xu wrote:
> On Thu, May 17, 2018 at 04:32:58PM +0200, Auger Eric wrote:
>> Hi Peter,
>>
>> On 05/04/2018 05:08 AM, Peter Xu wrote:
>>> During the recursive page walking of IOVA page tables, some stack
>>> variables a
Hi Peter,
On 05/18/2018 08:06 AM, Peter Xu wrote:
> On Thu, May 17, 2018 at 07:23:33PM +0200, Auger Eric wrote:
>> Hi Peter,
>>
>> On 05/04/2018 05:08 AM, Peter Xu wrote:
>>> IOMMU replay was carried out before in many use cases, e.g., context
>>> cache
Hi Peter,
On 05/18/2018 07:53 AM, Peter Xu wrote:
> On Thu, May 17, 2018 at 03:39:50PM +0200, Auger Eric wrote:
>> Hi Peter,
>>
>> On 05/04/2018 05:08 AM, Peter Xu wrote:
>>> For UNMAP-only IOMMU notifiers, we don't really need to walk the page
>> s/rea
Hi,
On 05/18/2018 05:41 AM, Peter Xu wrote:
> On Thu, May 17, 2018 at 04:42:54PM +0200, Auger Eric wrote:
>> Hi Peter,
>>
>> On 05/04/2018 05:08 AM, Peter Xu wrote:
>>> During IOVA page table walking, there is a special case when the PSI
>>> covers one
Hi Peter,
On 05/17/2018 10:59 AM, Peter Xu wrote:
> We pass in the VTDAddressSpace too. It'll be used in the follow up
> patches.
So you evetually preferred to keep .aw. I don't have a strong opinion
but maybe a small preference to v2 version.
Nevertheless
Reviewed-by: E
Hi Peter,
On 05/17/2018 10:59 AM, Peter Xu wrote:
> During IOVA page table walking, there is a special case when the PSI
> covers one whole PDE (Page Directory Entry, which contains 512 Page
> Table Entries) or more. In the past, we skip that entry and we don't
> notify the IOMMU notifiers. This
On 05/17/2018 10:59 AM, Peter Xu wrote:
> During the recursive page walking of IOVA page tables, some stack
> variables are constant variables and never changed during the whole page
> walking procedure. Isolate them into a struct so that we don't need to
> pass those contants down the stack eve
Hi Peter,
On 05/21/2018 04:03 PM, Peter Maydell wrote:
> Implement the Arm TrustZone Memory Protection Controller, which sits
> in front of RAM and allows secure software to configure it to either
> pass through or reject transactions.
>
> We implement the MPC as a QEMU IOMMU, which will direct t
Hi Peter,
On 05/21/2018 04:03 PM, Peter Maydell wrote:
> Add more detail to the documentation for memory_region_init_iommu()
> and other IOMMU-related functions and data structures.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Eric Auger
Thanks
Eric
> ---
> v2->v3 changes:
> * minor wording
Hi Peter,
On 05/22/2018 01:56 PM, Peter Maydell wrote:
> On 22 May 2018 at 12:30, Auger Eric wrote:
>> Hi Peter,
>>
>> On 05/21/2018 04:03 PM, Peter Maydell wrote:
>>> Implement the Arm TrustZone Memory Protection Controller, which sits
>>> in front of RAM
Hi Peter,
On 05/21/2018 04:03 PM, Peter Maydell wrote:
> If an IOMMU supports mappings that care about the memory
> transaction attributes, then it no longer has a unique
> address -> output mapping, but more than one. We can
> represent these using an IOMMU index, analogous to TCG's
> mmu indexes.
Hi Peter,
On 05/22/2018 03:22 PM, Peter Maydell wrote:
> On 22 May 2018 at 13:58, Auger Eric wrote:
>> Hi Peter,
>> On 05/21/2018 04:03 PM, Peter Maydell wrote:
>>> If an IOMMU supports mappings that care about the memory
>>> transaction attributes, then it n
On 05/22/2018 04:19 PM, Peter Maydell wrote:
> On 22 May 2018 at 15:11, Auger Eric wrote:
>> Hi Peter,
>>
>> On 05/22/2018 03:22 PM, Peter Maydell wrote:
>>> How many substream IDs do we expect to see in practice?
>>
>> Spec says max 20 bits, matching
Hi,
On 05/10/2018 07:45 PM, Peter Maydell wrote:
> From: Igor Mammedov
>
> load_dtb() depends on arm_load_kernel() to figure out place
> in RAM where it should be loaded, but it's not required for
> arm_load_kernel() to work. Sometimes it's neccesary for
> devices added with -device/device_add t
ate that dependency anyways as well as
eliminate, anyway?
> separate arch CPU reset parts from arm_load_kernel() into CPU
> itself, but that refactoring that I probably would have to do
> anyways later for CPU hotplug to work.
may deserve some rewording.
>
> Reported-by: Auger Eric
Hi Laszlo,
On 05/23/2018 07:45 PM, Laszlo Ersek wrote:
> Hi Eric,
>
> On 05/23/18 18:03, Eric Auger wrote:
>> Current Machvirt PCI host controller's ECAM region is 16MB large.
>> This limits the number of PCIe buses to 16.
>>
>> PC/Q35 machines have a 256MB region allowing up to 256 buses.
>> Thi
Hi,
On 05/23/2018 10:52 PM, Laszlo Ersek wrote:
> On 05/23/18 22:40, Auger Eric wrote:
>> On 05/23/2018 07:45 PM, Laszlo Ersek wrote:
>
>>> Regarding the second patch, I do believe we need "more sophistication"
>>> there. For example, I guess it could be
Hi Shannon,
On 05/23/2018 05:53 AM, Shannon Zhao wrote:
> While we skip the GIC_INTERNAL irqs, we don't change the register offset
> accordingly. This will overlap the GICR registers value and leave the
> last GIC_INTERNAL irq's registers out of update.
>
> Fix this by skipping the registers bank
Hi Shannon,
On 05/24/2018 11:20 AM, Shannon Zhao wrote:
>
>
> On 2018/5/24 17:04, Auger Eric wrote:
>> Hi Shannon,
>>
>> On 05/23/2018 05:53 AM, Shannon Zhao wrote:
>>> While we skip the GIC_INTERNAL irqs, we don't change the register offset
>>>
Hi Peter, Laszlo,
On 05/24/2018 03:07 PM, Peter Maydell wrote:
> On 24 May 2018 at 13:59, Laszlo Ersek wrote:
>> On 05/24/18 11:11, Peter Maydell wrote:
>>> Won't it also break a guest which is just Linux loaded not via
>>> firmware which is an aarch32 kernel without LPAE support?
>>
>> Does such
Hi,
On 05/24/2018 03:14 PM, Peter Maydell wrote:
> On 24 May 2018 at 10:04, Auger Eric wrote:
>> Now I am unclear about the semantics of the s->gicd_ipriority & friends.
>> With that change, is it supposed to contain only the states of SPIs or
>> contain the RAZ st
Hi Laszlo,
On 05/24/2018 03:59 PM, Laszlo Ersek wrote:
> On 05/24/18 15:07, Peter Maydell wrote:
>> On 24 May 2018 at 13:59, Laszlo Ersek wrote:
>>> On 05/24/18 11:11, Peter Maydell wrote:
Won't it also break a guest which is just Linux loaded not via
firmware which is an aarch32 kernel
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