Hi All,
How about having a generic Virtio-based machine for emulating a virtual
desktop ?
I know folks have already thought about this and probably also tried
something or other on this front but, it will be good to know the downsides.
Virtio-desktop can be a separate specification describing a
On 24 January 2013 14:55, Stefan Hajnoczi wrote:
> On Thu, Jan 24, 2013 at 11:40:24AM +0530, Anup Patel wrote:
> > IMHO, If we have something like Virtio-desktop specification then all
> > possible guest OSes can have support for it and different hypervisor can
> > emulat
On Thu, Jan 24, 2013 at 8:08 PM, Alexander Graf wrote:
>
> On 24.01.2013, at 10:25, Stefan Hajnoczi wrote:
>
> > On Thu, Jan 24, 2013 at 11:40:24AM +0530, Anup Patel wrote:
> >> IMHO, If we have something like Virtio-desktop specification then all
> >> possible g
On Mon, Aug 5, 2013 at 4:48 PM, Peter Maydell wrote:
> From: John Rigby
>
> Add 'virt' platform support corresponding to arch/arm/mach-virt
> in the Linux kernel tree. This has no platform-specific code but
> can use any device whose kernel driver is is able to work purely
> from a device tree no
On Mon, Aug 5, 2013 at 5:31 PM, Peter Maydell wrote:
> On 5 August 2013 12:48, Anup Patel wrote:
>>> +static const MemMapEntry a15memmap[] = {
>>> +[VIRT_FLASH] = { 0, 0x10 },
>>
>> IMHO, 1 MB of flash is small for possible future expansion. If mach-vi
On Mon, Aug 5, 2013 at 5:58 PM, Peter Maydell wrote:
> On 5 August 2013 13:22, Anup Patel wrote:
>> On Mon, Aug 5, 2013 at 5:31 PM, Peter Maydell
>> wrote:
>>> On 5 August 2013 12:48, Anup Patel wrote:
>>>>> +static const MemMapEntry a15memmap[] = {
Hi PMM,
On Fri, Aug 9, 2013 at 9:53 PM, Peter Maydell wrote:
> From: John Rigby
>
> Add 'virt' platform support corresponding to arch/arm/mach-virt
> in the Linux kernel tree. This has no platform-specific code but
> can use any device whose kernel driver is is able to work purely
> from a devic
Public bug reported:
There is no command line option like -kerner, or -initrd to load an
arbitrary binary file to a RAM location when launching QEMU.
** Affects: qemu
Importance: Undecided
Status: New
--
You received this bug notification because you are a member of qemu-
devel-ml
Just to add to my use case.
Currently, to load a test binary called "arm_test.bin.patched" i have
hacked QEMU in the following manner:
diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index bfac982..e4873d4 100644
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -280,6 +280,13 @@ void arm_load_kernel(CPUStat
I am trying to develop a lightweight hypervisor for ARM Cortex-A8. In my
case I have to load hypervisor elf as kernel and there and number of
other binaries like flattened device tree binary for hypervisor
configuration, guest kernel binary, guest ramdisk, etc.
Currently, I am developing it for Re
I understand that we should not change -kernel option for backwards
compatibility, that's why I suggest some new option for loading
arbitrary binary file (not necessarily ELF file). This option would just
mean: "Just blindly load the given file to the given physical address".
We can also pass this
On Wed, Jan 22, 2014 at 11:09 AM, Victor Kamensky
wrote:
> Hi Guys,
>
> Christoffer and I had a bit heated chat :) on this
> subject last night. Christoffer, really appreciate
> your time! We did not really reach agreement
> during the chat and Christoffer asked me to follow
> up on this thread.
>
Hi Alex,
On Wed, Jan 22, 2014 at 12:11 PM, Alexander Graf wrote:
>
>
>> Am 22.01.2014 um 07:31 schrieb Anup Patel :
>>
>> On Wed, Jan 22, 2014 at 11:09 AM, Victor Kamensky
>> wrote:
>>> Hi Guys,
>>>
>>> Christoffer and I had a bit h
Hi Andrew,
On Mon, Oct 14, 2013 at 9:29 PM, Andrew Jones wrote:
> This is a virtio version of hw/misc/debugexit and should evolve into a
> virtio version of pc-testdev. pc-testdev uses the PC's ISA bus, whereas
> this testdev can be plugged into a virtio-mmio transport, which is
> needed for kvm-
On Tue, Oct 15, 2013 at 2:06 PM, Andrew Jones wrote:
> On Tue, Oct 15, 2013 at 12:26:10PM +0530, Anup Patel wrote:
>> Hi Andrew,
>>
>> On Mon, Oct 14, 2013 at 9:29 PM, Andrew Jones wrote:
>> > This is a virtio version of hw/misc/debugexit and should evolve in
On Tue, Oct 15, 2013 at 3:17 PM, Anup Patel wrote:
> On Tue, Oct 15, 2013 at 2:06 PM, Andrew Jones wrote:
>> On Tue, Oct 15, 2013 at 12:26:10PM +0530, Anup Patel wrote:
>>> Hi Andrew,
>>>
>>> On Mon, Oct 14, 2013 at 9:29 PM, Andrew Jones wrote:
>&
On Tue, Oct 15, 2013 at 4:08 PM, Gleb Natapov wrote:
> On Tue, Oct 15, 2013 at 11:14:12AM +0100, Peter Maydell wrote:
>> On 15 October 2013 10:47, Anup Patel wrote:
>> > On Tue, Oct 15, 2013 at 2:06 PM, Andrew Jones wrote:
>> >> I'm not opposed to it, but at t
On Mon, Feb 16, 2015 at 2:43 PM, Jan Kiszka wrote:
> Hi,
>
> next issue related to KVM/QEMU on the TK1: The guest image I'm running
> gives proper framebuffer output when in emulation mode. Once KVM is
> enabled, the screen is - at best - only initially updated. Sometimes I
> see the famous tux im
We should be able to cross compile QEMU for ARM64 host.
This is required for trying out ARM 32-bit guest on ARM64 host using QEMU + KVM
ARM64.
Signed-off-by: Anup Patel
---
configure |5 +
1 file changed, 5 insertions(+)
diff --git a/configure b/configure
index fe18ed2..0bfb8bb
On 8 January 2013 17:38, Peter Maydell wrote:
> On 8 January 2013 11:05, Anup Patel wrote:
> > diff --git a/configure b/configure
> > index fe18ed2..0bfb8bb 100755
> > --- a/configure
> > +++ b/configure
> > @@ -366,6 +366,8 @@ elif check_define __s390__ ; then
name (ie what comes out in the
qemu-foo and qemu-system-foo binary names) we generally use
the same name that 'uname -m' produces on those machines. In
this case that would be "aarch64".
Signed-off-by: Anup Patel
---
configure |5 +
1 file changed, 5 insertions(+)
diff
Public bug reported:
ARMv7a has lot of undefined instruction from its instruction opcode
space. This undefined instructions are very useful for replacing
sensitive non-priviledged instructions of guest operating systems
(virtualization). The undefined instruction exception executes at
+ 0x4, wher
Hi,
You are right, I have deliberately used an instruction from a "permanently
UNDEF" space. I have used this instruction because thats this are the only
UNDEF instructions with maximum payload of 20 bits.
Also, the instruction "0xec019800" does not belong to STC instruction space.
GNU object dum
Hi
The correct command to launch qemu will be: ./qemu-system-arm -s -S -M
realview-pb-a8 -serial stdio -kernel arm_test.elf
Sorry, for mistake in previous mail.
--Anup
On Tue, Apr 12, 2011 at 3:48 PM, Anup Patel
wrote:
> Hi,
>
> You are right, I have deliberately used an instructi
Actually, the undefined instruction that I have used is documented as
undefined at two places in "ARM Instruction Set Encoding" section of ARMv7a
reference manual:
1. Refer "Table A5-22 Supervisor Call, and coprocessor instructions"
2. Refer "A8.6.188 STC, STC2"
So you see one can easily get confu
Also, in the test case hits 0x8 after encountering UNDEF instruction at
0x100058.
The test case is not broken it failed in initialization sequence itself.
PS: I had download most recent version of QEMU 0.14.0 and build it my
self.
On Tue, Apr 12, 2011 at 4:33 PM, Anup Patel
wrote:
> Actua
I see 0x0008 ().
I am using qemu-0.14.0.tar.gz available for QEMU Downloads.
--Anup
On Tue, Apr 12, 2011 at 5:12 PM, Peter Maydell
wrote:
> > Also, in the test case hits 0x8 after encountering UNDEF instruction
> at 0x100058.
>
> So if you run qemu like this:
> qemu-system-arm -M realview-p
debugging using :1234
0x0010 in ?? ()
(gdb) si
0x00100054 in ?? ()
(gdb) si
0x00100054 in ?? ()
(gdb) si
0x0008 in ?? ()
(I expect it to jump to 0x0004 after 0x00100054)
--Anup
On Tue, Apr 12, 2011 at 5:40 PM, Anup Patel
wrote:
> I see 0x0008 ().
>
> I am using qemu-0.14
Hi,
Were you able to replicate the problem with the steps that I had mentioned ?
The key thing is is if you don't set breakpoint at 0x4 or 0x8 just follow
the execution flow using "si" command of GDB.
You will definitely hit the problem.
--Anup
On Tue, Apr 12, 2011 at 5:57 PM, A
I think you are right. This seems to be more of a GDB issue.
Any ways thanks for your support.
--Anup
On Wed, Apr 13, 2011 at 5:24 PM, Peter Maydell
wrote:
> > Were you able to replicate the problem with the steps that I had
> mentioned ?
> > The key thing is is if you don't set breakpoint at 0
Public bug reported:
target-arm/helper.c:920
[current] table |= (address >> 18) & 0x3ffc
[fix] table |= (address >> 20) & 0xfff
** Affects: qemu
Importance: Undecided
Status: New
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed
Hi Alistair,
On Tue, Nov 8, 2022 at 6:27 PM Anup Patel wrote:
>
> This series mainly includes fixes discovered while developing nested
> virtualization running on QEMU.
>
> These patches can also be found in the riscv_nested_fixes_v2 branch at:
> https://github.com/avpatel/qe
hypervisor slow and
also breaks nested virtualization.
Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc")
Signed-off-by: Anup Patel
---
target/riscv/insn_trans/trans_privileged.c.inc | 4
target/riscv/insn_trans/trans_rvh.c.inc| 2 --
target/riscv/
On Wed, Jul 27, 2022 at 9:24 AM Richard Henderson
wrote:
>
> On 7/26/22 20:25, Anup Patel wrote:
> > We should call decode_save_opc() for every decoded instruction
> > because generating transformed instruction upon guest page faults
> > expects opcode to be available.
On Wed, Aug 3, 2022 at 6:16 PM Weiwei Li wrote:
>
> Normally, riscv_csrrw_check is called when executing Zicsr instructions.
> And we can only do access control for existed CSRs. So the priority of
> CSR related check, from highest to lowest, should be as follows:
> 1) check whether Zicsr is suppo
On Thu, Aug 4, 2022 at 5:59 PM Weiwei Li wrote:
>
>
> 在 2022/8/4 上午11:38, Anup Patel 写道:
> > On Wed, Aug 3, 2022 at 6:16 PM Weiwei Li wrote:
> >> Normally, riscv_csrrw_check is called when executing Zicsr instructions.
> >> And we can only do access control for
t; > On Fri, Jul 14, 2023 at 10:00:19AM +0530, Anup
On Wed, Jul 19, 2023 at 3:23 PM Alistair Francis wrote:
>
> On Wed, Jul 19, 2023 at 3:39 PM Anup Patel wrote:
> >
> > On Wed, Jul 19, 2023 at 7:03 AM Alistair Francis
> > wrote:
> > >
> > > On Sat, Jul 15, 2023 at 7:14 PM Atish Patra wrote:
>
Hi Bin,
On Wed, Jul 19, 2023 at 9:15 PM Bin Meng wrote:
>
> On Wed, Jul 19, 2023 at 11:22 PM Anup Patel wrote:
> >
> > On Wed, Jul 19, 2023 at 3:23 PM Alistair Francis
> > wrote:
> > >
> > > On Wed, Jul 19, 2023 at 3:39 PM Anup Patel wrote:
>
On Thu, Feb 29, 2024 at 8:42 PM Andrew Jones wrote:
>
> On Thu, Feb 29, 2024 at 07:07:43PM +0530, Himanshu Chauhan wrote:
> > All the CPUs may or may not implement the debug triggers (sdtrig)
> > extension. The presence of it should be dynamically detectable.
> > This patch exports the debug trigg
d RISC-V AIA APLIC device emulation")
Signed-off-by: Anup Patel
---
hw/intc/riscv_aplic.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index e98e258deb..775bb96164 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw
lue = (incoming wire value) XOR (source is inverted)"
Update the riscv_aplic_read_input_word() implementation to match the above.
Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation")
Signed-off-by: Anup Patel
---
hw/intc/riscv_aplic.c | 17 +++--
1 fil
Few fixes for RISC-V APLIC discovered during Linux AIA patch reviews.
These patches can also be found in the apatel_aplic_fixes_v1 branch at:
https://github.com/avpatel/qemu.git
Anup Patel (2):
hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC
MSI-mode
hw/intc/riscv_aplic
On Mon, Feb 5, 2024 at 9:36 AM Alistair Francis wrote:
>
> On Mon, Jan 22, 2024 at 7:16 PM Andrew Jones wrote:
> >
> > On Mon, Jan 22, 2024 at 03:42:10PM +1000, Alistair Francis wrote:
> > > > > From memory the "debug" property is for the original debug spec:
> > > > > https://github.com/riscv/ri
aud??
(Refer, https://patchew.org/QEMU/20191003230404.19384-1-phi...@redhat.com/)
Changes since v1:
- Implemented VMState save/restore for Goldfish RTC
Anup Patel (2):
hw: timer: Add Goldfish RTC device
riscv: virt: Use Goldfish RTC device
hw/riscv/Kconfig| 1 +
migration support is available but untested for Goldfish RTC
device. It will be hardened in-future when we implement VM migration for
KVM RISC-V.
Signed-off-by: Anup Patel
---
hw/rtc/Kconfig | 3 +
hw/rtc/Makefile.objs| 1 +
hw/rtc/goldfish_rtc.c | 278
We extend QEMU RISC-V virt machine by adding Goldfish RTC device
to it. This will allow Guest Linux to sync it's local date/time
with Host date/time via RTC device.
Signed-off-by: Anup Patel
---
hw/riscv/Kconfig| 1 +
hw/riscv/virt.c | 15 +++
include/hw/
> -Original Message-
> From: Alistair Francis
> Sent: Saturday, October 19, 2019 2:29 AM
> To: Anup Patel
> Cc: Peter Maydell ; Palmer Dabbelt
> ; Alistair Francis ; Sagar
> Karandikar ; Bastian Koppelmann
> ; Atish Patra ;
> qemu-ri...@nongnu.org; qemu-d
Hi,
From: Aleksandar Markovic
Sent: Saturday, October 19, 2019 2:45 AM
To: Anup Patel
Cc: Peter Maydell ; Palmer Dabbelt
; Alistair Francis ; Sagar
Karandikar ; Bastian Koppelmann
; Atish Patra ;
qemu-ri...@nongnu.org; qemu-devel@nongnu.org; Anup Patel
Subject: Re: [PATCH v3 1/2] hw
We extend QEMU RISC-V virt machine by adding Goldfish RTC device
to it. This will allow Guest Linux to sync it's local date/time
with Host date/time via RTC device.
Signed-off-by: Anup Patel
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
---
hw/
Rebased on RTC code refactoring
Changes since v1:
- Implemented VMState save/restore callbacks
Anup Patel (2):
hw: rtc: Add Goldfish RTC device
riscv: virt: Use Goldfish RTC device
hw/riscv/Kconfig| 1 +
hw/riscv/virt.c | 15 ++
hw/rtc/Kconfig
migration support is available but untested for Goldfish RTC
device. It will be hardened in-future when we implement VM migration for
KVM RISC-V.
Signed-off-by: Anup Patel
---
hw/rtc/Kconfig | 3 +
hw/rtc/Makefile.objs| 1 +
hw/rtc/goldfish_rtc.c | 288
This patch extends Spike machine support to allow loading OpenSBI
firmware (fw_jump.elf) separately using -bios option.
Signed-off-by: Anup Patel
---
hw/riscv/spike.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
This series improves QEMU Spike machine to:
1. Allow loading OpenBI firmware using -bios option
2. Allow more than one CPUs
Anup Patel (3):
hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
hw/riscv/spike: Allow loading firmware separately using -bios option
hw/riscv/spike
Currently, the upstream Spike ISA simulator allows more than
one CPUs so we update QEMU Spike machine on similar lines to
allow more than one CPUs.
The maximum number of CPUs for QEMU Spike machine is kept
same as QEMU Virt machine.
Signed-off-by: Anup Patel
---
hw/riscv/spike.c | 2 +-
1 file
mbols from firmware ELF
passed via "-bios" option.
Signed-off-by: Anup Patel
---
hw/riscv/boot.c | 13 -
hw/riscv/sifive_u.c | 2 +-
hw/riscv/virt.c | 2 +-
include/hw/riscv/boot.h | 6 --
4 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/
On Fri, Feb 21, 2020 at 8:08 AM Bin Meng wrote:
>
> Hi Philippe,
>
> On Fri, Feb 21, 2020 at 1:31 AM Philippe Mathieu-Daudé
> wrote:
> >
> > Hi Bin,
> >
> > On 2/20/20 3:42 PM, Bin Meng wrote:
> > > Although the real world SiFive HiFive Unleashed board is a 64-bit
> > > hardware configuration, wi
Hi Alistair,
On Tue, Jan 3, 2023 at 9:43 PM Anup Patel wrote:
>
> Hi Alistair,
>
> On Wed, Dec 28, 2022 at 11:08 AM Alistair Francis
> wrote:
> >
> > On Fri, Dec 23, 2022 at 11:14 PM Anup Patel wrote:
> > >
> > > On Thu, Dec 15, 2
riscv-to-apply.next branch of Alistair
Changes since v1:
- Added Alistair's Reviewed-by tags to appropriate patches
- Added detailed comment block in PATCH4
Anup Patel (4):
target/riscv: Update VS timer whenever htimedelta changes
target/riscv: Don't clear mask in riscv_cpu_update
as zero in htinst CSR for guest MMIO emulation
which makes MMIO emulation in hypervisor slow and also breaks nested
virtualization.
Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc")
Signed-off-by: Anup Patel
---
target/riscv/insn_trans/trans_rva.c.in
The time CSR will wrap-around immediately after reaching UINT64_MAX
so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
in riscv_timer_write_timecmp().
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/time_helper.c | 24
1
Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
for VSTIP.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/cp
The htimedelta[h] CSR has impact on the VS timer comparison so we
should call riscv_timer_write_timecmp() whenever htimedelta changes.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/
On Tue, Jun 28, 2022 at 4:48 AM Alistair Francis wrote:
>
> On Thu, Jun 9, 2022 at 1:31 PM Anup Patel wrote:
> >
> > We should write transformed instruction encoding of the trapped
> > instruction in [m|h]tinst CSR at time of taking trap as defined
> > by the R
On Tue, Jun 28, 2022 at 4:47 AM Alistair Francis wrote:
>
> On Sat, Jun 11, 2022 at 6:07 PM Anup Patel wrote:
> >
> > We should disable extensions in riscv_cpu_realize() if minimum required
> > priv spec version is not satisfied. This also ensures that machines with
>
rap write_gva is true only for HLV/HSV
instructions
- Included "[PATCH 0/3] QEMU RISC-V priv spec version fixes"
patches in this series for easy review
- Re-worked PATCH7 to force disable extensions if required
priv spec version is not staisfied
- Added new PATCH8 to fix "
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 5 +
target/riscv/cpu_helper.c
gs to the device
tree")
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
Signed-off-by: Rahul Pathak
---
target/riscv/cpu.c | 150 -
1 file changed, 94 insertions(+), 56 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/c
This reverts commit 33cc1c0b69e457f5c526f64297353cba6f7bfdb4 because
commit eab4776b2badd4088a4f807c9bb3dc453c53dc23 already implements
proper mcountinhibit CSR emulation.
Signed-off-by: Anup Patel
---
target/riscv/cpu_bits.h | 3 ---
target/riscv/csr.c | 2 --
2 files changed, 5 deletions
The minimum priv spec versino for mcountinhibit to v1.11 so that it
is not available for v1.10 (or lower).
Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents")
Signed-off-by: Anup Patel
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
On Mon, Jun 27, 2022 at 10:25 PM dramforever wrote:
>
> On 6/27/22 09:00, Alistair Francis wrote:
> > On Sat, Jun 11, 2022 at 6:06 PM Anup Patel wrote:
> >> We should write transformed instruction encoding of the trapped
> >> instruction in [m|h]tinst CSR at
This reverts commit 33cc1c0b69e457f5c526f64297353cba6f7bfdb4 because
commit eab4776b2badd4088a4f807c9bb3dc453c53dc23 already implements
proper mcountinhibit CSR emulation.
Signed-off-by: Anup Patel
---
target/riscv/cpu_bits.h | 3 ---
target/riscv/csr.c | 2 --
2 files changed, 5 deletions
gs to the device
tree")
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
Signed-off-by: Rahul Pathak
---
target/riscv/cpu.c | 150 -
1 file changed, 94 insertions(+), 56 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/c
priv spec version is not staisfied
- Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine
Anup Patel (4):
Revert "target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11
or higher"
target/riscv: Set minumum priv spec version for mcountinhibit
target/
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 5 +
target/riscv/cpu_helper.c
The minimum priv spec versino for mcountinhibit to v1.11 so that it
is not available for v1.10 (or lower).
Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents")
Signed-off-by: Anup Patel
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
On Wed, Jun 29, 2022 at 9:27 AM Bin Meng wrote:
>
> Hi Rahul,
>
> On Wed, Jun 29, 2022 at 10:07 AM Rahul Pathak
> wrote:
> >
> > Hi Alistair
> >
> > My fix patch needs to be dropped since Anup took care of this issue
> > in his yesterdays series update in this patch -
> > [PATCH v8 4/4] target/r
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 5 +
target/riscv/cpu_helper.c
gs to the device
tree")
Reviewed-by: Alistair Francis
Signed-off-by: Anup Patel
Signed-off-by: Rahul Pathak
---
target/riscv/cpu.c | 150 -
1 file changed, 94 insertions(+), 56 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/c
priv spec version is not staisfied
- Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine
Anup Patel (2):
target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
target/riscv: Force disable extensions if priv spec version does not
match
target/riscv/cpu.c
On Thu, Jun 30, 2022 at 11:42 AM Anup Patel wrote:
>
> This series does fixes and improvements to have nested virtualization
> on QEMU RISC-V.
>
> These patches can also be found in riscv_nested_fixes_v9 branch at:
> https://github.com/avpatel/qemu.git
>
> The RISC-V n
On Mon, Jul 4, 2022 at 2:59 AM Stafford Horne wrote:
>
> Add an endianness property to allow configuring the RTC as either
> native, little or big endian.
>
> Cc: Laurent Vivier
> Signed-off-by: Stafford Horne
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anu
te.
>
> Signed-off-by: Ivan Klokov
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> hw/intc/riscv_aplic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index cfd007e629..71591
On Mon, Mar 13, 2023 at 7:49 AM Hang Xu wrote:
>
> Because the starting address of ram is not necessarily 0,
> the remaining free space in ram is
> ram_size - (start - ram_base) instead of ram_size-start.
>
> Signed-off-by: Hang Xu
What happens in-case a platform has multiple RAM banks ?
Regard
ko Stubner
> Signed-off-by: Atish Patra
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> Changes from v2->v3:
> 1. Used g_strconcat to replace snprintf & a max isa string length as
> suggested by Anup.
> 2. I have not included the Tested-by Tag from
On Fri, Mar 4, 2022 at 8:50 AM Atish Patra wrote:
>
> Currently, the aclint and ibex timer devices uses the "timer" &
> "timecmp" to generate the m-mode timer interrupt. In future,
> we will have timer interrupt injected to S/VS mode directly.
> No functionality change introduced in this patch.
s
On Tue, Aug 31, 2021 at 4:36 PM Anup Patel wrote:
>
> The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement
> over the SiFive CLINT but also maintains backward compatibility with
> the SiFive CLINT.
>
> Latest RISC-V ACLINT specification (will be frozen soo
On Wed, Sep 29, 2021 at 9:52 AM Alistair Francis wrote:
>
> On Wed, Sep 29, 2021 at 2:09 PM Anup Patel wrote:
> >
> > On Tue, Aug 31, 2021 at 4:36 PM Anup Patel wrote:
> > >
> > > The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement
On Fri, Jan 28, 2022 at 7:24 AM Alistair Francis wrote:
>
> On Thu, Jan 20, 2022 at 1:55 AM Anup Patel wrote:
> >
> > From: Anup Patel
> >
> > The RISC-V AIA (Advanced Interrupt Architecture) defines a new
> > interrupt controller for MSIs (message signal in
From: Anup Patel
The advanced interrupt architecture (AIA) extends the per-HART local
interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
and Advanced PLIC (wired interrupt controller).
The latest AIA draft specification can be found here:
https://github.com/riscv/riscv-aia
From: Anup Patel
We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Reviewed-by
From: Anup Patel
The guest external interrupts from an interrupt controller are
delivered only when the Guest/VM is running (i.e. V=1). This means
any guest external interrupt which is triggered while the Guest/VM
is not running (i.e. V=0) will be missed on QEMU resulting in Guest
with sluggish
From: Anup Patel
The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
---
target/riscv/cpu.h| 14 +-
target
From: Anup Patel
The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example
From: Anup Patel
The AIA specification defines IMSIC interface CSRs for easy access
to the per-HART IMSIC registers without using indirect xiselect and
xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Frank Chang
From: Anup Patel
The AIA hvictl and hviprioX CSRs allow hypervisor to control
interrupts visible at VS-level. This patch implements AIA hvictl
and hviprioX CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
---
target/riscv
From: Anup Patel
The AIA specificaiton adds interrupt filtering support for M-mode
and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
take local interrupt 13 or above and selectively inject same local
interrupt to lower privilege modes.
At the moment, we don't have any
From: Anup Patel
We extend virt machine to emulate AIA APLIC devices only when
"aia=aplic" parameter is passed along with machine name in QEMU
command-line. When "aia=none" or not specified then we fallback
to original PLIC device emulation.
Signed-off-by: Anup Patel
Signe
From: Anup Patel
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for MSIs (message signal interrupts) called
IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
is per-HART device and also suppport virtualizaiton of MSIs using
dedicated VS-level
From: Anup Patel
We should be returning illegal instruction trap when RV64 HS-mode tries
to access RV32 HS-mode CSR.
Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Review
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