Adds the AST2400 machine type with ASPEED AVIC and timer models. The
new machine type is functional enough to boot Linux to userspace.
Signed-off-by: Andrew Jeffery
---
hw/arm/Makefile.objs | 1 +
hw/arm/ast2400.c | 139 +++
trace-events
ed_timer.c:
* Refactor initialisation of and respect requested clock rates (APB/External)
* Simplify some index calculations
===
Andrew Jeffery (3):
hw/timer: Add ASPEED AST2400 timer device model
hw/intc: Add (new) ASPEED AST2400 AVIC device model
hw/arm: Add ASPEED AST2400 machine type
aspeed_defconfig.
Signed-off-by: Andrew Jeffery
---
default-configs/arm-softmmu.mak | 2 +
hw/timer/Makefile.objs | 2 +
hw/timer/aspeed_timer.c | 313
include/hw/timer/aspeed_timer.h | 55 +++
trace-events| 9
ons process the provided offset to understand
whether the access is requesting the lower or upper 32bits of the 64bit
quantity.
Signed-off-by: Andrew Jeffery
---
hw/intc/Makefile.objs| 1 +
hw/intc/aspeed_vic.c | 256 +++
include/hw/intc/asp
Hi Peter,
On Thu, 2016-02-25 at 16:11 +, Peter Maydell wrote:
> On 16 February 2016 at 11:34, Andrew Jeffery wrote:
> > Implement basic AST2400 timer functionality: Timers can be configured,
> > enabled, reset and disabled.
> >
> > A number of hardware f
On Fri, 2016-02-26 at 10:20 +, Peter Maydell wrote:
> On 26 February 2016 at 03:14, Andrew Jeffery wrote:
> >
> > Hi Peter,
> >
> > On Thu, 2016-02-25 at 16:11 +, Peter Maydell wrote:
> > >
> > > On 16 February 2016 at 11:34, Andrew Jef
Hi Peter,
On Thu, 2016-02-25 at 16:29 +, Peter Maydell wrote:
> On 16 February 2016 at 11:34, Andrew Jeffery wrote:
> > Implement a minimal ASPEED AVIC device model, enough to boot a Linux
> > kernel configured with aspeed_defconfig. The VIC implements the 'new&#
On Thu, 2016-02-25 at 16:29 +, Peter Maydell wrote:
> > +case 0x20: /* Interrupt Enable */
> > +s->int_enable |= data;
>
> Are you sure this only ORs in new 1 bits?
As in, am I sure I only want to take the newly set bits? If so, yes, as
the the following register serves to clear t
On Thu, 2016-03-03 at 08:39 +, Peter Maydell wrote:
> On 3 March 2016 at 05:14, Andrew Jeffery wrote:
> >
> > On Thu, 2016-02-25 at 16:29 +, Peter Maydell wrote:
> > >
> > > >
> > > > +case 0x20: /* Interrupt Enable */
> > >
* Peter Maydell
* Alexey Kardashevskiy
* Joel Stanley
Changes since v1:
Addressed reviews/comments from:
* Cédric Le Goater
Andrew Jeffery (3):
hw/timer: Add ASPEED timer device model
hw/intc: Add (new) ASPEED VIC device model
hw/arm: Add ASPEED AST2400 machine model
default-co
=376
Signed-off-by: Andrew Jeffery
---
Since v2:
* Implement a SOC model to move code out from the machine definition
* Rework the machine to better use QOM
* Include qemu/osdep.h
* Revert back to qemu_log_mask(LOG_UNIMP, ...) in IO handlers
Since v1:
hw/arm/Makefile.objs | 1 +
hw
ed (though the access will be logged).
Signed-off-by: Andrew Jeffery
---
Since v2:
* Implement all supported interrupt types and configurations
* Implement a VMStateDescription
* Log accesses to legacy IO space
* Add documentation on some implementation and hardware details
* Switch to
aspeed_defconfig.
Signed-off-by: Andrew Jeffery
---
Since v2:
* Improve handling of timer configuration with respect to enabled state
* Remove redundant enabled member from AspeedTimer
* Implement VMStateDescriptions
* Fix interrupt behaviour (edge triggered, both edges)
* Fix various
On Fri, 2016-03-11 at 15:56 +0700, Peter Maydell wrote:
> On 5 March 2016 at 11:29, Andrew Jeffery wrote:
> > Implement basic AST2400 timer functionality: Up to 8 timers can
> > independently be configured, enabled, reset and disabled. A couple of
> > hardware features are no
On Fri, 2016-03-11 at 16:03 +0700, Peter Maydell wrote:
> On 5 March 2016 at 11:29, Andrew Jeffery wrote:
> > Implement a basic ASPEED VIC device model, enough to boot a Linux kernel
> > configured with aspeed_defconfig. The model implements the 'new'
> > (revi
While the ASPEED AST2400 SoC[1] has a broad range of capabilities this
implementation is minimal, comprising an ARM926 processor, ASPEED VIC
and timer devices, and a 8250 UART.
[1] http://www.aspeedtech.com/products.php?fPath=20&rId=376
Signed-off-by: Andrew Jeffery
---
Since v3:
* Split
* Alexey Kardashevskiy
* Joel Stanley
Changes since v1:
Addressed reviews/comments from:
* Cédric Le Goater
Andrew Jeffery (4):
hw/timer: Add ASPEED timer device model
hw/intc: Add (new) ASPEED VIC device model
hw/arm: Add an ASPEED AST2400 SoC
hw/arm: Add opbmc2400, an AST2400-based Open
cy
register set will not be serviced (however the access will be logged).
[1] http://www.aspeedtech.com/products.php?fPath=20&rId=376
Signed-off-by: Andrew Jeffery
---
Since v3:
* Switch from g_assert() to qemu_log_mask(LOG_GUEST_ERROR, ...) in guest path
Since v2:
* Implement all suppor
ar to be a
common, formal name for the hardware configuration that isn't generic
(e.g. 'BMC' or 'AST2400').
[1] http://www.aspeedtech.com/products.php?fPath=20&rId=376
Signed-off-by: Andrew Jeffery
---
Since v3:
* Split the machine from the SoC implementation
configured with aspeed_defconfig.
[1] http://www.aspeedtech.com/products.php?fPath=20&rId=376
Signed-off-by: Andrew Jeffery
---
Since v3:
* Drop unnecessary mention of VMStateDescription in timer_to_ctrl description
* Mention hw/timer/a9gtimer.c with respect to clock value matching
*
On Tue, 2016-03-15 at 12:34 +0800, Jeremy Kerr wrote:
> Hi Andrew,
>
> > This patch series models enough of the ASPEED AST2400 ARM9 SoC[0] to
> > boot an aspeed_defconfig Linux kernel[1][2]. Specifically, the series
> > implements the ASPEED timer and VIC devices, integrates them into an
> > AST24
Hi Dmitry,
On Tue, 2016-03-15 at 21:14 +0300, Dmitry Osipenko wrote:
> Hello Andrew,
>
> 14.03.2016 07:13, Andrew Jeffery пишет:
> > Implement basic ASPEED timer functionality for the AST2400 SoC[1]: Up to
> > 8 timers can independently be configured, enabled, reset a
On Tue, 2016-03-15 at 14:14 +0100, Cédric Le Goater wrote:
> On 03/14/2016 05:13 AM, Andrew Jeffery wrote:
> > Implement basic ASPEED timer functionality for the AST2400 SoC[1]: Up to
> > 8 timers can independently be configured, enabled, reset and disabled.
> > Some hard
On Tue, 2016-03-15 at 11:25 +0100, Cédric Le Goater wrote:
> On 03/15/2016 06:01 AM, Andrew Jeffery wrote:
> > On Tue, 2016-03-15 at 12:34 +0800, Jeremy Kerr wrote:
> > > Hi Andrew,
> > >
> > > > This patch series models enough of the ASPEED AST2400 ARM9 SoC
While the ASPEED AST2400 SoC[1] has a broad range of capabilities this
implementation is minimal, comprising an ARM926 processor, ASPEED VIC
and timer devices, and a 8250 UART.
[1] http://www.aspeedtech.com/products.php?fPath=20&rId=376
Signed-off-by: Andrew Jeffery
---
Since v3:
* Split
cy
register set will not be serviced (however the access will be logged).
[1] http://www.aspeedtech.com/products.php?fPath=20&rId=376
Signed-off-by: Andrew Jeffery
---
Since v3:
* Switch from g_assert() to qemu_log_mask(LOG_GUEST_ERROR, ...) in guest path
Since v2:
* Implement all suppor
Changes since v1:
Addressed reviews/comments from:
* Cédric Le Goater
Andrew Jeffery (4):
hw/timer: Add ASPEED timer device model
hw/intc: Add (new) ASPEED VIC device model
hw/arm: Add ASPEED AST2400 SoC model
hw/arm: Add palmetto-bmc machine
default-configs/arm-softmmu.mak | 1
0 SoC), but creating specific machine types is preferable
to a generic machine that doesn't match any particular hardware.
[1] http://www.aspeedtech.com/products.php?fPath=20&rId=376
Signed-off-by: Andrew Jeffery
---
Since v4:
* Rename to hw/arm/palmetto-bmc.c, update functions, struc
configured with aspeed_defconfig.
[1] http://www.aspeedtech.com/products.php?fPath=20&rId=376
Signed-off-by: Andrew Jeffery
---
Since v4:
* Fix to compile when using GCC 4.x
* Drop unnecessary asserts
Since v3:
* Drop unnecessary mention of VMStateDescription in timer_to_ctrl descrip
Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the
palmetto-bmc machine. Two match registers are provided for each timer.
Signed-off-by: Andrew Jeffery
---
The change pulls out ptimer in favour of the regular timer infrastructure. As a
consequence it implements the conversions
On Mon, 2016-06-06 at 15:01 +0100, Peter Maydell wrote:
> On 27 May 2016 at 06:08, Andrew Jeffery wrote:
> >
> > Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the
> > palmetto-bmc machine. Two match registers are provided for each timer.
> >
> &
On Thu, 2016-06-09 at 19:15 +0100, Peter Maydell wrote:
> On 27 May 2016 at 06:08, Andrew Jeffery wrote:
> >
> > Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the
> > palmetto-bmc machine. Two match registers are provided for each timer.
> >
> &
On Fri, 2016-06-10 at 11:42 +0100, Peter Maydell wrote:
> On 10 June 2016 at 01:59, Andrew Jeffery wrote:
> >
> > On Thu, 2016-06-09 at 19:15 +0100, Peter Maydell wrote:
> > >
> > > On 27 May 2016 at 06:08, Andrew Jeffery wrote:
> > > >
> &g
Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the
palmetto-bmc machine. Two match registers are provided for each timer.
Signed-off-by: Andrew Jeffery
---
Since v1: Address comments from Peter
* Switch calculations to use muldiv64()
* Switch to loops when calculating the next
of the state to determine how to boot, but the
reset values vary from SoC to SoC. qdev properties are exposed so that
the integrating SoC model can configure the appropriate reset values.
Signed-off-by: Andrew Jeffery
Reviewed-by: Cédric Le Goater
Reviewed-by: Joel Stanley
---
hw/misc
Almost all configured reset values are specified by the datasheet. The
notable exception is ASPEED_SCU_SOC_SCRATCH1, where we mark the DRAM as
successfully initialised by the SoC to avoid unnecessary dark corners in
the SoC's u-boot support.
Signed-off-by: Andrew Jeffery
Reviewed-by: Cédr
of the software and the
software's configuration of the SoC.
Cheers,
Andrew
Andrew Jeffery (2):
hw/misc: Add a model for the ASPEED System Control Unit
ast2400: Integrate the SCU model and configure reset values
hw/arm/ast2400.c | 57 +
hw/misc/Makefile
On Fri, 2016-06-17 at 15:22 +0100, Peter Maydell wrote:
On 16 June 2016 at 08:48, Andrew Jeffery wrote:
The SCU is a collection of chip-level control registers that manage the
various functions supported by the AST2400. Typically the bits control
interactions with clocks, external hardware or
On Mon, 2016-06-20 at 14:57 +0100, Peter Maydell wrote:
> On 20 June 2016 at 04:44, Andrew Jeffery wrote:
> >
> > On Fri, 2016-06-17 at 15:22 +0100, Peter Maydell wrote:
> > >
> > > +static Property aspeed_scu_properties[] = {
> > > +DEFINE_PROP
On Tue, 2016-06-21 at 07:56 +0100, Peter Maydell wrote:
> On 21 June 2016 at 04:49, Andrew Jeffery wrote:
> >
> > On Mon, 2016-06-20 at 14:57 +0100, Peter Maydell wrote:
> > >
> > > I think there are a couple of plausible ways you might model this:
> > &
, influencing the configuration of the
software and the software's configuration of the SoC.
Since v1:
* Select reset values based on silicon ID
* Expose hardware strapping values via properties
Cheers,
Andrew
Andrew Jeffery (3):
hw/misc: Add a model for the ASPEED System Control Unit
as
igned-off-by: Andrew Jeffery
---
Since v1:
* Move reset values into SCU implementation (also make register defines private)
* Expose silicon-rev property which is used to select appropriate reset values
* Expose hw-strap1/hw-strap2 properties for board-specific SoC configuration
hw/misc/Makefile
By specifying the silicon revision we select the appropriate reset
values for the SoC.
Additionally, expose hardware strapping properties aliasing those
provided by the SCU for board-specific configuration.
Signed-off-by: Andrew Jeffery
---
Since v1:
* Remove reset value configuration
: Configure MAC#2 for RMII/NCSI
* 6: Configure MAC#1 for RMII/NCSI
* 5: No VGA BIOS ROM
* 4: Boot using 32bit SPI address mode
* 3:2: Select 16MB VGA memory
* 1:0: Boot from SPI flash memory
Signed-off-by: Andrew Jeffery
---
hw/arm/palmetto-bmc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
On Thu, 2016-06-23 at 18:37 +0100, Peter Maydell wrote:
> On 23 June 2016 at 03:15, Andrew Jeffery wrote:
> >
> > The SCU is a collection of chip-level control registers that manage the
> > various functions supported by ASPEED SoCs. Typically the bits control
> &g
On Thu, 2016-06-23 at 18:42 +0100, Peter Maydell wrote:
> On 23 June 2016 at 03:15, Andrew Jeffery wrote:
> >
> > The SCU is a collection of chip-level control registers that manage the
> > various functions supported by ASPEED SoCs. Typically the bits control
> &g
On Thu, 2016-06-23 at 18:39 +0100, Peter Maydell wrote:
> On 23 June 2016 at 03:15, Andrew Jeffery wrote:
> >
> > The magic constant configures the following options:
> >
> > * 28:27: Configure DRAM size as 256MB
> > * 26:24: DDR3 SDRAM with CL = 6, CWL = 5
&
xpose hardware strapping values via properties
Andrew Jeffery (3):
hw/misc: Add a model for the ASPEED System Control Unit
ast2400: Integrate the SCU model and set silicon revision
palmetto-bmc: Configure the SCU's hardware strapping register
hw/arm/ast2400.c | 21
hw/ar
igned-off-by: Andrew Jeffery
---
Since v2:
* Fix mixing of offsets and register indexes
* Sanity check device property values
* Move trace event definition to hw/misc/trace-events
Since v1:
* Move reset values into SCU implementation (also make register defines private)
* Expose silicon-rev pro
By specifying the silicon revision we select the appropriate reset
values for the SoC.
Additionally, expose hardware strapping properties aliasing those
provided by the SCU for board-specific configuration.
Signed-off-by: Andrew Jeffery
Reviewed-by: Cédric Le Goater
Reviewed-by: Peter Maydell
: Configure MAC#2 for RMII/NCSI
* 6: Configure MAC#1 for RMII/NCSI
* 5: No VGA BIOS ROM
* 4: Boot using 32bit SPI address mode
* 3:2: Select 16MB VGA memory
* 1:0: Boot from SPI flash memory
Signed-off-by: Andrew Jeffery
Reviewed-by: Cédric Le Goater
Reviewed-by: Peter Maydell
---
hw/arm
WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not
Hi Cédric,
On Fri, 2016-05-20 at 18:31 +0200, Cédric Le Goater wrote:
> Largely inspired by the TMP105 temperature sensor, this patch brings
> to Qemu a model for TMP42{1,2,3} temperature sensors.
>
> Specs can be found here :
>
> http://www.ti.com/lit/gpn/tmp421
>
> Signed-off-by: Cédric
On Mon, 2016-05-23 at 07:55 +0200, Cédric Le Goater wrote:
> >
> > The hunk fails to apply to master as the SCU isn't yet integrated
> > there. The change to ast2400.h also fails to apply for this reason.
>
> Ah yes. I am using your branch for this patch.
>
> So, I will provide you a fix for "q
On Fri, 22 Jul 2022, at 16:06, Cédric Le Goater wrote:
> A mx25l25635f chip model is generally found on these machines. It's
> newer and uses 4B opcodes which is better to exercise the support in
> the Linux kernel.
>
> Signed-off-by: Cédric Le Goater
> ---
> hw/arm/aspeed.c | 6 +++---
> 1 fi
On Mon, 25 Jul 2022, at 16:02, Cédric Le Goater wrote:
> On 7/25/22 04:08, Andrew Jeffery wrote:
>>
>>
>> On Fri, 22 Jul 2022, at 16:06, Cédric Le Goater wrote:
>>> aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
>>> mc-&
On Sun, 31 Jul 2022, at 06:48, Cédric Le Goater wrote:
> On 7/29/22 19:30, Peter Delevoryas wrote:
>> Certainly we'd like to use IRQ's instead, but she ran into correctness
>> problems. Maybe we can investigate that further and fix it.
Yes, let's not work around problems that we have the abilit
Goater
Acked-by: Andrew Jeffery
Joel Stanley
Reviewed-by: Andrew Jeffery
> ---
> hw/arm/aspeed.c | 6 ++
> include/hw/arm/aspeed.h | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 1c23ebd99252..3f3d4162b3c5 100644
> --- a/hw/arm/aspe
638-1-cr...@redhat.com>
> > https://lists.gnu.org/archive/html/qemu-devel/2019-03/msg03881.html
> >
> > * Maybe identify a few machines we don't know how to boot anymore.
> >
> > Thanks in advance for your help!
> >
> >
> >
> > Machi
On Thu, 6 Feb 2020, at 21:56, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
and data corruption can be
> seen on machines using two chips, witherspoon and romulus.
>
> Rework the handler setting the CEx Control Register to fix this issue.
>
> Fixes: 7c1c69bca43c ("ast2400: add SMC controllers (FMC and SPI)")
> Signed-off-by: Cédric Le Goater
Champion!
Reviewed-by: Andrew Jeffery
Hello,
The AST2600 has an additional SDHCI intended for use as an eMMC boot source.
These two patches rework the existing ASPEED SDHCI model to accommodate the
single-slot nature of the eMMC controller and wire it into the AST2600 SoC.
Please review!
Andrew
Andrew Jeffery (2):
hw/sd
sumed that the SD controller always provided two
slots. Rework the SDHCI object to expose the number of slots as a
property to be set by the SoC configuration.
Signed-off-by: Andrew Jeffery
---
hw/arm/aspeed.c | 2 +-
hw/arm/aspeed_ast2600.c | 2 ++
hw/arm/aspeed_soc.c
Initialise another SDHCI model instance for the AST2600's eMMC
controller and use the SDHCI's num_slots value introduced previously to
determine whether we should create an SD card instance for the new slot.
Signed-off-by: Andrew Jeffery
---
hw/arm/aspeed.c | 13 +++
On Tue, 10 Dec 2019, at 23:22, Cédric Le Goater wrote:
> On 10/12/2019 01:52, Andrew Jeffery wrote:
> > Initialise another SDHCI model instance for the AST2600's eMMC
> > controller and use the SDHCI's num_slots value introduced previously to
> > determine whet
On Tue, 10 Dec 2019, at 19:26, Cédric Le Goater wrote:
> On 10/12/2019 01:52, Andrew Jeffery wrote:
> > The AST2600 includes a second cut-down version of the SD/MMC controller
> > found in the AST2500, named the eMMC controller. It's cut down in the
> > sense that
On Tue, 10 Dec 2019, at 19:23, Cédric Le Goater wrote:
> On 10/12/2019 01:52, Andrew Jeffery wrote:
> > Hello,
> >
> > The AST2600 has an additional SDHCI intended for use as an eMMC boot source.
>
> Have you also considered booting the QEMU Aspeed AST2600 mach
pointed out by
Cedric.
v1 can be found here:
https://patchwork.ozlabs.org/cover/1206845/
Please review!
Andrew
Andrew Jeffery (2):
hw/sd: Configure number of slots exposed by the ASPEED SDHCI model
hw/arm: ast2600: Wire up the eMMC controller
hw/arm/aspeed.c | 27
Initialise another SDHCI model instance for the AST2600's eMMC
controller and use the SDHCI's num_slots value introduced previously to
determine whether we should create an SD card instance for the new slot.
Signed-off-by: Andrew Jeffery
---
v2:
* Extract instantiation of SD cards
sumed that the SD controller always provided two
slots. Rework the SDHCI object to expose the number of slots as a
property to be set by the SoC configuration.
Signed-off-by: Andrew Jeffery
Reviewed-by: Philippe Mathieu-Daudé
---
hw/arm/aspeed.c | 2 +-
hw/arm/aspeed_ast2600.c
: Andrew Jeffery
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
v3:
* Uninline gt_cntfrq_period_ns()
* Rename gt_cntfrq to gt_cntfrq_hz
target/arm/cpu.c| 8
target/arm/cpu.h| 5 +
target/arm/helper.c | 10 +++---
3 files changed, 20 insertions
ilure from partial renaming of gt_cntfrq_period_ns()
* Add tags from Cedric and Richard
Please review.
Andrew
Andrew Jeffery (4):
target/arm: Remove redundant scaling of nexttick
target/arm: Abstract the generic timer frequency
target/arm: Prepare generic timer for per-platform CNTFRQ
The corner-case codepath was adjusting nexttick such that overflow
wouldn't occur when timer_mod() scaled the value back up. Remove a use
of GTIMER_SCALE and avoid unnecessary operations by calling
timer_mod_ns() directly.
Signed-off-by: Andrew Jeffery
Reviewed-by: Richard Henderson
Review
effect is QEMUTimer cannot exactly
capture the period of frequencies that do not cleanly divide
NANOSECONDS_PER_SECOND for scaling ticks to time. As such, provide an
equally inaccurate scaling factor for scaling time to ticks so at least
a self-consistent inverse relationship holds.
Signed-off-by: Andr
This matches the configuration set by u-boot on the AST2600.
Signed-off-by: Andrew Jeffery
Reviewed-by: Richard Henderson
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
---
hw/arm/aspeed_ast2600.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/aspeed_ast2600
On Fri, 13 Dec 2019, at 18:03, Cédric Le Goater wrote:
> On 13/12/2019 05:28, Andrew Jeffery wrote:
> > Hello,
> >
> > The AST2600 has an additional SDHCI intended for use as an eMMC boot source.
> > These two patches rework the existing ASPEED SDHCI model to acco
On Wed, 18 Dec 2019, at 01:55, Peter Maydell wrote:
> On Fri, 13 Dec 2019 at 05:48, Andrew Jeffery wrote:
> >
> > Hello,
> >
> > This is a v3 of the belated follow-up from a few of my earlier attempts to
> > fix
> > up the ARM generic timer for corr
This matches the configuration set by u-boot on the AST2600.
Signed-off-by: Andrew Jeffery
---
hw/arm/aspeed_ast2600.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 931887ac681f..5aecc3b3caec 100644
--- a/hw/arm/aspeed_ast2600.c
The corner-case codepath was adjusting nexttick such that overflow
wouldn't occur when timer_mod() scaled the value back up. Remove a use
of GTIMER_SCALE and avoid unnecessary operations by calling
timer_mod_ns() directly.
Signed-off-by: Andrew Jeffery
---
target/arm/helper.c | 5 +++--
1
: Andrew Jeffery
---
target/arm/cpu.c| 2 ++
target/arm/cpu.h| 10 ++
target/arm/helper.c | 10 +++---
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7a4ac9339bf9..5698a74061bb 100644
--- a/target/arm/cpu.c
+++ b/target/arm
-coded generic timer rate
of 62.5MHz and so we see "sticky" behaviour in the guest.
Please review.
Andrew
Andrew Jeffery (4):
target/arm: Remove redundant scaling of nexttick
target/arm: Abstract the generic timer frequency
target/arm: Prepare generic timer for per-platform CNTFRQ
effect is QEMUTimer cannot exactly
capture the period of frequencies that do not cleanly divide
NANOSECONDS_PER_SECOND for scaling ticks to time. As such, provide an
equally inaccurate scaling factor for scaling time to ticks so at least
an self-consistent inverse relationship holds.
Signed-of
On Thu, 28 Nov 2019, at 19:16, Cédric Le Goater wrote:
> On 28/11/2019 06:45, Andrew Jeffery wrote:
> > Prepare for SoCs such as the ASPEED AST2600 whose firmware configures
> > CNTFRQ to values significantly larger than the static 62.5MHz value
> > currently derived from
On Tue, 3 Dec 2019, at 04:42, Peter Maydell wrote:
> On Thu, 28 Nov 2019 at 05:44, Andrew Jeffery wrote:
> >
> > Prepare for SoCs such as the ASPEED AST2600 whose firmware configures
> > CNTFRQ to values significantly larger than the static 62.5MHz value
> > currentl
rd
Please review.
Andrew
Andrew Jeffery (4):
target/arm: Remove redundant scaling of nexttick
target/arm: Abstract the generic timer frequency
target/arm: Prepare generic timer for per-platform CNTFRQ
ast2600: Configure CNTFRQ at 1125MHz
hw/arm/aspeed_ast2600.c | 3 +++
target
The corner-case codepath was adjusting nexttick such that overflow
wouldn't occur when timer_mod() scaled the value back up. Remove a use
of GTIMER_SCALE and avoid unnecessary operations by calling
timer_mod_ns() directly.
Signed-off-by: Andrew Jeffery
Reviewed-by: Richard Henderson
Review
This matches the configuration set by u-boot on the AST2600.
Signed-off-by: Andrew Jeffery
Reviewed-by: Richard Henderson
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast2600.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index
effect is QEMUTimer cannot exactly
capture the period of frequencies that do not cleanly divide
NANOSECONDS_PER_SECOND for scaling ticks to time. As such, provide an
equally inaccurate scaling factor for scaling time to ticks so at least
a self-consistent inverse relationship holds.
Signed-off-by: Andr
: Andrew Jeffery
Reviewed-by: Richard Henderson
---
target/arm/cpu.c| 2 ++
target/arm/cpu.h| 10 ++
target/arm/helper.c | 10 +++---
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7a4ac9339bf9..5698a74061bb 100644
--- a
On Tue, 3 Dec 2019, at 16:39, Philippe Mathieu-Daudé wrote:
> On 12/3/19 5:14 AM, Andrew Jeffery wrote:
> > Prepare for SoCs such as the ASPEED AST2600 whose firmware configures
> > CNTFRQ to values significantly larger than the static 62.5MHz value
> > currently derived
On Tue, 3 Dec 2019, at 16:49, Philippe Mathieu-Daudé wrote:
> On 12/3/19 5:14 AM, Andrew Jeffery wrote:
> > The ASPEED AST2600 clocks the generic timer at the rate of HPLL. On
> > recent firmwares this is at 1125MHz, which is considerably quicker than
> > the assumed 6
On Wed, 4 Dec 2019, at 03:57, Philippe Mathieu-Daudé wrote:
> On 12/3/19 1:48 PM, Andrew Jeffery wrote:
> > On Tue, 3 Dec 2019, at 16:39, Philippe Mathieu-Daudé wrote:
> >> On 12/3/19 5:14 AM, Andrew Jeffery wrote:
> >>> Prepare for SoCs such as the ASPEED AST
guest timer
subsystems account for the difference between delay time and the counter
value.
Signed-off-by: Andrew Jeffery
---
The timer rate assumptions seemed unusual, so I'm not sure if this patch is way
off-base or not. However it does make the AST2600 u-boot and kernel behave
correctly.
t
On Fri, 9 Aug 2019, at 13:36, no-re...@patchew.org wrote:
> Patchew URL: https://patchew.org/QEMU/20190809031321.14760-1-and...@aj.id.au/
>
>
>
> Hi,
>
> This series failed build test on s390x host. Please find the details below.
>
> === TEST SCRIPT BEGIN ===
> #!/bin/bash
> # Testing scrip
guest timer
subsystems account for the difference between delay time and the counter
value.
Signed-off-by: Andrew Jeffery
---
v2:
1. Removed the user-mode change that broke v1
2. Rearranged the implementation as a consequence of 1.
target/arm/helper.c | 51
gor Mammedov
> > Signed-off-by: Tao Xu
>
> Reviewed-by: Alistair Francis
>
> Alistair
>
> > ---
> >
> > No changes in v9
> > ---
> > hw/arm/aspeed.c | 5 +
For the ASPEED machines:
Acked-by: Andrew Jeffery
On Thu, 19 Jan 2023, at 23:14, Joel Stanley wrote:
> Enough model to capture the pinmux writes to enable correct operation of
> the parts of pinmux that depend on GFX registers.
>
> Signed-off-by: Joel Stanley
> ---
> include/hw/arm/aspeed_soc.h | 3 +
> include/hw/misc/aspeed_gfx.h | 31 +
As-is the error message can cause some confusion as the mentioned sysctl
attribute name is wrong:
https://www.kernel.org/doc/html/latest/admin-guide/sysctl/vm.html#mmap-min-addr
Signed-off-by: Andrew Jeffery
---
linux-user/elfload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Given several different concepts are suggested for investigation, let's
not confuse e.g. ulimit's -R with what was actually intended.
Signed-off-by: Andrew Jeffery
---
linux-user/elfload.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/linux-user/elfload.c b/
1 - 100 of 340 matches
Mail list logo
