Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function. It introduces three layers of caches and modifies the cache
description registers accordingly. Additionally, a new function is added
to handle cache description when CCIDX is disabled. The CCIDX remains
disabled for cp
Specify which layer (core/cluster/socket) caches found at in the CPU
topology.
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d and l1i (threads will share these caches by default.
Add wrapper for different types of CPUs available in tcg to decribe
caches. Two functions `make_ccsidr32` and `make_ccsidr64`
describing descriptions. The 32 bit version receives extra parameters
that became unknown later in 64 bit.
For CCSIDR register, 32 bit version follows specification [1].
Co
On Fri, 30 Aug 2024 17:29:59 +0100
Peter Maydell wrote:
> On Fri, 30 Aug 2024 at 17:19, Alireza Sanaee
> wrote:
> >
> > Add wrapper for different types of CPUs available in tcg to decribe
> > caches. Two functions `make_ccsidr32` and `make_ccsidr64`
> > describing descriptions. The 32 bit versio
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds wrappers for different types of CPUs
available in tcg to decribe caches. Two function
On Sat, 31 Aug 2024 19:25:47 +0800
Zhao Liu wrote:
> Hi Alireza,
>
> Great to see your Arm side implementation!
>
> On Fri, Aug 23, 2024 at 01:54:44PM +0100, Alireza Sanaee wrote:
> > Date: Fri, 23 Aug 2024 13:54:44 +0100
> > From: Alireza Sanaee
> > Subject: [RFC PATCH 0/2] Specifying cache t
On Mon, 2 Sep 2024 11:25:36 +0100
Peter Maydell wrote:
> On Mon, 2 Sept 2024 at 11:07, Philippe Mathieu-Daudé
> wrote:
> >
> > Hi Alireza,
> >
> > On 30/8/24 20:47, Alireza Sanaee via wrote:
> > > This patch allows for easier manipulation of the cache de
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
available in tcg to decribe caches. One functi
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
available in tcg to decribe caches. One functi
On Tue, 3 Sep 2024 00:11:04 +0200
Philippe Mathieu-Daudé wrote:
> Hi Alireza,
>
> On 2/9/24 22:32, Alireza Sanaee wrote:
> > This patch allows for easier manipulation of the cache description
> > register, CCSIDR. Which is helpful for testing as well. Currently,
> > numbers get hard-coded and mi
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
available in tcg to decribe caches. One functi
On Tue, 3 Sep 2024 15:18:41 +0200
Philippe Mathieu-Daudé wrote:
> On 3/9/24 10:35, Alireza Sanaee wrote:
> > This patch allows for easier manipulation of the cache description
> > register, CCSIDR. Which is helpful for testing as well. Currently,
> > numbers get hard-coded and might be prone to e
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
Prepare to update `build_pptt` function to add cache description
functionalities, thus add binaries in this patch.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/t
This commit adds IsDefined flag to the object and this helps in avoiding
extra checks for every single layer of caches in both x86 and ARM.
Signed-off-by: Alireza Sanaee
---
hw/core/machine-smp.c | 2 ++
include/hw/boards.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/hw/core/machine-
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three layers of caches and modifies
the cache description registers accordingly.
Signed-off-by: Alireza Sanaee
---
target/arm/tcg/cpu64.c | 13 +
1 file changed, 13 insertions(+
Specify which layer (core/cluster/socket) caches found at in the CPU
topology.
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d and l1i (threads will share these caches by default.
Signed-off-by: Alireza Sanaee
---
tests/data/acpi/aarch64/virt/PPTT | Bin 76 -> 76 bytes
tests/data/acpi/aarch64/virt/PPTT.acpihmatvirt | Bin 156 -> 156 bytes
tests/data/acpi/aarch64/virt/PPTT.topology | Bin 336 -> 336 bytes
tests/qtest/bios-tables-test-allowed-diff.h| 3
On Fri, 13 Sep 2024 11:21:28 +0100
Jonathan Cameron wrote:
> On Thu, 12 Sep 2024 14:38:26 +0100
> Alireza Sanaee wrote:
>
> > This commit adds IsDefined flag to the object and this helps in
> > avoiding extra checks for every single layer of caches in both x86
> > and ARM.
> Hi Ali,
>
> You
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three layers of caches and modifies
the cache description registers accordingly.
Signed-off-by: Alireza Sanaee
---
target/arm/tcg/cpu64.c | 13 +
1 file changed, 13 insertions(+
Prepare to update `build_pptt` function to add cache description
functionalities, thus add binaries in this patch.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/test
This commit adds IsDefined flag to the object and this helps in avoiding
extra checks for every single layer of caches in both x86 and ARM.
Signed-off-by: Alireza Sanaee
---
hw/core/machine-smp.c | 2 ++
include/hw/boards.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/hw/core/machine-
The disassembled differences between actual and expected PPTT based on
the following cache topology representation:
```
test_acpi_one("-M virt,smp-cache.0.cache=l1i,smp-cache.0.topology=cluster,"
"smp-cache.1.cache=l1d,smp-cache.1.topology=cluster,"
"smp-cache.2
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
Specify which layer (core/cluster/socket) caches found at in the CPU
topology.
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d and l1i (threads will share these caches by default.
Test new PPTT topolopy with cache representation.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 36e5c0adde..65219f8823 100644
--- a/tests/qtest/bios-ta
On Fri, 4 Oct 2024 10:59:20 +0100
Jonathan Cameron wrote:
> On Thu, 26 Sep 2024 19:33:18 +0800
> Yicong Yang wrote:
>
> > From: Yicong Yang
> >
> > OS like Linux is using PPTT processor node's identical
> > implementation flag [1] to infer whether the whole system or a
> > certain CPU cluster
On Mon, 23 Dec 2024 17:48:18 +
Jonathan Cameron wrote:
> On Mon, 16 Dec 2024 17:54:08 +
> Alireza Sanaee wrote:
>
> > This commit adds IsDefined flag to the object and this helps in
> > avoiding extra checks for every single layer of caches in both x86
> > and ARM.
> >
> > There is alr
On Mon, 23 Dec 2024 18:13:32 +
Jonathan Cameron wrote:
> On Mon, 16 Dec 2024 17:54:14 +
> Alireza Sanaee wrote:
>
> > The disassembled differences between actual and expected PPTT based
> > on the following cache topology representation:
> >
> > ```
> > test_acpi_one("-M
> > virt,smp-c
On Mon, 23 Dec 2024 18:11:45 +
Jonathan Cameron wrote:
> On Mon, 16 Dec 2024 17:54:13 +
> Alireza Sanaee wrote:
>
> > Test new PPTT topolopy with cache representation.
> >
> > Signed-off-by: Alireza Sanaee
> > ---
> > tests/qtest/bios-tables-test.c | 6 +-
> > 1 file changed, 5 i
The disassembled differences between actual and expected PPTT based on
the following cache topology representation:
```
test_acpi_one("-M virt,smp-cache.0.cache=l1i,smp-cache.0.topology=cluster,"
"smp-cache.1.cache=l1d,smp-cache.1.topology=cluster,"
"smp-cache.2
Test new PPTT topolopy with cache representation.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 36e5c0adde..0f72520664 100644
--- a/te
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
This commit adds IsDefined flag to the object and this helps in avoiding
extra checks for every single layer of caches in both x86 and ARM.
There is already a discussion on mailing list to have this flag. A
patch that enables this flag will follow later.
Signed-off-by: Alireza Sanaee
---
hw/cor
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three layers of caches and modifies
the cache description registers accordingly.
Signed-off-by: Alireza Sanaee
---
target/arm/tcg/cpu64.c | 13 +
1 file changed, 13 insertions(+
Prepare to update `build_pptt` function to add cache description
functionalities, thus add binaries in this patch.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/test
Specify which layer (core/cluster/socket) caches found at in the CPU
topology. Updating cache topology to device tree (spec v0.4).
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d an
Add cache topology to PPTT table. With this patch, both ACPI PPTT table
and device tree will represent the same cache topology given users
input.
Signed-off-by: Alireza Sanaee
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
hw/acpi/aml-build.c | 235 ++
On Sun, 8 Sep 2024 20:59:13 +0800
Zhao Liu wrote:
> Hi all,
>
> Compared with previous Patch v1 [1], I've put the cache properties
> list into -machine, this is to meet current needs and also remain
> compatible with my future topology support (more discussion details,
> pls refer [2]).
>
> Th
Hi Zhao,
Thanks for this quick reiteration.
I will prepare the ARM one too. I implemented the ACPI PPTT table to support
thread but later when I worked on device tree noticed the mismatch. Will remove
those PPTT thread support for now.
Alireza
-Original Message-
From: Zhao Liu
Sent
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three layers of caches and modifies
the cache description registers accordingly.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
target/arm/tcg/cpu64.c | 13 +
From: Yicong Yang
Update the ACPI tables according to the acpi aml_build change, also
empty bios-tables-test-allowed-diff.h.
The disassembled differences between actual and expected PPTT shows
below. Only about the root node adding and identification flag set
as expected.
/*
* Intel ACPI C
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
Prepare to update `build_pptt` function to add cache description
functionalities, thus add binaries in this patch.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/test
Specify which layer (core/cluster/socket) caches found at in the CPU
topology. Updating cache topology to device tree (spec v0.4).
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d an
Add cache topology to PPTT table. With this patch, both ACPI PPTT table
and device tree will represent the same cache topology given users
input.
Signed-off-by: Alireza Sanaee
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
hw/acpi/aml-build.c | 205 ++
Test new PPTT topolopy with cache representation.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
tests/qtest/bios-tables-test.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 0a333ec435..6bdc25f4df 1
The disassembled differences between actual and expected PPTT based on
the following cache topology representation:
- l1d and l1i shared at cluster level
- l2 shared at cluster level
- l3 shared at cluster level
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64
Specify which layer (core/cluster/socket) caches found at in the CPU
topology. Updating cache topology to device tree (spec v0.4).
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d an
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three layers of caches and modifies
the cache description registers accordingly.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
target/arm/tcg/cpu64.c | 13 +
Add cache topology to PPTT table. With this patch, both ACPI PPTT table
and device tree will represent the same cache topology given users
input.
Signed-off-by: Alireza Sanaee
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
hw/acpi/aml-build.c | 205 ++
Test new PPTT topolopy with cache representation.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
tests/qtest/bios-tables-test.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 0a333ec435..6bdc25f4df 1
The disassembled differences between actual and expected PPTT based on
the following cache topology representation:
- l1d and l1i shared at cluster level
- l2 shared at cluster level
- l3 shared at cluster level
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64
Prepare to update `build_pptt` function to add cache description
functionalities, thus add binaries in this patch.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/test
Specify which layer (core/cluster/socket) caches found at in the CPU
topology. Updating cache topology to device tree (spec v0.4).
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d an
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three layers of caches and modifies
the cache description registers accordingly.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
target/arm/tcg/cpu64.c | 13 +
Add cache topology to PPTT table. With this patch, both ACPI PPTT table
and device tree will represent the same cache topology given users
input.
Signed-off-by: Alireza Sanaee
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
hw/acpi/aml-build.c | 235 ++
Test new PPTT topolopy with cache representation.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
tests/qtest/bios-tables-test.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 6035ec2c61..f0df03c43e 1
The disassembled differences between actual and expected PPTT based on
the following cache topology representation:
- l1d and l1i shared at cluster level
- l2 shared at cluster level
- l3 shared at cluster level
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
On Fri, 3 Jan 2025 16:25:58 +0800
Zhao Liu wrote:
> On Thu, Jan 02, 2025 at 06:01:41PM +, Alireza Sanaee wrote:
> > Date: Thu, 2 Jan 2025 18:01:41 +
> > From: Alireza Sanaee
> > Subject: Re: [PATCH v6 0/4] i386: Support SMP Cache Topology
> > X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_
Apologies for the duplication. I needed to resend this patch set because I
inadvertently included an extra patch in the version I sent a few minutes ago.
I have now removed the additional patch and resent the corrected set.
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
Hi Ani,
I made a mistake in sending my patchset and included one more patch
before my actual set starts.
I have resent the whole patch-set again
here.
https://lore.kernel.org/qemu-devel/20250114180611.353-1-alireza.san...@huawei.com/
Apologies for the confusion.
Thanks,
Alireza
On Wed, 15 Jan
+alireza.sanaee=huawei@nongnu.org
On Behalf Of Alireza
Sanaee via
Sent: Tuesday, January 14, 2025 6:06 PM
To: qemu-devel@nongnu.org; qemu-...@nongnu.org
Cc: zhao1@intel.com; dapeng1...@linux.intel.com; arm...@redhat.com;
far...@linux.ibm.com; peter.mayd...@linaro.org; m...@redhat.com;
anisi
Prepare to update `build_pptt` function to add cache description
functionalities, thus add binaries in this patch.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/test
On Wed, 25 Dec 2024 11:03:42 +0800
Zhao Liu wrote:
> > > About smp-cache
> > > ===
> > >
> > > The API design has been discussed heavily in [3].
> > >
> > > Now, smp-cache is implemented as a array integrated in -machine.
> > > Though -machine currently can't support JSON format, th
On Thu, 2 Jan 2025 11:09:51 -0600
Rob Herring wrote:
> On Thu, Jan 2, 2025 at 8:57 AM Alireza Sanaee
> wrote:
> >
> > On Wed, 25 Dec 2024 11:03:42 +0800
> > Zhao Liu wrote:
> >
> > > > > About smp-cache
> > > > > ===
> > > > >
> > > > > The API design has been discussed heavily in
Add cache topology to PPTT table. With this patch, both ACPI PPTT table
and device tree will represent the same cache topology given users
input.
Signed-off-by: Alireza Sanaee
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
hw/acpi/aml-build.c| 205 +++
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three layers of caches and modifies
the cache description registers accordingly.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
target/arm/tcg/cpu64.c | 13 +
Specify which layer (core/cluster/socket) caches found at in the CPU
topology. Updating cache topology to device tree (spec v0.4).
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d an
Prepare to update `build_pptt` function to add cache description
functionalities, thus add binaries in this patch.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/test
Test new PPTT topolopy with cache representation.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
tests/qtest/bios-tables-test.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 0a333ec435..6bdc25f4df 1
From: Yicong Yang
Currently we build the PPTT starting from the socket node and each
socket will be a separate tree. For a multi-socket system it'll
be hard for the OS to know the whole system is homogeneous or not
(actually we're in the current implementation) since no parent node
to telling the
From: Yicong Yang
Allow changes to PPTT test table, preparing for adding identical
implementation flags support and for adding a root node for all
the system.
Signed-off-by: Yicong Yang
Reviewed-by: Jonathan Cameron
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.
From: Yicong Yang
The lastest ACPI spec 6.5 support PPTT revision 3. Update it
by handy. This is compatible with previous revision.
Signed-off-by: Yicong Yang
Reviewed-by: Jonathan Cameron
Signed-off-by: Alireza Sanaee
---
hw/acpi/aml-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
From: Yicong Yang
Update the ACPI tables according to the acpi aml_build change, also
empty bios-tables-test-allowed-diff.h.
The disassembled differences between actual and expected PPTT shows
below. Only about the root node adding and identification flag set
as expected.
/*
* Intel ACPI C
OS like Linux is using PPTT processor node's identical implementation
flag [1] to infer whether the whole system or a certain CPU cluster is
homogeneous or not [2]. QEMU currently only support building homogeneous
system, set the flag to indicate the fact. Build a root node in PPTT
for indicates th
From: Yicong Yang
Per ACPI 6.5 Table 5.158: Processor Structure Flags, the identical
implementation flag indicates whether all the children processors
of this node share the same identical implementation revision.
Currently Linux support parsing this field [1] and maybe used to
identify the heter
The disassembled differences between actual and expected PPTT based on
the following cache topology representation:
- l1d and l1i shared at cluster level
- l2 shared at cluster level
- l3 shared at cluster level
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64
Prepare to update `build_pptt` function to add cache description
functionalities, thus add binaries in this patch.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/test
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three layers of caches and modifies
the cache description registers accordingly.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
target/arm/tcg/cpu64.c | 13 +
The disassembled differences between actual and expected PPTT based on
the following cache topology representation:
- l1d and l1i shared at cluster level
- l2 shared at cluster level
- l3 shared at cluster level
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
On Thu, 6 Mar 2025 02:33:37 +
Alireza Sanaee via wrote:
> OS like Linux is using PPTT processor node's identical implementation
> flag [1] to infer whether the whole system or a certain CPU cluster is
> homogeneous or not [2]. QEMU currently only support building
> homoge
On Thu, 6 Mar 2025 02:33:37 +
Alireza Sanaee via wrote:
Hi everyone,
v1 -> v2: I just rebased this patchset which initially was posted in
Sep 2024.
Thanks,
Alireza
> OS like Linux is using PPTT processor node's identical implementation
> flag [1] to infer whether the who
Add cache topology to PPTT table. With this patch, both ACPI PPTT table
and device tree will represent the same cache topology given users
input.
Signed-off-by: Alireza Sanaee
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
hw/acpi/aml-build.c| 205 +++
On Thu, 13 Mar 2025 09:24:56 +
Jonathan Cameron wrote:
> On Mon, 10 Mar 2025 16:23:35 +
> Alireza Sanaee wrote:
>
> > Add cache topology to PPTT table. With this patch, both ACPI PPTT
> > table and device tree will represent the same cache topology given
> > users input.
> >
> > Signed
Specify which layer (core/cluster/socket) caches found at in the CPU
topology. Updating cache topology to device tree (spec v0.4).
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d an
Test new PPTT topolopy with cache representation.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
tests/qtest/bios-tables-test.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 0a333ec43536..6bdc25f4df
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