e now correctly set the device-tree entry 'mmu-type' using
this new satp_mode property.
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
---
hw/riscv/virt.c| 15 ++-
target/riscv/cpu.c | 45 ++
e now correctly set the device-tree entry 'mmu-type' using
this new satp_mode property.
Reviewed-by: Atish Patra
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
---
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
type' using
those new properties.
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
---
v3:
- Free sv_name as pointed by Bin
- Replace satp-mode with boolean properties as suggested by Andrew
- Removed RB from Atish as the patch considerably changed
Hi Andrew,
On Thu, Dec 1, 2022 at 3:47 PM Andrew Jones wrote:
> On Thu, Dec 01, 2022 at 10:36:23AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes
> for
> > the machine's support at startup via the sat
The Svvptc extension describes a uarch that does not cache invalid TLB
entries: that's the case for qemu so there is nothing particular to
implement other than the introduction of this extension, which is done
here.
Signed-off-by: Alexandre Ghiti
---
That's an RFC since the extensi
Hi Andrew,
Sorry for the very late reply, I was (and still am) off!
On Tue, Feb 13, 2024 at 4:33 PM Andrew Jones wrote:
>
> On Tue, Feb 13, 2024 at 03:53:08PM +0100, Alexandre Ghiti wrote:
> > The Svvptc extension describes a uarch that does not cache invalid TLB
> > entrie
-off-by: Alexandre Ghiti
---
hw/riscv/boot.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0ffca05189..9a367af2fa 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -188,13 +188,13 @@ static void riscv_load_initrd
Hi Daniel,
On Mon, Feb 5, 2024 at 1:17 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 2/5/24 04:00, Alexandre Ghiti wrote:
> > Currently, the initrd is placed at 128MB, which overlaps with the kernel
> > when it is large (for example syzbot kernels are). From the kern
Hi Daniel,
On Mon, Feb 5, 2024 at 2:36 PM Alexandre Ghiti wrote:
>
> Hi Daniel,
>
> On Mon, Feb 5, 2024 at 1:17 PM Daniel Henrique Barboza
> wrote:
> >
> >
> >
> > On 2/5/24 04:00, Alexandre Ghiti wrote:
> > > Currently, the initrd is placed at
ideal solution would have been to place the initrd based on the
kernel size but we actually can't since the bss size is not known when
the image is loaded by load_image_targphys_as() and the initrd would
then overlap with this section.
Signed-off-by: Alexandre Ghiti
---
Changes in v2:
- Fix typ
On Tue, Feb 6, 2024 at 9:39 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 2/6/24 12:40, Alexandre Ghiti wrote:
> > Currently, the initrd is placed at 128MB, which overlaps with the kernel
> > when it is large (for example syzbot kernels are). From the kernel side,
> &g
Hey Andrew,
Sorry about the response delay, I was traveling.
On Fri, Jan 6, 2023 at 4:30 PM Andrew Jones wrote:
>
> On Mon, Dec 12, 2022 at 11:22:50AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the ma
with boolean properties as suggested by Andrew
- Removed RB from Atish as the patch considerably changed
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre Ghiti (2):
riscv
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions
x will boot using sv48 scheme
-cpu rv64,sv32=on,sv32=off # Linux will boot using sv57 scheme (the default)
In addition, we now correctly set the device-tree entry 'mmu-type' using
those new properties.
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Si
Hey Andrew,
On Tue, Jan 17, 2023 at 5:31 PM Andrew Jones wrote:
>
> On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the sat
> > wrote:
> > > >
> > > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote:
> > ...
> > > > > +
> > > > > +/* Get rid of 32-bit/64-bit incompatibility */
> > > > > +for (int i = 0; i < 16; ++i)
On Fri, Jan 20, 2023 at 10:53 AM Andrew Jones wrote:
>
> On Fri, Jan 20, 2023 at 09:46:05AM +1000, Alistair Francis wrote:
> > On Thu, Jan 19, 2023 at 11:00 PM Alexandre Ghiti
> > wrote:
> > >
> > > Hi Alistair, Andrew,
> > >
> > > On Thu,
-mode with boolean properties as suggested by Andrew
- Removed RB from Atish as the patch considerably changed
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre Ghiti (5
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Signed-off-by: Alexandre Ghiti
---
target/riscv/csr.c | 21 +++--
1 file changed, 11
will boot using sv48 scheme
And contradictory configurations:
-cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
In addition, we now correctly set the device-tree entry 'mmu-type' using
those new properties.
Co-Developed-by: Ludovic Henry
S
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
---
hw/riscv/virt.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/virt.c
ty
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 78 +++---
target/riscv/cpu.h | 8 +++--
2 files changed, 59 insertions(+), 27 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e409e6ab64..19a37fee2b 100644
--- a/targ
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
---
target
On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> > Currently, the max satp mode is set with the only constraint that it must be
> > implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
> >
>
Hi Alistair,
On Tue, Jan 24, 2023 at 1:41 AM Alistair Francis wrote:
>
> On Mon, Jan 23, 2023 at 7:09 PM Alexandre Ghiti
> wrote:
> >
> > Currently, the max satp mode is set with the only constraint that it must be
> > implemented in qemu, i.e. set in valid_vm_1
Hi Andrew,
On Mon, Jan 23, 2023 at 11:11 AM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the sat
On Mon, Jan 23, 2023 at 11:14 AM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the satp CSR register (done i
On Mon, Jan 23, 2023 at 11:29 AM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote:
> ...
> > +/* Sets the satp mode to the max supported */
> > +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit)
> > +{
>
> ni
On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> > Currently, the max satp mode is set with the only constraint that it must be
> > implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
> >
>
On Mon, Jan 23, 2023 at 2:31 PM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 12:15:08PM +0100, Alexandre Ghiti wrote:
> > On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones
> > wrote:
> > >
> > > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
On Mon, Jan 23, 2023 at 2:51 PM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> > Currently, the max satp mode is set with the only constraint that it must be
> > implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
> >
> &g
as suggested by Andrew
- Removed RB from Atish as the patch considerably changed
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre Ghiti (5):
riscv: Pass Object to
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
---
target
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair
cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 207 +
target/riscv/cpu.h | 19 +
target/riscv/csr.c | 12 ++-
3
r may select
- the user's selection then constrains what's available to the guest
OS.
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 74 +++---
target/riscv/cpu.h | 8 +++--
2 files changed, 56 insertions(+), 26 deletions(-)
diff --git
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 19 ++-
1 file changed, 10 insert
On Wed, Jan 25, 2023 at 1:01 PM Andrew Jones wrote:
>
> On Wed, Jan 25, 2023 at 09:41:05AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the satp CSR register (done i
rivos one
Alexandre Ghiti (5):
riscv: Pass Object to register_cpu_props instead of DeviceState
riscv: Change type of valid_vm_1_10_[32|64] to bool
riscv: Allow user to set the satp mode
riscv: Introduce satp mode hw capabilities
riscv: Correctly set the device-tree entry 'mmu-type&
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
---
target
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair
cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 206 +
target/riscv/cpu.h | 19 +
target/riscv/csr.c | 12 ++-
3
r may select
- the user's selection then constrains what's available to the guest
OS.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 74 +++---
target/riscv/cpu.h | 8 +++--
2 files changed, 56 insertions(+
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 19 ++-
1 file changed, 10 insert
Hi Bin,
On Mon, Jan 30, 2023 at 5:22 AM Bin Meng wrote:
>
> On Thu, Jan 26, 2023 at 12:23 AM Alexandre Ghiti
> wrote:
> >
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup vi
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
hw/riscv/virt.c | 19 ++-
1 fi
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
Reviewed-by
- Replace satp-mode with boolean properties as suggested by Andrew
- Removed RB from Atish as the patch considerably changed
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre
r may select
- the user's selection then constrains what's available to the guest
OS.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 79 +++---
target/riscv/cpu.h | 8 +++--
2 files changed, 60 insertions(+
On Wed, Jan 25, 2023 at 5:52 PM Andrew Jones wrote:
>
> On Wed, Jan 25, 2023 at 05:20:08PM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the satp CSR register (done i
cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 207 +
target/riscv/cpu.h | 19 +
ta
On Mon, Jan 30, 2023 at 5:29 AM Bin Meng wrote:
>
> On Thu, Jan 26, 2023 at 12:24 AM Alexandre Ghiti
> wrote:
> >
> > Currently, the max satp mode is set with the only constraint that it must be
> > implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
As per the specification, in 64-bit, if any of the pte reserved bits 60-54
is set, an exception should be triggered (see 4.4.1, "Addressing and Memory
Protection"), so implement this behaviour in the address translation process.
Reported-by: Andrea Parri
Signed-off-by: Alexa
Hi Alistair,
Sorry for the late reply, I was on PTO.
On Tue, Apr 18, 2023 at 4:22 AM Alistair Francis wrote:
>
> On Mon, Apr 17, 2023 at 8:47 PM Andrea Parri wrote:
> >
> > Hi Alistair,
> >
> > > > @@ -936,6 +936,11 @@ restart:
> > > > return TRANSLATE_FAIL;
> > > > }
> >
ned-off-by: Alexandre Ghiti
---
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 15 +++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fca7ef0cef..8d9ba2ce11 100644
--- a/target/riscv/cpu_bits.h
+++ b/ta
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
---
Changes in v3:
- Rebase on top of https://github.com/alistair23/qemu/tree/riscv-to-apply.next
Changes in v2:
- Handle napot and pbmt exception
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 15 +++
2 fil
On Thu, Apr 20, 2023 at 1:31 AM Alistair Francis wrote:
>
> On Wed, Apr 19, 2023 at 8:48 PM Alexandre Ghiti
> wrote:
> >
> > As per the privileged specification, in 64-bit, if any of the pte reserved
> > bits 60-54 is set an exception should be triggered, and the sam
Hi Frank,
On Wed, Feb 1, 2023 at 4:49 PM Frank Chang wrote:
>
> On Tue, Jan 31, 2023 at 10:36 PM Alexandre Ghiti
> wrote:
>>
>> Currently, the max satp mode is set with the only constraint that it must be
>> implemented in QEMU, i.e. set in valid_vm_1_10_[32|64].
&g
from Atish as the patch considerably changed
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre Ghiti (5):
riscv: Pass Object to register_cpu_props instead of DeviceSta
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
Reviewed-by
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair
cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
Acked-by: Alistair Francis
---
target/riscv/cpu.c | 215 +++
r may select
- the user's selection then constrains what's available to the guest
OS.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
---
target/riscv/cpu.c | 91 +-
target/riscv/cpu.h | 8 +++-
2 files changed
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Frank Chang
---
hw/riscv/v
type' using
those new properties.
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
---
v4:
- Use custom boolean properties instead of OnOffAuto properties, based
on ARMVQMap, as suggested by Andrew
v3:
- Free sv_name as pointed by Bin
- R
t the default satp mode for the
current cpus in each cpu init function too.
Thanks for your remarks,
Alex
>
> Regards,
> Frank Chang
>
>
> On Mon, Dec 12, 2022 at 6:23 PM Alexandre Ghiti
> wrote:
>>
>> RISC-V specifies multiple sizes for addressable memory and
On Fri, Dec 16, 2022 at 2:03 PM Alexandre Ghiti wrote:
>
> Hi Frank,
>
> On Fri, Dec 16, 2022 at 10:32 AM Frank Chang wrote:
> >
> > Hi Alexandre,
> >
> > Thanks for the contribution. This is really helpful.
> >
> > It seems like if we want to sp
From: Gianluca Guida
Add Zabha implementation.
Signed-off-by: Gianluca Guida
Signed-off-by: Alexandre Ghiti
---
target/riscv/cpu.c | 2 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 22 +++
target/riscv
iew it and give comments.
Sure, I'll do that, your patchset seems more complete than ours.
Thanks,
Alex
>
> Thanks,
> Zhiwei
>
> On 2024/5/28 13:45, Alexandre Ghiti wrote:
> > From: Gianluca Guida
> >
> > Add Zabha implementation.
> >
&
allows to drastically reduce the number of sfence.vma emitted
by S-mode.
Signed-off-by: Alexandre Ghiti
---
Changes in v3:
- Rebase on top of master
- Change 1.12 to 1.13 spec version (drew)
Changes in v2:
- Rebase on top of master
- Enable Svvptc by default
target/riscv/cpu.c | 2 ++
target/riscv
#x27;s
> comment in patch 3 can also be handled during the process.
Sure I'll do that today,
Thanks,
Alex
>
>
> Thanks,
>
>
> Daniel
>
>
>
> >
> >
> > Thanks,
> >
> >
> > Daniel
> >
> >
> >
> >
&
uggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre Ghiti (5):
riscv: Pass Object to register_cpu_props instead of DeviceState
riscv: Change type of valid_vm_1_10_[32|64] to bool
riscv: Allow user to set t
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
Reviewed-by
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair
cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Frank Chang
---
target/riscv/cpu.c | 214 ++
r may select
- the user's selection then constrains what's available to the guest
OS.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/r
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Frank Chang
---
hw/riscv/v
gt;
> > v4:
> > - Use custom boolean properties instead of OnOffAuto properties, based
> > on ARMVQMap, as suggested by Andrew
> >
> > v3:
> > - Free sv_name as pointed by Bin
> > - Replace satp-mode with boolean properties as suggested by Andrew
> > - Removed
allows to drastically reduce the number of sfence.vma emitted
by S-mode.
Signed-off-by: Alexandre Ghiti
---
Changes in v2:
- Rebase on top of master
- Enable Svvptc by default
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu.
On Fri, Mar 14, 2025 at 1:38 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 3/14/25 9:11 AM, Alexandre Ghiti wrote:
> > On Fri, Mar 14, 2025 at 11:48 AM Alexandre Ghiti
> > wrote:
> >>
> >> The Svrsw60b59b extension allows to free the PTE reserv
The Svrsw60b59b extension allows to free the PTE reserved bits 60 and 59
for software to use.
Signed-off-by: Alexandre Ghiti
---
I tested it by always setting the bits 60 and 59 in Linux which booted
fine.
target/riscv/cpu.c| 2 ++
target/riscv/cpu_bits.h | 3 ++-
target/riscv
On Fri, Mar 14, 2025 at 11:48 AM Alexandre Ghiti wrote:
>
> The Svrsw60b59b extension allows to free the PTE reserved bits 60 and 59
> for software to use.
I missed that the extension had been renamed to Svrsw60*t*59b, I'll
fix that in v2 later after I collect some feedback.
The satp mode is set using the svXX properties, but that actually
restricts the satp mode to the minimum required by the profile and
prevents the use of higher satp modes.
Fix this by not setting any svXX property and allow all satp mode to be
supported.
Signed-off-by: Alexandre Ghiti
The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software to use.
Signed-off-by: Alexandre Ghiti
---
Changes in v2:
- Add support for IOMMU
- Make svrsw60t59b depend on sv39 (deepak)
Open question: svrsw60t59b in IOMMU should also depend on 64bit, but I
did not
Hi Daniel,
On Sat, Jun 7, 2025 at 7:54 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 6/5/25 11:21 AM, Alexandre Ghiti wrote:
> > The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
> > for software to use.
> >
> > Signed-off-by: Alexandre
The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software to use.
Reviewed-by: Deepak Gupta
Signed-off-by: Alexandre Ghiti
---
Changes in v2:
- Fix riscv32 max config (thanks Daniel!)
- Add RB from Deepak
- Remove tab usage
---
hw/riscv/riscv-iommu-bits.h
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