[PATCH] target/arm: add support for 64-bit PMCCNTR in AArch32 mode

See https://developer.arm.com/documentation/ddi0601/2024-06/AArch32-Registers/PMCCNTR--Performance-Monitors-Cycle-Count-Register?lang=en Signed-off-by: Alex Richardson --- target/arm/helper.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c

[PATCH v2 2/2] target/riscv: Call check_access() before tcg_temp_new()

--- target/riscv/insn_trans/trans_rvh.c.inc | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc index c66268a9b0..c6bbc54d68 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++

[PATCH v2 1/2] target/riscv: Reduce duplicated code in trans_rvh.c.inc

I rencently merged CHERI QEMU up to 5.2, and we have to modify all functions that perform memory accesses. Factoring these almost-indentical functions into two shared helpers makes our changes a lot smaller and should also make this code easier to maintain. --- target/riscv/insn_trans/trans_rvh.c.

[PATCH 2/2] target/riscv: Call check_access() before tcg_temp_new()

--- target/riscv/insn_trans/trans_rvh.c.inc | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc index 203a620723..b0a9ea1dca 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/t

[PATCH 1/2] target/riscv: Reduce duplicated code in trans_rvh.c.inc

I rencently merged CHERI QEMU up to 5.2, and we have to modify all functions that perform memory accesses. Factoring these almost-indentical functions into two shared helpers makes our changes a lot smaller and should also make this code easier to maintain. --- target/riscv/insn_trans/trans_rvh.c.

[PATCH] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR

The TW and TSR fields should be bits 21 and 22 and not 30/29. This was found while comparing QEMU behaviour against the sail formal model (https://github.com/rems-project/sail-riscv/). Signed-off-by: Alex Richardson --- target/riscv/cpu_bits.h | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH] Fix MIPS add.s after 1ace099f2acb952eaaef0ba7725879949a7e4406

After merging latest QEMU upstream into our CHERI fork, I noticed that some of the FPU tests in our MIPS baremetal testsuite (https://github.com/CTSRD-CHERI/cheritest) started failing. It turns out this commit accidentally changed add.s into a subtract. Signed-off-by: Alex Richardson --- target