17 00:00:00 2001
From: Alejandro Jimenez
Date: Fri, 26 Jan 2024 17:54:16 +
Subject: [PATCH 5/4] pvpanic: Emit GUEST_PVSHUTDOWN QMP event on pvpanic
shutdown signal
Emit a QMP event on receiving a PVPANIC_SHUTDOWN event. Even though a typical
SHUTDOWN event will be sent, it will be indistin
On 5/24/2022 3:48 PM, Moger, Babu wrote:
On 5/24/22 10:19, Igor Mammedov wrote:
On Tue, 24 May 2022 11:10:18 -0400
Igor Mammedov wrote:
CCing AMD folks as that might be of interest to them
I am trying to recreate the bug on my AMD system here.. Seeing this message..
qemu-system-x86_64: -nu
On 5/25/2022 3:56 PM, Moger, Babu wrote:
On 5/24/22 18:23, Alejandro Jimenez wrote:
On 5/24/2022 3:48 PM, Moger, Babu wrote:
On 5/24/22 10:19, Igor Mammedov wrote:
On Tue, 24 May 2022 11:10:18 -0400
Igor Mammedov wrote:
CCing AMD folks as that might be of interest to them
I am trying
On 10/20/2020 1:14 PM, Paolo Bonzini wrote:
On 02/10/20 04:41, Alejandro Jimenez wrote:
The fact that the behavior of hv-crash is also affected is why I chose to
implement this change as an independent
option, as opposed to making it a property of the pvpanic device (e.g. -device
pvpanic
.
Suggested-by: Paolo Bonzini
Signed-off-by: Alejandro Jimenez
Reviewed-by: David Edmondson
Reviewed-by: Liam Merwick
---
MAINTAINERS | 2 +
include/sysemu/runstate-action.h | 16 +
include/sysemu/sysemu.h | 1 +
qapi/run-state.json | 88
Add QMP commands to allow for the behaviors specified by the
-action event=action command line option to be set at runtime,
mimicking the watchdog-set-action QMP command.
Suggested-by: Paolo Bonzini
Signed-off-by: Alejandro Jimenez
Reviewed-by: David Edmondson
Reviewed-by: Liam Merwick
down, panic, and watchdog
expiration are the current options). The existing options would translate to
the new option, like:
* -no-reboot --> "-action reboot=shutdown"
* -no-shutdown --> "-action shutdown=pause"
Please share any questions or comments.
Regards,
Alej
Test the scenario where the -action panic=none parameter is used to
signal that the VM must continue executing after a guest panic
occurs.
Suggested-by: Paolo Bonzini
Signed-off-by: Alejandro Jimenez
Reviewed-by: David Edmondson
Reviewed-by: Liam Merwick
---
tests/qtest/pvpanic-test.c | 26
: Paolo Bonzini
Signed-off-by: Alejandro Jimenez
Reviewed-by: David Edmondson
Reviewed-by: Liam Merwick
---
include/sysemu/sysemu.h | 1 +
qapi/run-state.json | 27 ++-
qemu-options.hx | 3 +++
softmmu/runstate-action.c | 22
On 12/8/2020 2:58 PM, Paolo Bonzini wrote:
On 08/12/20 20:57, Paolo Bonzini wrote:
On 08/12/20 20:14, Alejandro Jimenez wrote:
##
+# @reboot-set-action:
+#
+# Set reboot action
+#
+# Since: 6.0
+##
+{ 'command': 'reboot-set-action', 'data
: "set-action",
"arguments": { "pair": {
"event": "shutdown",
"action": "pause" } } }
<- { "return": {} }
Suggested-by: Paolo Bonzini
Signed-off-by: Alejandro Jimenez
---
qapi/run-state.json
Test the scenario where the -action panic=none parameter is used to
signal that the VM must continue executing after a guest panic
occurs.
Suggested-by: Paolo Bonzini
Signed-off-by: Alejandro Jimenez
---
tests/qtest/pvpanic-test.c | 26 +-
1 file changed, 25 insertions
: Paolo Bonzini
Signed-off-by: Alejandro Jimenez
---
include/sysemu/sysemu.h | 1 +
qapi/run-state.json | 27 ++-
qemu-options.hx | 3 +++
softmmu/runstate-action.c | 22 ++
softmmu/vl.c | 14 +++---
5 files
.
Suggested-by: Paolo Bonzini
Signed-off-by: Alejandro Jimenez
---
MAINTAINERS | 2 +
include/sysemu/runstate-action.h | 16 +
include/sysemu/sysemu.h | 1 +
qapi/run-state.json | 88 ++
qemu-options.hx
s). The existing options would translate to
the new option, like:
* -no-reboot --> "-action reboot=shutdown"
* -no-shutdown --> "-action shutdown=pause"
Please share any questions or comments.
Regards,
Alejandro
Alejandro Jimenez (4):
vl: Add an -action option to r
On 12/9/2020 4:43 PM, Paolo Bonzini wrote:
On 09/12/20 18:52, Alejandro Jimenez wrote:
+# Set the action that will be taken by the emulator in response to a
guest
+# event.
+#
+# @pair: a @RunStateAction type that describes an event|action pair.
+#
+# Returns: Nothing on success
Test the scenario where the -action panic=none parameter is used to
signal that the VM must continue executing after a guest panic
occurs.
Suggested-by: Paolo Bonzini
Signed-off-by: Alejandro Jimenez
---
tests/qtest/pvpanic-test.c | 26 +-
1 file changed, 25 insertions
: Paolo Bonzini
Signed-off-by: Alejandro Jimenez
---
include/sysemu/runstate-action.h | 1 +
qapi/run-state.json | 27 ++-
qemu-options.hx | 3 +++
softmmu/runstate-action.c| 17 +
softmmu/vl.c | 23
.
Suggested-by: Paolo Bonzini
Signed-off-by: Alejandro Jimenez
---
MAINTAINERS | 2 +
include/sysemu/runstate-action.h | 21 +
include/sysemu/sysemu.h | 1 -
monitor/qmp-cmds.c | 3 +-
qapi/run-state.json | 90
",
"arguments": {
"reboot": "none",
"shutdown": "poweroff",
"panic": "none",
"watchdog": "debug" } }
<- { "return": {} }
Suggested-by: Paolo Bonzini
Signe
reboot --> "-action reboot=shutdown"
* -no-shutdown --> "-action shutdown=pause"
Please share any questions or comments.
Regards,
Alejandro
Alejandro Jimenez (4):
vl: Add an -action option to respond to guest events
vl: Add option to avoid stopping VM upon guest pani
On 1/19/2021 4:34 PM, Peter Maydell wrote:
On Tue, 15 Dec 2020 at 18:11, Paolo Bonzini wrote:
From: Alejandro Jimenez
The current default action of pausing a guest after a panic event
is received leaves the responsibility to resume guest execution to the
management layer. The reasons for
);
vm_stop(RUN_STATE_GUEST_PANICKED);
-} else if (panic_action == PANIC_ACTION_POWEROFF) {
+} else if (panic_action == PANIC_ACTION_SHUTDOWN) {
qapi_event_send_guest_panicked(GUEST_PANIC_ACTION_POWEROFF,
!!info, info);
vm_stop(RUN_STATE_GU
Advertise both types of events supported when the guest OS
queries the pvpanic device. Currently only PVPANIC_PANICKED is
exposed; PVPANIC_CRASHLOADED must also be advertised.
Fixes: 7dc58deea79a ("pvpanic: implement crashloaded event handling")
Signed-off-by: Alejandro Jimenez
Acke
device (e.g. -device
pvpanic,no-panicstop).
Please let me know if you have any comments or suggestions.
Regards,
Alejandro
Alejandro Jimenez (1):
vl: Add -no-panicstop option
qemu-options.hx | 11 +++
softmmu/vl.c| 17 ++---
2 files changed, 25 insertions(+), 3 deletions(-)
--
1.8.3.1
proceed to capture a crash dump and automatically reboot
without intervention of a management layer.
Add an option to avoid stopping a VM after a panic event is received.
Signed-off-by: Alejandro Jimenez
Reviewed-by: Mark Kanda
---
qemu-options.hx | 11 +++
softmmu/vl.c| 17
advertised, but only on
new machine types.
Fixes: 7dc58deea79a ("pvpanic: implement crashloaded event handling")
Reported-by: Alejandro Jimenez
Signed-off-by: Paolo Bonzini
---
hw/core/machine.c | 1 +
hw/misc/pvpanic.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git
quot;
I pointed out a few minor nits, of which I think the most important is to
correct the error message on PATCH 5/5. With that addressed:
Reviewed-by: Alejandro Jimenez
Thank you.
Change History:
V2:
- Fixed non-kvm build issue (Reported by Michael Tsirkin)
V1:
- https://lore.kernel.org
Hi Santosh,
On 9/16/24 10:31, Santosh Shukla wrote:
From: Suravee Suthikulpanit
Introduce 'nodma' shared memory region to support PT mode
so that for each device, we only create an alias to shared memory
region when DMA-remapping is disabled.
Signed-off-by: Suravee Suthikulpanit
Signed-off-b
In subject:
s/invaldate/invalidate/
On 9/16/24 10:31, Santosh Shukla wrote:
From: Suravee Suthikulpanit
In order to support AMD IOMMU interrupt remapping emulation with PCI
pass-through devices, QEMU needs to notify VFIO when guest IOMMU driver
updates and invalidate the guest interrupt remapp
On 9/16/24 10:31, Santosh Shukla wrote:
From: Suravee Suthikulpanit
The XTSup mode enables x2APIC support for AMD IOMMU, which is needed
to support vcpu w/ APIC ID > 255.
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Santosh Shukla
---
v2:
- Fixed non-kvm build issue by adding a che
On 3/19/25 2:06 AM, Vasant Hegde wrote:
Alejandro,
On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
The AMD I/O Virtualization Technology (IOMMU) Specification (see Table 8: V,
TV, and GV Fields in Device Table Entry), specifies that a DTE with V=0,
TV=1 does not contain a valid address
Hi Sairaj Kodilkar,
On 3/20/25 1:11 AM, Arun Kodilkar, Sairaj wrote:
On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
The AMD I/O Virtualization Technology (IOMMU) Specification (see Table
8: V,
TV, and GV Fields in Device Table Entry), specifies that a DTE with V=0,
TV=1 does not contain a
On 4/17/25 11:14 AM, Ethan MILON wrote:
Hi,
On 4/13/25 10:02 PM, Alejandro Jimenez wrote:
For the specified address range, walk the page table identifying regions
as mapped or unmapped and invoke registered notifiers with the
corresponding event type.
Signed-off-by: Alejandro Jimenez
On 4/17/25 6:19 AM, Sairaj Kodilkar wrote:
On 4/17/2025 3:47 AM, Alejandro Jimenez wrote:
On 4/16/25 8:14 AM, Sairaj Kodilkar wrote:
+
+ /* DMA address translation */
+ bool dma_remap;
I think you should use this flag in the remapping path as well.
I am aware that you are
On 4/17/25 8:40 AM, CLEMENT MATHIEU--DRIF wrote:
On 14/04/2025 4:02 am, Alejandro Jimenez wrote:
Caution: External email. Do not open attachments or click links, unless this
email comes from a known sender and you know the content is safe.
The current amdvi_page_walk() is designed to be
en as it fails to call kvm_enable_x2apic().
Fix this by adding back kvm_enable_x2apic() call when xtsup=on.
Fixes: 8c6619f3e692 ("hw/i386/amd_iommu: Simplify non-KVM checks on XTSup
feature")
Reported-by: Alejandro Jimenez
Cc: Philippe Mathieu-Daudé
Cc: Joao Martins
Signed-off-by: V
u/amd:
Remove redundant domain flush from attach_device()").
Remove the assertion altogether and adjust the range to ensure it does
not cross notifier boundaries.
Signed-off-by: Alejandro Jimenez
---
system/memory.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --gi
and UNMAP events.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 49 +
1 file changed, 49 insertions(+)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index e24eab34c9e0..3bfa08419ffe 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386
evice vfio-pci,host=0000:a1:00.1,id=net0
---
Alejandro Jimenez (18):
memory: Adjust event ranges to fit within notifier boundaries
amd_iommu: Add helper function to extract the DTE
amd_iommu: Add support for IOMMU notifier
amd_iommu: Unmap all address spaces under the AMD IOMMU on reset
a
: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 34 --
hw/i386/amd_iommu.h | 6 ++
2 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 22d648c2e0e3..8dbb10d91339 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw
Extracting the DTE from a given AMDVIAddressSpace pointer structure is a
common operation required for syncing the shadow page tables. Implement a
helper to do it and check for common error conditions.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 47
regions where a mapping
doesn't currently exist, which is not correct.
Note that after this change there are no users of amdvi_page_fault(),
but since the IO page fault handling will be addressed in upcoming work,
I am choosing to mark it as unused rather than deleting it.
Signed-off-by: Alej
whether DMA remapping is available as a global capability, and
if the specific address space is using address translation.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/hw/i386/amd_iommu.c b
.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 0df658712ec0..5f55be1f4d36 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -958,7 +958,7 @@ static inline
les on the host.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index cf83ac607064..e24eab34c9e0 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -1902,
For the specified address range, walk the page table identifying regions
as mapped or unmapped and invoke registered notifiers with the
corresponding event type.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 74 +
1 file changed, 74
.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 110
1 file changed, 102 insertions(+), 8 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 6789e1e9b688..cf83ac607064 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386
The current amdvi_page_walk() is designed to be called by the replay()
method. Rather than drastically altering it, introduce helpers to fetch
guest PTEs that will be used by a page walker implementation.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 125
address translation for the address space if needed.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 68 -
1 file changed, 67 insertions(+), 1 deletion(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 3bfa08419ffe..abdd67f6b12c
On reset, restore the default address translation mode for all the
address spaces managed by the vIOMMU.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 28
1 file changed, 28 insertions(+)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index
and used to issue
the UNMAP notification. Using the correct size is essential since the
VFIO IOMMU Type1v2 driver in the host kernel will reject unmap requests
that do not fully cover previous mappings.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 98
Simplify amdvi_page_walk() by making it call the fetch_pte() helper that
is already in use by the shadow page synchronization code. Ensures all
code uses the same page table walking algorithm.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 60
Support dropping all existing mappings on reset. When the guest kernel
reboots it will create new ones, but other components that run before
the kernel (e.g. OVMF) should not be able to use existing mappings from
the previous boot.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 68
The size of the region to invalidate depends on the S bit and address
encoded in the command. Add a helper to extract this information, which
will be used to sync shadow page tables in upcoming changes.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 34
encountered.
Do not assume that addresses for a device with DTE[TV]=0 are passed
through (i.e. not remapped) and instead terminate the page table walk
early.
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_io
On 4/16/25 2:50 PM, Michael S. Tsirkin wrote:
On Wed, Apr 16, 2025 at 09:29:23AM -0400, Alejandro Jimenez wrote:
On 4/16/25 7:36 AM, Sairaj Kodilkar wrote:
+static int amdvi_as_to_dte(AMDVIAddressSpace *as, uint64_t *dte);
+
No need to have this function declaration as it is a
On 4/16/25 7:36 AM, Sairaj Kodilkar wrote:
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
Hi Alejandro,
Extracting the DTE from a given AMDVIAddressSpace pointer structure is a
common operation required for syncing the shadow page tables. Implement a
helper to do it and check for common
On 4/16/25 8:14 AM, Sairaj Kodilkar wrote:
+
+ /* DMA address translation support */
+ IOMMUNotifierFlag notifier_flags;
+ /* entry in list of Address spaces with registered notifiers */
+ QLIST_ENTRY(AMDVIAddressSpace) next;
+ /* DMA address translation active */
+ bool add
On 4/15/25 2:38 AM, Sairaj Kodilkar wrote:
Hi Alejandro,
On 4/15/2025 1:56 AM, Alejandro Jimenez wrote:
Hi Sairaj,
I'm conflicted by the implementation of the change, so I'd like to
make sure I fully understand...
On 4/10/25 2:44 AM, Sairaj Kodilkar wrote:
Fix th
Hi Sairaj,
I'm conflicted by the implementation of the change, so I'd like to make
sure I fully understand...
On 4/10/25 2:44 AM, Sairaj Kodilkar wrote:
Current amd_iommu enables the iommu_nodma address space when pt_supported
flag is on.
As it should, that is the intended purpose of the i
On 4/22/25 8:17 AM, Sairaj Kodilkar wrote:
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
Enable the appropriate memory region for an address space depending on
the address translation mode selected for it. This is currently based on
a generic x86 IOMMMU property, and only done during the
On 4/22/25 8:26 AM, Sairaj Kodilkar wrote:
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
The size of the region to invalidate depends on the S bit and address
encoded in the command. Add a helper to extract this information, which
will be used to sync shadow page tables in upcoming
On 4/22/25 8:38 AM, Sairaj Kodilkar wrote:
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
When the guest issues an INVALIDATE_IOMMU_PAGES command, decode the
address and size of the invalidation and sync the guest page table state
with the host. This requires walking the guest page table
On 4/22/25 8:48 AM, Sairaj Kodilkar wrote:
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
+ if ((ret < 0) || (!ret && !dte_mode)) {
+ /*
+ * The DTE could not be retrieved, it is not valid, or it is
not setup
+ * for paging. In either case, ens
The size of the region to invalidate depends on the S bit and address
encoded in the command. Add a helper to extract this information, which
will be used to sync shadow page tables in upcoming changes.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 34
The current amdvi_page_walk() is designed to be called by the replay()
method. Rather than drastically altering it, introduce helpers to fetch
guest PTEs that will be used by a page walker implementation.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 123
and UNMAP events.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 48 +
1 file changed, 48 insertions(+)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 5ce74f2c052d..fa5dbc3cc700 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386
only, no functional change intended.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 170 ++--
1 file changed, 85 insertions(+), 85 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 2cf7e24a21d8..9e500121f6e8 100644
--- a
.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 82 -
1 file changed, 74 insertions(+), 8 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 2f69459ab68d..bddfe2f93136 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386
Extracting the DTE from a given AMDVIAddressSpace pointer structure is a
common operation required for syncing the shadow page tables. Implement a
helper to do it and check for common error conditions.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 45
On reset, restore the default address translation mode for all the
address spaces managed by the vIOMMU.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 28
1 file changed, 28 insertions(+)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index
.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 5322a614f5d6..698967cc1a88 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -496,7 +496,7 @@ static inline
nt testing by Sairaj (thank you!)
Thank you,
Alejandro
[0]
https://lore.kernel.org/all/20250414020253.443831-1-alejandro.j.jime...@oracle.com/
Alejandro Jimenez (20):
memory: Adjust event ranges to fit within notifier boundaries
amd_iommu: Document '-device amd-iommu' common options
g list threads.
Signed-off-by: Alejandro Jimenez
---
qemu-options.hx | 23 +++
1 file changed, 23 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
index dc694a99a30a..198acab48e8e 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1226,6 +1226,29 @@ SRST
`
Support dropping all existing mappings on reset. When the guest kernel
reboots it will create new ones, but other components that run before
the kernel (e.g. OVMF) should not be able to use existing mappings from
the previous boot.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 74
Simplify amdvi_page_walk() by making it call the fetch_pte() helper that is
already in use by the shadow page synchronization code. Ensures all code
uses the same page table walking algorithm.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 59
that enable the synchronization of
guest I/O page tables with host IOMMU state, at which point an amd-iommu
device property will be introduced to control this capability.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 26 +++---
hw/i386/amd_iommu.h | 3 +++
2 files
configured with
the NpCache capability, so a guest driver issues IOMMU invalidations for
both map() and unmap() operations. This capability is already set by default
and written to the configuration in amdvi_pci_realize() as part of
AMDVI_CAPAB_FEATURES.
Signed-off-by: Alejandro Jimenez
---
hw
whether the specific address space is using address translation (via the
newly introduced addr_translation field). Later, region activation will also
be controlled by availability of DMA remapping capability (via dma-remap
property to be introduced in follow up changes).
Signed-off-by: Alejandro Jimenez
les on the
host.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 24
1 file changed, 24 insertions(+)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 7bcba47a01ba..5ce74f2c052d 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -879
address translation for the address space if needed. Requires dma-remap=on.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 78 +++--
1 file changed, 76 insertions(+), 2 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index
For the specified address range, walk the page table identifying regions
as mapped or unmapped and invoke registered notifiers with the
corresponding event type.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 75 +
1 file changed, 75
encountered.
Do not assume that addresses for a device with DTE[TV]=0 are passed
through (i.e. not remapped) and instead terminate the page table walk
early.
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_io
and used to issue the UNMAP
notification. Using the correct size is essential since the VFIO IOMMU
Type1v2 driver in the host kernel will reject unmap requests that do not
fully cover previous mappings.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 91
u/amd:
Remove redundant domain flush from attach_device()").
Remove the assertion altogether and adjust the range to ensure it does
not cross notifier boundaries.
Signed-off-by: Alejandro Jimenez
---
system/memory.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --gi
not yet implemented.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 7 ---
hw/i386/amd_iommu.h | 9 ++---
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 068eeb0cae..8b97abe28c 100644
The size mask currently encompasses reserved bits [11:9]. Extract only the
corrects bits encoding size (i.e. [8:0]).
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.h | 10 +-
1 file
Correctly calculate the Device Table size using the format encoded in the
Device Table Base Address Register (MMIO Offset h).
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 4 ++--
1 file
state of the AMD vIOMMU, but the fixes on this
series should be simple enough to apply, so I Cc'd stable for consideration.
Thank you,
Alejandro
Alejandro Jimenez (6):
amd_iommu: Fix Miscellanous Information Register 0 offsets
amd_iommu: Fix Device ID decoding for INVALIDATE_IOTLB_PAGES co
encountered.
Do not assume that addresses for a device with DTE[TV]=0 are passed through
(i.e. not remapped) and instead terminate the page table walk early.
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
---
hw/i386/a
The definitions encoding the maximum Virtual, Physical, and Guest Virtual
Address sizes supported by the IOMMU are using incorrect offsets i.e. the
VASize and GVASize offsets are switched.
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by:
The DeviceID bits are extracted using an incorrect offset in the call to
amdvi_iotlb_remove_page(). This field is read (correctly) earlier, so use
the value already retrieved for devid.
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by:
On 3/12/25 12:12 AM, Arun Kodilkar, Sairaj wrote:
Hi Alejandro,
On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
[...]
--- a/hw/i386/amd_iommu.h
+++ b/hw/i386/amd_iommu.h
@@ -25,6 +25,8 @@
#include "hw/i386/x86-iommu.h"
#include "qom/object.h"
+#define GENMASK64(h,
+ Suravee
On 2/17/25 02:26, Philippe Mathieu-Daudé wrote:
On 31/7/24 19:00, Peter Maydell wrote:
In amdvi_update_iotlb() we will only put a new entry in the hash
table if to_cache.perm is not IOMMU_NONE. However we allocate the
memory for the new AMDVIIOTLBEntry and for the hash table key
rega
On 5/12/25 3:00 AM, Sairaj Kodilkar wrote:
On 5/2/2025 7:46 AM, Alejandro Jimenez wrote:
- if (pte & AMDVI_DEV_TRANSLATION_VALID) {
- level = get_pte_translation_mode(pte);
- if (level >= 7) {
- trace_amdvi_mode_invalid(level, addr);
+ if
On 5/12/25 2:45 AM, Sairaj Kodilkar wrote:
On 5/2/2025 7:45 AM, Alejandro Jimenez wrote:
@@ -1035,13 +1070,13 @@ static void
amdvi_do_translate(AMDVIAddressSpace *as, hwaddr addr,
return;
}
- if (!amdvi_get_dte(s, devid, entry)) {
- return;
- }
+ dte_ret
Hi Sairaj
On 5/16/25 4:07 AM, Sairaj Kodilkar wrote:
On 5/2/2025 7:45 AM, Alejandro Jimenez wrote:
Hi Alejandro,
Tested the v2, everything looks good when I boot guest with upstream
kernel. But I observed that NVME driver fails to load with guest kernel
version 4.15.0-213-generic. This is
Hi Ethan,
On 5/20/25 6:18 AM, Ethan MILON wrote:
Hi,
On 5/2/25 4:15 AM, Alejandro Jimenez wrote:
Extracting the DTE from a given AMDVIAddressSpace pointer structure is a
common operation required for syncing the shadow page tables. Implement a
helper to do it and check for common error
Correctly calculate the Device Table size using the format encoded in the
Device Table Base Address Register (MMIO Offset h).
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/a
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