[PATCH v2 00/17] bsd-user: Comprehensive RISCV Support

Key Changes Compared to Version 1: Patch 3: Array subscript was replaced by a register constant. Patches 4 and 5: Merged into a single patch. Patch 6: Comment was removed. Patch 10: ROUND_DOWN was used to align the stack. Array subscript was replaced by a register constant. Patch 15: Regi

[PATCH v2 12/17] bsd-user: Add generic RISC-V64 target definitions

From: Warner Losh Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh

[PATCH v2 15/17] bsd-user: Implement 'get_mcontext' for RISC-V

orbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/signal.c | 53 + 1 file changed, 53 insertions(+) diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signa

[PATCH v2 01/17] bsd-user: Implement RISC-V CPU initialization and main loop

From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored

[PATCH v2 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling

: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 94 1 file changed, 94 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h index

[PATCH v2 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- configs/targets/riscv64-bsd-user.mak | 4 1 file changed, 4 insertions(+) create mode 100644 configs/targets

[PATCH v2 08/17] bsd-user: Implement RISC-V sysarch system call emulation

From: Mark Corbin Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corb

[PATCH v2 06/17] bsd-user: Define RISC-V register structures and register copying

ure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_reg.h | 88 1 file changed, 88 insertions(+) create mode 100644 bsd-user/riscv

[PATCH v2 14/17] bsd-user: Implement RISC-V signal trampoline setup functions

the signal handler address, and the signal frame pointer. 'setup_sigframe_arch()': Initializes the signal frame with the current machine context.This function copies the context from the CPU state to the signal frame, preparing it for the signal handler. Signed-off-by: Mark Corbin Signed

[PATCH v2 07/17] bsd-user: Add RISC-V signal trampoline setup function

From: Mark Corbin Implemented the `setup_sigtramp` function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_sigtramp.h | 46

[PATCH v2 11/17] bsd-user: Define RISC-V system call structures and constants

From: Mark Corbin Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet

[PATCH v2 04/17] bsd-user: Implement RISC-V TLS register setup

From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajee

[PATCH v2 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

From: Mark Corbin Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin Signed-off-by: Warner Losh Signed-off

[PATCH v2 09/17] bsd-user: Add RISC-V thread setup and initialization support

zes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans --- bsd-user/riscv/target_arch_thread.h | 47 + 1 file changed, 47 insertions(+) create mode 1

[PATCH v2 13/17] bsd-user: Define RISC-V signal handling structures and constants

From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_signal.h

[PATCH v2 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 14 ++ 1 file changed, 14 insertions

[PATCH v2 10/17] bsd-user: Define RISC-V VM parameters and helper functions

-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_vmparam.h | 53 1 file changed, 53 insertions(+) create mode 100644 bsd-user/riscv/target_arch_vmparam.h diff --git a/bsd-user/riscv/target_arch_vmparam.h

[PATCH v2 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b

[PATCH 13/23] Add ARM AArch64 ELF definitions for bsd-user

From: Stacey Son Defined mmap and dynamic load adresses and set various elf parameters Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans --- bsd-user/aarch64/target_arch_elf.h | 37 ++ 1 file changed, 37 insertions(+) create mode

[PATCH 01/23] Add CPU initialization function

From: Stacey Son Addded function to initialize ARM CPU and to check if it supports 64 bit mode Signed-off-by: Ajeet Singh Signed-off-by: Stacey Son --- bsd-user/aarch64/target_arch_cpu.h | 42 ++ 1 file changed, 42 insertions(+) create mode 100644 bsd-user

[PATCH 11/23] Update ARM AArch64 VM parameter definitions for bsd-user

From: Stacey Son Defined address spaces for FreeBSD/arm64 and added function for getting stack pointer from CPU and setting a return value. Signed-off-by: Stacey Son Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Co-authored-by: Sean Bruno Co-authored-by: Warner Losh --- bsd-user

[PATCH 04/23] AArch64 specific CPU for bsd-user

From: Stacey Son Function to set and recieve thread-local-storage value from tpidr_el0 register Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_cpu.c | 34 ++ 1 file changed, 34 insertions(+) create mode 100644 bsd-user

[PATCH 15/23] Add function to retrieve ARM AArch64 hardware capabilities

From: Warner Losh The function initializes default hardware capabilities and finds additional features using the `GET_FEATURE_ID` macro Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_elf.h | 38 ++ 1 file changed, 38

[PATCH 14/23] Add ARM AArch64 hardware capability definitions

From: Warner Losh Defined a huge list of hardware capabilites and added macros for retrieving hwcap flags Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_elf.h | 61 ++ 1 file changed, 61 insertions(+) diff --git a/bsd-user

[PATCH 05/23] Managing CPU register for BSD-USER

From: Stacey Son Added structure for storing register states Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Sean Bruno --- bsd-user/aarch64/target_syscall.h | 51 +++ 1 file changed, 51 insertions(+) create mode 100644 bsd-user/aarch64

[PATCH 17/23] Add ARM AArch64 sigcode setup function for bsd-user

From: Stacey Son signal trampoline function initializes a sequence of instructions to handle signal returns and exits, and copies this code to the target offset. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_sigtramp.h | 48 + 1

[PATCH 02/23] Added CPU loop function

From: Stacey Son CPU loop function to handle exceptions and emulate execution of instructions Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Co-authored-by: Sean Bruno Co-authored-by: Jessica Clarke --- bsd-user/aarch64/target_arch_cpu.h | 132

[PATCH 21/23] Add setup_sigframe_arch function for ARM AArch64 in bsd-user

From: Warner Losh The function utilizes the `get_mcontext` function to retrieve the machine context for the current CPUARMState Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh --- bsd-user/aarch64/signal.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/bsd-user

[PATCH 07/23] Add ARM AArch64 TLS Management Prototypes for BSD-User

From: Stacey Son Prototypes for setting and getting TLS( thread local storage) Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch.h | 28 1 file changed, 28 insertions(+) create mode 100644 bsd-user/aarch64/target_arch.h diff

[PATCH 16/23] Add function to retrieve additional ARM AArch64 hwcap

From: Warner Losh Function to retrieve the extended hardware capability flags Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_elf.h | 29 + 1 file changed, 29 insertions(+) diff --git a/bsd-user/aarch64/target_arch_elf.h b

[PATCH 00/23] ARM AArch64 Support for BSD

making sure to credit all the authors correctly Stacey Son (18): Add CPU initialization function Added CPU loop function Added function to clone CPU state AArch64 specific CPU for bsd-user Managing CPU register for BSD-USER Add Aarch64 register handling Add ARM AArch64 TLS Management

[PATCH 09/23] Add thread setup for BSD-USER

From: Stacey Son Function for setting up thread upcall which will add thread support to BSD-User Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke --- bsd-user/aarch64/target_arch_thread.h | 45 +++ 1 file changed, 45 insertions

[PATCH 10/23] Add thread initialization for BSD-USER

From: Stacey Son Initializes thread's register state Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke --- bsd-user/aarch64/target_arch_thread.h | 16 1 file changed, 16 insertions(+) diff --git a/bsd-user/aarch64/target_arch_thread

[PATCH 18/23] Add ARM AArch64 specific signal definitions for bsd-user

From: Stacey Son Defined register indices and sizes,introduced structures to represent general purpose registers, floating point registers, and machine context Signed-off-by: Stacey Son Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh --- bsd-user/aarch64

[PATCH 08/23] Add Aarch64 sysarch() system call emulation for BSD-USER

From: Stacey Son Initial implementation of sysarch() syscall and a printing function Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_sysarch.h | 42 ++ 1 file changed, 42 insertions(+) create mode 100644 bsd-user/aarch64

[PATCH 03/23] Added function to clone CPU state

From: Stacey Son Function can copy cpu state to create new thread Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_cpu.h | 17 + 1 file changed, 17 insertions(+) diff --git a/bsd-user/aarch64/target_arch_cpu.h b/bsd-user/aarch64

[PATCH 19/23] Add ARM AArch64 signal trampoline argument setup for bsd-user

From: Stacey Son function to set up signal handler arguments it populates register values in `CPUARMState` based on the provided signal, signal frame, signal action, and frame address Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch64/signal.c | 53

[PATCH 23/23] Add get_ucontext_sigreturn function

From: Stacey Son Function checks the processor state to ensure that the current execution mode is EL0 and no flags indicating interrupts or exceptions are set Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch64/signal.c | 18 ++ 1 file changed, 18

[PATCH 22/23] Add set_mcontext function for ARM AArch64 in bsd-user

From: Stacey Son The function copies register values from the provided target_mcontext_t structure to the CPUARMState registers Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch64/signal.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/bsd

[PATCH 20/23] Add get_mcontext function for ARM AArch64 in bsd-user

From: Stacey Son function to retrieve machine context,it populates the provided target_mcontext_t structure with information from the CPUARMState registers Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans --- bsd-user/aarch64/signal.c | 30

[PATCH 06/23] Add Aarch64 register handling

From: Stacey Son Header file for managing CPU register states in FreeBSD user mode Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_reg.h | 56 ++ 1 file changed, 56 insertions(+) create mode 100644 bsd-user/aarch64

[PATCH 12/23] Add ability to get rval2

From: Warner Losh Function accesses the x1 register which holds the value Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_vmparam.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/bsd-user/aarch64/target_arch_vmparam.h b/bsd-user/aarch64

[PATCH v3 10/17] bsd-user: Define RISC-V VM parameters and helper functions

-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_vmparam.h | 53 1 file changed, 53 insertions(+) create mode 100644 bsd-user/riscv/target_arch_vmparam.h diff --git a/bsd-user/riscv/target_arch_vmparam.h

[PATCH v3 07/17] bsd-user: Add RISC-V signal trampoline setup function

From: Mark Corbin Implemented the 'setup_sigtramp' function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_sigtr

[PATCH v3 04/17] bsd-user: Implement RISC-V TLS register setup

From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajee

[PATCH v3 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- configs/targets/riscv64-bsd-user.mak | 4 1 file changed, 4 insertions(+) create mode 100644 configs/targets

[PATCH v3 00/17] bsd-user: Comprehensive RISCV Support

Key Changes Compared to Version 2: Patch 1: changed loop conditions to avoid setting r0 Patch 7: replaced manual byte swapping with const_le32 Patch 9: used ROUND_DOWN to align the stack Mark Corbin (15): bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Add RISC-V CPU exec

[PATCH v3 01/17] bsd-user: Implement RISC-V CPU initialization and main loop

From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored

[PATCH v3 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

From: Mark Corbin Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin Signed-off-by: Warner Losh Signed-off

[PATCH v3 09/17] bsd-user: Add RISC-V thread setup and initialization support

zes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans --- bsd-user/riscv/target_arch_thread.h | 47 + 1 file changed, 47 insertions(+) create mode 1

[PATCH v3 11/17] bsd-user: Define RISC-V system call structures and constants

From: Mark Corbin Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet

[PATCH v3 06/17] bsd-user: Define RISC-V register structures and register copying

ure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_reg.h | 88 1 file changed, 88 insertions(+) create mode 100644 bsd-user/riscv

[PATCH v3 12/17] bsd-user: Add generic RISC-V64 target definitions

From: Warner Losh Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh

[PATCH v3 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 14 ++ 1 file changed, 14 insertions

[PATCH v3 13/17] bsd-user: Define RISC-V signal handling structures and constants

From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_signal.h

[PATCH v3 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling

: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 94 1 file changed, 94 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h index

[PATCH v3 15/17] bsd-user: Implement 'get_mcontext' for RISC-V

orbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/signal.c | 53 + 1 file changed, 53 insertions(+) diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signa

[PATCH v3 14/17] bsd-user: Implement RISC-V signal trampoline setup functions

the signal handler address, and the signal frame pointer. 'setup_sigframe_arch()': Initializes the signal frame with the current machine context.This function copies the context from the CPU state to the signal frame, preparing it for the signal handler. Signed-off-by: Mark Corbin Signed

[PATCH v3 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b

[PATCH v3 08/17] bsd-user: Implement RISC-V sysarch system call emulation

From: Mark Corbin Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corb

[PATCH v4 00/17] bsd-user: Comprehensive RISCV Support

Key Changes Compared to Version 3: Minor comment changes and all the patches have been reviewed by Richard Henderson Mark Corbin (15): bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Implement RISC-V CPU regi

[PATCH v4 09/17] bsd-user: Add RISC-V thread setup and initialization support

zes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_thread.h | 47 + 1 file ch

[PATCH v4 10/17] bsd-user: Define RISC-V VM parameters and helper functions

-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_vmparam.h | 53 1 file changed, 53 insertions(+) create mode 100644 bsd-user/riscv/target_arch_vmparam.h diff --git a/bsd-user/riscv/target_arch_vmparam.h

[PATCH v4 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

From: Mark Corbin Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin Signed-off-by: Warner Losh Signed-off

[PATCH v4 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- configs/targets/riscv64-bsd-user.mak | 4 1 file changed, 4 insertions(+) create mode 100644 configs/targets

[PATCH v4 01/17] bsd-user: Implement RISC-V CPU initialization and main loop

From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored

[PATCH v4 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 14 ++ 1 file changed, 14 insertions

[PATCH v4 11/17] bsd-user: Define RISC-V system call structures and constants

From: Mark Corbin Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet

[PATCH v4 13/17] bsd-user: Define RISC-V signal handling structures and constants

From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_signal.h

[PATCH v4 12/17] bsd-user: Add generic RISC-V64 target definitions

From: Warner Losh Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh

[PATCH v4 14/17] bsd-user: Implement RISC-V signal trampoline setup functions

the signal handler address, and the signal frame pointer. 'setup_sigframe_arch()': Initializes the signal frame with the current machine context.This function copies the context from the CPU state to the signal frame, preparing it for the signal handler. Signed-off-by: Mark Corbin Signed

[PATCH v4 04/17] bsd-user: Implement RISC-V TLS register setup

From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajee

[PATCH v4 08/17] bsd-user: Implement RISC-V sysarch system call emulation

From: Mark Corbin Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corb

[PATCH v4 15/17] bsd-user: Implement 'get_mcontext' for RISC-V

orbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/signal.c | 53 + 1 file changed, 53 insertions(+) diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signa

[PATCH v4 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b

[PATCH v4 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling

: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 94 1 file changed, 94 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h index

[PATCH v4 07/17] bsd-user: Add RISC-V signal trampoline setup function

From: Mark Corbin Implemented the 'setup_sigtramp' function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_sigtr

[PATCH v4 06/17] bsd-user: Define RISC-V register structures and register copying

ure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_reg.h | 88 1 file changed, 88 insertions(+) create mode 100644 bsd-user/riscv

[PATCH v5 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling

: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 94 1 file changed, 94 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h index

[PATCH v5 04/17] bsd-user: Implement RISC-V TLS register setup

From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajee

[PATCH v5 06/17] bsd-user: Define RISC-V register structures and register copying

ure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_reg.h | 88 1 file changed, 88 insertions(+) create mode 100644 bsd-user/riscv

[PATCH v5 11/17] bsd-user: Define RISC-V system call structures and constants

From: Mark Corbin Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet

[PATCH v5 07/17] bsd-user: Add RISC-V signal trampoline setup function

From: Mark Corbin Implemented the 'setup_sigtramp' function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_sigtr

[PATCH v5 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b

[PATCH v5 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 14 ++ 1 file changed, 14 insertions

[PATCH v5 10/17] bsd-user: Define RISC-V VM parameters and helper functions

-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_vmparam.h | 53 1 file changed, 53 insertions(+) create mode 100644 bsd-user/riscv/target_arch_vmparam.h diff --git a/bsd-user/riscv/target_arch_vmparam.h

[PATCH v5 01/17] bsd-user: Implement RISC-V CPU initialization and main loop

From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored

[PATCH v5 08/17] bsd-user: Implement RISC-V sysarch system call emulation

From: Mark Corbin Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corb

[PATCH v5 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- configs/targets/riscv64-bsd-user.mak | 4 1 file changed, 4 insertions(+) create mode 100644 configs/targets

[PATCH v5 14/17] bsd-user: Implement RISC-V signal trampoline setup functions

the signal handler address, and the signal frame pointer. 'setup_sigframe_arch()': Initializes the signal frame with the current machine context.This function copies the context from the CPU state to the signal frame, preparing it for the signal handler. Signed-off-by: Mark Corbin Signed

[PATCH v5 15/17] bsd-user: Implement 'get_mcontext' for RISC-V

orbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/signal.c | 53 + 1 file changed, 53 insertions(+) diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signa

[PATCH v5 12/17] bsd-user: Add generic RISC-V64 target definitions

From: Warner Losh Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh

[PATCH v5 00/17] bsd-user: Comprehensive RISCV Support

Key Changes Compared to Version 4: Minor formatting changes Mark Corbin (15): bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Implement RISC-V CPU register cloning and reset functions bsd-user: Implement RIS

[PATCH v5 13/17] bsd-user: Define RISC-V signal handling structures and constants

From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_signal.h

[PATCH v5 09/17] bsd-user: Add RISC-V thread setup and initialization support

zes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_thread.h | 47 + 1 file ch

[PATCH v5 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

From: Mark Corbin Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin Signed-off-by: Warner Losh Signed-off

[PATCH v6 00/17] bsd-user: Comprehensive RISCV Support

Key Changes Compared to Version 5: In target_arch_sigtramp.h removed static const, as there was a compile-time constant issue Mark Corbin (15): bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Implement RISC-V

[PATCH v6 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b

[PATCH v6 13/17] bsd-user: Define RISC-V signal handling structures and constants

From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_signal.h

[PATCH v6 10/17] bsd-user: Define RISC-V VM parameters and helper functions

-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_vmparam.h | 53 1 file changed, 53 insertions(+) create mode 100644 bsd-user/riscv/target_arch_vmparam.h diff --git a/bsd-user/riscv/target_arch_vmparam.h

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