[PATCH qemu 0/1] target/riscv: Add Zilsd and Zcmlsd extension support

This patch adds support for the Zilsd and Zcmlsd extension, which is documented at https://github.com/riscv/riscv- zilsd/releases/tag/v0.9.0 lxx (1): target/riscv: Add Zilsd and Zcmlsd extension support target/riscv/cpu.c | 4 + target/riscv/cpu_cfg.h

[PATCH qemu 1/1] target/riscv: Add Zilsd and Zcmlsd extension support

From: lxx <1733205...@qq.com> This patch adds support for the Zilsd and Zcmlsd extension, which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0 Co-developed-by: SUN Dongya Co-developed-by: LIU Xu Co-developed-by: ZHAO Fujin --- target/riscv/cpu.c

[PATCH qemu] target/riscv: Add Zilsd and Zcmlsd extension support

From: lxx <1733205...@qq.com> This patch adds support for the Zilsd and Zcmlsd extension, which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0 Co-developed-by: SUN Dongya Co-developed-by: LIU Xu Co-developed-by: ZHAO Fujin --- target/riscv/cpu.c

[PATCH qemu v3 1/1] target/riscv: Add Zilsd and Zclsd extension support

From: lxx <1733205...@qq.com> This patch adds support for the Zilsd and Zclsd extension, which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0 Co-developed-by: SUN Dongya Co-developed-by: LIU Xu Co-developed-by: ZHAO Fujin --- target/riscv/cpu.c

[PATCH qemu v3 0/1] target/riscv: Add Zilsd and Zclsd extension support

Thanks for your previous reply. Here are some explanations for the previous questions: 1. In the previous version, the 'int flag' was used to distinguish whether an instruction was 'ld' or 'ldsp' for different processing. In this version, a boolean type 'is_1dsp' is defined to make the code cleare

[PATCH qemu v4 0/1] target/riscv: Add Zilsd and Zclsd extension support

Last reply: https://lists.gnu.org/archive/html/qemu- devel/2024-08/msg01631.html This version no longer separates the implementation of Zilsd and Zclsd extensions. lxx (1): target/riscv: Add Zilsd and Zclsd extension support target/riscv/cpu.c| 4 + target/riscv/cpu_

[PATCH qemu v4 1/1] target/riscv: Add Zilsd and Zclsd extension support

From: lxx <1733205...@qq.com> This patch adds support for the Zilsd and Zclsd extension, which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0 Co-developed-by: SUN Dongya Co-developed-by: LIU Xu Co-developed-by: ZHAO Fujin --- target/riscv/cpu.c

[PATCH qemu v5 1/1] target/riscv: Add Zilsd and Zclsd extension support

From: lxx <1733205...@qq.com> This patch adds support for the Zilsd and Zclsd extension, which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0 Co-developed-by: SUN Dongya Co-developed-by: LIU Xu Co-developed-by: ZHAO Fujin --- target/riscv/cpu.c

[PATCH qemu v5 0/1] target/riscv: Add Zilsd and Zclsd extension support

Fix for the last reply: https://lists.gnu.org/archive/html/qemu-devel/2024-08/msg02469.html lxx (1): target/riscv: Add Zilsd and Zclsd extension support target/riscv/cpu.c| 4 + target/riscv/cpu_cfg.h| 2 + target/riscv/insn16.decode

[PATCH qemu v2 0/1] target/riscv: Add Zilsd and Zcmlsd extension support

In this version of the patch: 1. Adjusted the code formatting issue 2. Optimize the processing of all instructions lxx (1): target/riscv: Add Zilsd and Zcmlsd extension support target/riscv/cpu.c | 4 + target/riscv/cpu_cfg.h | 2 + target/riscv/in

[PATCH qemu v2 1/1] target/riscv: Add Zilsd and Zcmlsd extension support

From: lxx <1733205...@qq.com> This patch adds support for the Zilsd and Zcmlsd extension, which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0 Co-developed-by: SUN Dongya Co-developed-by: LIU Xu Co-developed-by: ZHAO Fujin --- target/riscv/cpu.c

[PATCH qemu v6] target/riscv: Add Zilsd and Zclsd extension support

From: lxx <1733205...@qq.com> This patch adds support for the Zilsd and Zclsd extension, which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v0.10 Co-developed-by: SUN Dongya Co-developed-by: LIU Xu Co-developed-by: ZHAO Fujin --- target/riscv/cpu.c

[PATCH qemu v7 1/1] target/riscv: Add Zilsd and Zclsd extension support

From: lxx <1733205...@qq.com> This patch adds support for the Zilsd and Zclsd extension, which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v1.0 Co-developed-by: SUN Dongya Co-developed-by: LIU Xu Co-developed-by: ZHAO Fujin --- target/riscv/cpu.c

[PATCH qemu v7 0/1] target/riscv: Add Zilsd and Zclsd extension support

The Zilsd extension implementation is synchronized to riscv-zilsd v1.0. lxx (1): target/riscv: Add Zilsd and Zclsd extension support target/riscv/cpu.c| 4 + target/riscv/cpu_cfg.h| 2 + target/riscv/insn16.decode| 8 ++ target/

[PATCH qemu v9 1/1] target/riscv: Add Zilsd and Zclsd extension support

From: lxx <1733205...@qq.com> This patch adds support for the Zilsd and Zclsd extension, which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v1.0 Signed-off-by: LIU Xu Co-developed-by: SUN Dongya Co-developed-by: ZHAO Fujin Reviewed-by: Alistair Francis --- target/riscv/

[PATCH qemu v9 0/1] target/riscv: Add Zilsd and Zclsd extension support

Thanks for Alistair's correction on the V8 version. Now Zclsd has been disabled for the "max" CPU as C and F are already enabled. lxx (1): target/riscv: Add Zilsd and Zclsd extension support target/riscv/cpu.c| 4 + target/riscv/cpu_cfg_fields.h.inc | 2 +

[PATCH qemu v8 1/1] target/riscv: Add Zilsd and Zclsd extension support

From: lxx <1733205...@qq.com> This patch adds support for the Zilsd and Zclsd extension, which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v1.0 Signed-off-by: LIU Xu Co-developed-by: SUN Dongya Co-developed-by: ZHAO Fujin Reviewed-by: Alistair Francis --- target/riscv/

[PATCH qemu v8 0/1] target/riscv: Add Zilsd and Zclsd extension support

Thanks for Alistair Francis's reply, and now this version has changed as follows: 1. Rebase to https://github.com/alistair23/qemu/tree/riscv-to- apply.next. 2. The Review-by information has been added. lxx (1): target/riscv: Add Zilsd and Zclsd extension support target/riscv/cpu.c

Re: [PATCH qemu v9 0/1] target/riscv: Add Zilsd and Zclsd extension support

>On Tue, Jun 17, 2025 at 4:29 PM ~liuxu wrote: >> >> Thanks for Alistair's correction on the V8 version. >> >> Now Zclsd has been disabled for the "max" CPU as C and F are already >> enabled. > >This is still broken with userspace mode: &g