From: Shaoqin Huang
Currently the ramfb device loads the vgabios-ramfb.bin unconditionally,
but only the x86 need the vgabios-ramfb.bin, this can cause that when
use the release package on arm64 it can't find the vgabios-ramfb.bin.
Because only seabios will use the vgabios-ramfb.bin, load the ro
Upon examining the current implementation for getting/setting SIMD
and SVE registers via remote GDB, there is a concern about mixed
endian support.
Consider the following snippet from a GDB session in which a SIMD
register's value is set via remote GDB where the QEMU host is little
endian and the
On 7/18/25 10:30, Peter Maydell wrote:
FEAT_SVE_B16B16 adds bfloat16 versions of the FMLA and FMLS insns in
the SVE floating-point multiply-add (indexed) insn group. Implement
these.
Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max")
Signed-off-by: Peter Maydell
---
target
On 7/18/25 10:30, Peter Maydell wrote:
In the part of the SVE DO_REDUCE macro used by the SVE2p1 FMAXQV,
FMINQV, etc insns, we incorrectly applied the H() macro twice when
calculating an offset to add to the vn pointer. This has no effect
on little-endian hosts but on big-endian hosts the two in
On 7/18/25 10:30, Peter Maydell wrote:
When we implemented the FMAXQV and FMINQV insns we accidentally
inverted the sense of the FPCR.AH test, so we gave the AH=1 behaviour
when FPCR.AH was zero, and vice-versa. (The difference is limited to
hadling of negative zero and NaN inputs.)
Fixes: 1de7
On 7/18/25 12:11, Peter Maydell wrote:
On Fri, 18 Jul 2025 at 18:46, Richard Henderson
wrote:
There is no such thing as vector extract.
Fixes: 932522a9ddc1 ("tcg/optimize: Fold and to extract during optimize")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3036
Signed-off-by: Richard
On 7/18/25 10:30, Peter Maydell wrote:
FEAT_SVE_B16B16 adds bfloat16 versions of the SVE floating point
(unpredicated) instructions, which are encoded via sz==0b00.
Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max")
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper.h
On 7/18/25 10:30, Peter Maydell wrote:
FEAT_SVE_B16B16 adds bfloat16 versions of the SVE floating point
(predicated) instructions, which are encoded via sz=0b00.
Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM; these are all the insns
in this group which do not change behaviour for AH=1.
We will deal
On 7/18/25 10:30, Peter Maydell wrote:
FEAT_SVE_B16B16 adds a bfloat16 version of the FMUL insn in the
floating-point multiply (indexed) instruction group. The encoding
is slightly bespoke; in our implementation we use MO_8 to indicate
bfloat16, as with the other B16B16 insns.
Fixes: 7b1613a1020
On 7/18/25 10:30, Peter Maydell wrote:
FEAT_SVE_B16B16 adds bfloat16 versions of the SVE floating point
(predicated) instructions, which are encoded via sz=0b00. Add the
BFMAX and BFMIN insns. These have separate behaviour for AH=1 and
AH=0; we have already implemented the AH=1 helper for the S
On 7/18/25 10:30, Peter Maydell wrote:
FEAT_SVE_B16B16 adds bfloat16 versions of the FMLA and FMLS insns in
the "SVE floating-point multiply-accumulate writing addend" group,
encoded as sz=0b00.
Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max")
Signed-off-by: Peter Maydell
-
On 7/18/25 10:30, Peter Maydell wrote:
For the LD1Q instruction (gather load of quadwords) we use the
LD1_zprz pattern with MO_128 elements. At this element size there is
no signed vs unsigned distinction, and we only set the 'u' bit in the
arg_LD1_zprz struct because we share the code and decod
On 7/18/25 10:30, Peter Maydell wrote:
The FMAXNMQV and FMINNMQV insns use the default NaN as their identity
value for inactive source vector elements. We open-coded this in
sve_helper.c, hoping to avoid a function call. However, this fails
to account for FPCR.AH=1 changing the default NaN value
The temporary egl fb scanout_tex_fb is only needed to facilitate the
blit to the display surface's texture (ssd->ds->texture). Therefore,
destroy it after the blit is submitted. And, also make sure that it
is empty initialized before it is actually used.
Fixes: f851cd65 ("ui/spice: Blit the scanou
From: Shaoqin Huang
Move the TYPE_* to a new file hw/vfio/types.h because the
TYPE_VFIO_PCI will be used in later patch, but directly include the
hw/vfio/pci.h can cause some compilation error when cross build the
windows version.
The hw/vfio/types.h can be included to mitigate that problem.
Si
gs/display-20250718-pull-request
for you to fetch changes up to d5fcf0d960d893b1765e6388cefca9c690839267:
hw/i386: Add the ramfb romfile compatibility (2025-07-18 21:41:57 +0200)
Load ramfb vgabios o
On 7/18/25 21:43, Gerd Hoffmann wrote:
From: Shaoqin Huang
Move the TYPE_* to a new file hw/vfio/types.h because the
TYPE_VFIO_PCI will be used in later patch, but directly include the
hw/vfio/pci.h can cause some compilation error when cross build the
windows version.
The hw/vfio/types.h can
TF-A needs to be patched to enable support for FEAT_TCR2 and
FEAT_SCTLR2. This new image contains updated firmware.
Signed-off-by: Pierrick Bouvier
---
tests/functional/test_aarch64_rme_sbsaref.py | 64 ---
tests/functional/test_aarch64_rme_virt.py| 85 +++-
2 fil
The FEAT_MEC series [1] introduces FEAT_TCR2 and FEAT_SCTLR2.
TF-A needs to be aware of that change to allow accesses to those registers, and
thus must be patched [2] to enable this for QEMU platforms.
Concerned test images need to be updated to allow them to boot.
[1]
https://lore.kernel.org/qe
Hi Richard,
On 7/18/25 8:58 PM, Pierrick Bouvier wrote:
The FEAT_MEC series [1] introduces FEAT_TCR2 and FEAT_SCTLR2.
TF-A needs to be aware of that change to allow accesses to those registers, and
thus must be patched [2] to enable this for QEMU platforms.
Concerned test images need to be upda
TF-A needs to be patched to enable support for FEAT_TCR2 and
FEAT_SCTLR2. This new image contains updated firmware.
Signed-off-by: Pierrick Bouvier
---
.../test_aarch64_device_passthrough.py| 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/tests/fu
On 7/15/25 2:23 PM, Pierrick Bouvier wrote:
The FEAT_MEC series [1] introduces FEAT_TCR2 and FEAT_SCTLR2.
TF-A needs to be aware of that change to allow accesses to those registers, and
thus must be patched [2] to enable this for QEMU platforms.
Concerned test images need to be updated to allow
On 7/18/25 10:38 AM, Richard Henderson wrote:
There is no such thing as vector extract.
Fixes: 932522a9ddc1 ("tcg/optimize: Fold and to extract during optimize")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3036
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 2 +-
1 file ch
From: Shaoqin Huang
ramfb is a sysbus device so it can only used for machine types where it
is explicitly enabled:
# git grep machine_class_allow_dynamic_sysbus_dev.*TYPE_RAMFB_DEVICE
hw/arm/virt.c:machine_class_allow_dynamic_sysbus_dev(mc,
TYPE_RAMFB_DEVICE);
hw/i386
On Fri, 18 Jul 2025 at 18:46, Richard Henderson
wrote:
>
> There is no such thing as vector extract.
>
> Fixes: 932522a9ddc1 ("tcg/optimize: Fold and to extract during optimize")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3036
> Signed-off-by: Richard Henderson
> ---
> tcg/optimiz
char/pl011/src/lib.rs
@@ -13,7 +13,6 @@
//! the [`registers`] module for register types.
mod device;
-mod device_class;
mod registers;
pub use device::pl011_create;
---
base-commit: 3656e761bcdd207b7759cdcd608212d2a6f9c12d
change-id: 20250718-rust-pl011-cleanup-1a8e125eaf04
--
γαῖα πυρί μιχθήτω
On Fri, Jul 18, 2025 at 07:59:50AM +0200, Markus Armbruster wrote:
> Markus Armbruster writes:
>
> > Adam Williamson writes:
> >
> >> In cfcacba an `error_report` was added to this file, but the
> >> corresponding include of `qemu/error-report.h` was missed. This
> >> only becomes apparent when
On Fri, 18 Jul 2025 at 07:29, Vivek Kasireddy wrote:
>
> The temporary egl fb scanout_tex_fb is only needed to facilitate the
> blit to the display surface's texture (ssd->ds->texture). Therefore,
> destroy it after the blit is submitted. And, also make sure that it
> is empty initialized before i
Common function loongarch_check_pte() is to check tlb entry, return
the physical address and access priviledge. Also it can be used with
page table entry, which is used in page table walker.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu-mmu.h| 8
target/loongarch/cpu_helper.c
Move function definition specified with kvm to the corresponding
directory. Also remove header file "cpu.h" including outside of
macro QEMU_KVM_LOONGARCH_H.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 1 +
target/loongarch/cpu.h | 9 -
target/loongarc
There is some enhance about LoongArch mmu tcg emulation, add new
header file cpu-mmu.h and function loongarch_check_pte(). Function
loongarch_check_pte() can work on both TLB entry and pte entry.
This patchset mainly is code cleanup and enhancement, its main
purpose is to work for hardware page ta
Function loongarch_cpu_post_init() is implemented and used in the
same file target/loongarch/cpu.c, it can be defined as static function.
This patch moves implementation about function loongarch_cpu_post_init()
before it is referenced. And it is only code movement, no function
change.
Signed-off-
New header file cpu-mmu.h is added and move mmu relative function
declaration to this file.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu-mmu.h| 30 ++
target/loongarch/cpu.c| 1 +
target/loongarch/cpu_helper.c | 1 +
target/loongarch/inte
Function loongarch_check_pte() can get physical address and access
priviledge, it works on both TLB entry and pte entry. It can be used
at page table walking.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu_helper.c | 35 ++-
1 file changed, 10 insertions(+), 25
Qemu TCG provides some tlb flushing API, tlb can be flushed with
specified mmu idx and virtual address. Here fine-grained tlb flush
method is used.
Signed-off-by: Bibo Mao
---
target/loongarch/tcg/tlb_helper.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git
With API tlb_flush_range_by_mmuidx(), bitmap method of mmu idx should
be used rather than itself. Also mmu idx comes from page table entry
information rather current running mode. With page table entry,
global bit for MMU_KERNEL_IDX, otherwise it is MMU_USER_IDX.
Signed-off-by: Bibo Mao
---
targ
With VTLB different TLB entry may have different page size, and
page size is set in PS field of TLB misc. However with STLB, all the
TLB entries have the same page size, page size comes from register
CSR_STLBPS, PS field of TLB misc is not used.
Here PS field of TLB misc is used with all TLB entri
On 17.07.2025 18:23, Paolo Bonzini wrote:
KVM emulates the ARCH_CAPABILITIES on x86 for both Intel and AMD
cpus, although the IA32_ARCH_CAPABILITIES MSR is an Intel-specific
MSR and it makes no sense to emulate it on AMD.
As a consequence, VMs created on AMD with qemu -cpu host and using
KVM wil
> -Original Message-
> From: Nicolin Chen
> Sent: Friday, July 18, 2025 5:14 AM
> To: Shameerali Kolothum Thodi
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org;
> eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nvidia.com;
> ddut...@redhat.com; berra...@redhat.com; imamm...@redh
> -Original Message-
> From: Nicolin Chen
> Sent: Friday, July 18, 2025 9:12 AM
> To: Shameerali Kolothum Thodi
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org;
> eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nvidia.com;
> ddut...@redhat.com; berra...@redhat.com; imamm...@redh
Similar to virtio infra, vhost core maintains the features status
in the full extended format and allows the devices to implement
extended version of the getter/setter.
Note that 'protocol_features' are not extended: they are only
used by vhost-user, and the latter device is not going to implement
Extend the features configuration space to 128 bits, and allow the
common read/write operation to access all of it.
On migration, save the 128 bit version of the features only if the
upper bits are non zero. Relay reset to clear all the feature
space before load.
Signed-off-by: Paolo Abeni
---
v
Some virtualized deployments use UDP tunnel pervasively and are impacted
negatively by the lack of GSO support for such kind of traffic in the
virtual NIC driver.
The virtio_net specification recently introduced support for GSO over
UDP tunnel, and the kernel side of the implementation has been me
The set_offload() argument list is already pretty long and
we are going to introduce soon a bunch of additional offloads.
Replace the offload arguments with a single struct and update
all the relevant call-sites.
No functional changes intended.
Signed-off-by: Paolo Abeni
---
Note: I maintained
Extend the VirtioDeviceFeatures struct with an additional u64
to track unknown features in the 64-127 bit range and decode
the full virtio features spaces for vhost and virtio devices.
Also add entries for the soon-to-be-supported virtio net GSO over
UDP features.
Signed-off-by: Paolo Abeni
---
The virtio specifications allows for up to 128 bits for the
device features. Soon we are going to use some of the 'extended'
bits features for the virtio net driver.
Add support to allow extended features negotiation on a per
devices basis. Devices willing to negotiated extended features
need to i
Use the extended types and helpers to manipulate the virtio_net
features.
Note that offloads are still 64bits wide, as per specification,
and extended offloads will be mapped into such range.
Signed-off-by: Paolo Abeni
---
v2 -> v3:
- rebased on top of 2deec9ab7d ("virtio-net: Move
virtio_
Update headers to include the virtio GSO over UDP tunnel features
Signed-off-by: Paolo Abeni
--
Note: while the relevant change are not into Linus's tree yet, they have
been merged in the net-next tree and they should land into the vanilla
tree during the next merge window.
---
include/standard-
Provide extended version of the features manipulation helpers,
and let the device initialization deal with the full features space,
adjusting the relevant format strings accordingly.
Signed-off-by: Paolo Abeni
---
v2 -> v3:
- use virtio_features_andnot return value instead of virtio_features_em
On 7/18/25 11:12, Manos Pitsidianakis wrote:
Add a CLI argument that takes fnmatch(3)-style patterns as value and can
be specified many times. Only tests that match the pattern will be
executed. This argument is passed to unittest.main which takes the same
argument.
Signed-off-by: Manos Pitsidia
Queued, thanks. But for 10.2 maybe we could alternate in preparing pull
requests? We'll see.
Paolo
On Fri, Jul 18, 2025 at 08:01:22AM +, Shameerali Kolothum Thodi wrote:
> > > +int irq = platform_bus_get_irqn(pbus, sbdev, 0);
> > > +hwaddr base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
> > > +MachineState *ms = MACHINE(vms);
> > > +
> > > +if (!(vms->bootinfo.firmware_loa
Hi Steve
I tested your patch which hit a problem under enable/disable nic mq
state(The full test scenario is live migration vm at local under
enable/disable vm nic mq state):
Run command: /qemu-img info /home/images/vm1.qcow2 --output=json
Error info: qemu-img: Could not open '/home/images/vm1.qco
If the driver uses any of the extended features (i.e. 64 or above),
store the extended features range (64-127 bits).
At load time, let legacy features initialize the full features range
and pass it to the set helper; sub-states loading will have filled-up
the extended part as needed.
This is one
Leverage the kernel extended features manipulation ioctls(), if
available, and fallback to old ops otherwise. Error out when setting
extended features but kernel support is not available.
Note that extended support for get/set backend features is not needed,
as the only feature that can be changed
When any host or guest GSO over UDP tunnel offload is enabled the
virtio net header includes the additional tunnel-related fields,
update the size accordingly.
Push the GSO over UDP tunnel offloads all the way down to the tap
device extending the newly introduced NetFeatures struct, and
eventually
Tap devices support GSO over UDP tunnel offload. Probe for such
feature in a similar manner to other offloads.
GSO over UDP tunnel needs to be enabled in addition to a "plain"
offload (TSO or USO).
No need to check separately for the outer header checksum offload:
the kernel is going to support b
The virtio specifications allows for up to 128 bits for the
device features. Soon we are going to use some of the 'extended'
bits features (bit 64 and above) for the virtio net driver.
Represent the virtio features bitmask with a fixes size array, and
introduce a few helpers to help manipulate the
On Fri, Jul 18, 2025 at 12:37 PM Paolo Bonzini wrote:
>
> On 7/18/25 11:12, Manos Pitsidianakis wrote:
> > Add a CLI argument that takes fnmatch(3)-style patterns as value and can
> > be specified many times. Only tests that match the pattern will be
> > executed. This argument is passed to unitte
On LoongArch system, there are two pages with one TLB entry. If the
whole TLB entry is flushed, two pages will be flushed. Otherwise if
tlb is flushed one by one, page size is one page at a time.
Also virtual address of odd page is fixed here.
Signed-off-by: Bibo Mao
---
target/loongarch/tcg/tl
Signed-off-by: Ayush Mishra
---
hw/nvme/ctrl.c | 63
include/block/nvme.h | 21 +++
2 files changed, 84 insertions(+)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 93c950b5b2..5ef2282fd2 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme
This series adds support for:
- Log Page ID 0x00: Supported Log Pages
- Log Page ID 0x12: Feature Identifiers Supported and Effects
These changes improve compliance with newer NVMe specifications and enhance
introspection capabilities for NVMe devices under QEMU.
Tested using:
- Custom log page
Signed-off-by: Ayush Mishra
---
hw/nvme/ctrl.c | 32
hw/nvme/nvme.h | 2 ++
include/block/nvme.h | 11 +++
3 files changed, 45 insertions(+)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index e62c6a3588..93c950b5b2 100644
--- a/hw/nvme/ctrl.c
On 7/18/25 09:21, Michael Tokarev wrote:
On 17.07.2025 18:23, Paolo Bonzini wrote:
KVM emulates the ARCH_CAPABILITIES on x86 for both Intel and AMD
cpus, although the IA32_ARCH_CAPABILITIES MSR is an Intel-specific
MSR and it makes no sense to emulate it on AMD.
As a consequence, VMs created on
On Fri, Jul 18, 2025 at 08:22:09AM +, Shameerali Kolothum Thodi wrote:
> > So, my question was: where do we set the number of 4 to the sbdev?
> > As platform_bus_get_irqn() returned very correctly with 0, 4, 8,
> > and so on..
>
> See smmu_realize() --> smmu_init_irq()
>
> And then in virt_ma
Tested this patch v2 again,everything works fine.
Tested-by: Lei Yang
On Wed, Jul 16, 2025 at 3:29 PM Vladimir Sementsov-Ogievskiy <
vsement...@yandex-team.ru> wrote:
> Theoretically tap_read_packet() may return size less than
> s->host_vnet_hdr_len, and next, we'll work with negative size
> (i
Add CLI argument to list tests and exit.
Example output (current dir is build directory under root dir):
$ export PYTHONPATH=../python:../tests/functional
$ export QEMU_TEST_QEMU_BINARY="$(pwd)/qemu-system-aarch64"
$ ./pyvenv/bin/python3 ../tests/functional/test_aarch64_virt.py --list-tests
, 39 insertions(+), 6 deletions(-)
---
base-commit: 3656e761bcdd207b7759cdcd608212d2a6f9c12d
change-id: 20250718-functional_tests_args-12cdb5e56d84
prerequisite-change-id: 20250716-functional_tests_debug_arg-aa0a5f6b9375:v2
prerequisite-patch-id: 4ccc8f39ffb382d31c8e6450c43a5f8d177af044
--
γαῖα πυρί
Add CLI arg to keep scratch files after test execution, equivalent to
setting QEMU_TEST_KEEP_SCRATCH env var.
Suggested-by: Alex Bennée
Signed-off-by: Manos Pitsidianakis
---
tests/functional/qemu_test/testcase.py | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git
Add a CLI argument that takes fnmatch(3)-style patterns as value and can
be specified many times. Only tests that match the pattern will be
executed. This argument is passed to unittest.main which takes the same
argument.
Signed-off-by: Manos Pitsidianakis
---
tests/functional/qemu_test/testcase
On Thu, Jul 17, 2025 at 01:34:13PM +0300, Manos Pitsidianakis wrote:
> Add argument parsing to functional tests to improve developer experience
> when running individual tests. All logs are printed to stdout
> interspersed with TAP output.
>
> Example usage, assuming current build directory with q
On Fri, Jul 18, 2025 at 12:20 PM Daniel P. Berrangé wrote:
>
> On Thu, Jul 17, 2025 at 01:34:13PM +0300, Manos Pitsidianakis wrote:
> > Add argument parsing to functional tests to improve developer experience
> > when running individual tests. All logs are printed to stdout
> > interspersed with T
On Thu, Jul 17, 2025 at 12:34:48PM +0200, Paolo Bonzini wrote:
> Date: Thu, 17 Jul 2025 12:34:48 +0200
> From: Paolo Bonzini
> Subject: [PATCH] target/i386: do not expose ARCH_CAPABILITIES on AMD CPU
> X-Mailer: git-send-email 2.50.1
>
> KVM emulates the ARCH_CAPABILITIES on x86 for both Intel an
On Fri, Jul 18, 2025 at 10:52:34AM +0200, Paolo Abeni wrote:
Extend the VirtioDeviceFeatures struct with an additional u64
to track unknown features in the 64-127 bit range and decode
the full virtio features spaces for vhost and virtio devices.
Also add entries for the soon-to-be-supported virt
Add CLI arg to keep scratch files after test execution, equivalent to
setting QEMU_TEST_KEEP_SCRATCH env var.
Suggested-by: Alex Bennée
Signed-off-by: Manos Pitsidianakis
---
tests/functional/qemu_test/testcase.py | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git
Add CLI argument to list tests and exit.
Example output (current dir is build directory under root dir):
$ export PYTHONPATH=../python:../tests/functional
$ export QEMU_TEST_QEMU_BINARY="$(pwd)/qemu-system-aarch64"
$ ./pyvenv/bin/python3 ../tests/functional/test_aarch64_virt.py --list-tests
Add a CLI argument that takes fnmatch(3)-style patterns as value and can
be specified many times. Only tests that match the pattern will be
executed. This argument is passed to unittest.main which takes the same
argument.
Signed-off-by: Manos Pitsidianakis
---
tests/functional/qemu_test/testcase
Pitsidianakis
---
Changes in v2:
- Fixed invalid -k value passing when -k was specified more than once
(thanks Paolo)
- Link to v1:
https://lore.kernel.org/qemu-devel/20250718-functional_tests_args-v1-0-54d4c6207...@linaro.org
---
Manos Pitsidianakis (3):
tests/functional: add --keep
On Fri, Jul 18, 2025 at 10:52:36AM +0200, Paolo Abeni wrote:
Provide extended version of the features manipulation helpers,
and let the device initialization deal with the full features space,
adjusting the relevant format strings accordingly.
Signed-off-by: Paolo Abeni
---
v2 -> v3:
- use vir
Daniel P. Berrangé writes:
> On Fri, Jul 18, 2025 at 07:59:50AM +0200, Markus Armbruster wrote:
>> Markus Armbruster writes:
>>
>> > Adam Williamson writes:
>> >
>> >> In cfcacba an `error_report` was added to this file, but the
>> >> corresponding include of `qemu/error-report.h` was missed.
On Fri, Jul 18, 2025 at 10:52:39AM +0200, Paolo Abeni wrote:
When any host or guest GSO over UDP tunnel offload is enabled the
virtio net header includes the additional tunnel-related fields,
update the size accordingly.
Push the GSO over UDP tunnel offloads all the way down to the tap
device ex
The passt networking backend uses functions from the GIO library,
such as g_subprocess_launcher_new(), to manage its daemon process.
So, building with passt enabled requires GIO to be available.
If we enable passt and disable gio the build fails during linkage with
undefined reference errors:
/
On Fri, Jul 18, 2025 at 03:44:20PM +0200, Paolo Abeni wrote:
On 7/18/25 3:22 PM, Stefano Garzarella wrote:
On Fri, Jul 18, 2025 at 10:52:39AM +0200, Paolo Abeni wrote:
diff --git a/net/tap.c b/net/tap.c
index 23c6c118e7..2dfa843547 100644
--- a/net/tap.c
+++ b/net/tap.c
@@ -62,6 +62,8 @@ static
On Fri, Jul 18, 2025 at 03:31:10PM +0200, Laurent Vivier wrote:
> The passt networking backend uses functions from the GIO library,
> such as g_subprocess_launcher_new(), to manage its daemon process.
> So, building with passt enabled requires GIO to be available.
>
> If we enable passt and disabl
On 7/18/25 9:28 AM, Vasant Hegde wrote:
Alejandro, Sairaj,
On 7/17/2025 7:18 PM, Alejandro Jimenez wrote:
On 7/17/25 2:07 AM, Michael S. Tsirkin wrote:
On Thu, Jul 17, 2025 at 11:17:05AM +0530, Sairaj Kodilkar wrote:
On 7/16/2025 6:59 PM, Michael S. Tsirkin wrote:
On Wed, Jul 16, 202
On 7/18/25 3:01 PM, Stefano Garzarella wrote:
> On Fri, Jul 18, 2025 at 10:52:36AM +0200, Paolo Abeni wrote:
>> @@ -234,7 +234,8 @@ struct vhost_net *vhost_net_init(VhostNetOptions
>> *options)
>> int r;
>> bool backend_kernel = options->backend_type == VHOST_BACKEND_TYPE_KERNEL;
>> st
On Thu, Jul 17, 2025 at 9:14 PM Cornelia Huck wrote:
>
> On Tue, Jul 15 2025, Daniel P. Berrangé wrote:
>
> > On Tue, Jul 15, 2025 at 09:16:24AM -0700, Andrea Bolognani wrote:
> >> On Tue, Jul 15, 2025 at 05:02:54PM +0100, Daniel P. Berrangé wrote:
> >> > On Tue, Jul 15, 2025 at 05:44:25PM +0200,
On Fri, Jul 18, 2025 at 10:52:33AM +0200, Paolo Abeni wrote:
Similar to virtio infra, vhost core maintains the features status
in the full extended format and allows the devices to implement
extended version of the getter/setter.
Note that 'protocol_features' are not extended: they are only
used
On 18/07/2025 15.31, Laurent Vivier wrote:
The passt networking backend uses functions from the GIO library,
such as g_subprocess_launcher_new(), to manage its daemon process.
So, building with passt enabled requires GIO to be available.
If we enable passt and disable gio the build fails during
When either the postcopy or return path capabilities are
enabled, the migration code will use the primary channel
for bidirectional I/O.
If either of those capabilities are enabled, the migration
code needs to mark the channel as expecting concurrent I/O
in order to activate the thread safety work
Add a QIO_CHANNEL_FEATURE_CONCURRENT_IO feature flag.
If this is set on a QIOChannelTLS session object, the TLS
session will be marked as requiring thread safety, which
will activate the workaround for GNUTLS bug 1717 if needed.
Signed-off-by: Daniel P. Berrangé
---
include/io/channel.h | 1 +
When TLS 1.3 is negotiated on a TLS session, GNUTLS will perform
automatic rekeying of the session after 16 million records. This
is done for all algorithms except CHACHA20_POLY1305 which does
not require rekeying.
Unfortunately the rekeying breaks GNUTLS' promise that it is safe
to use a gnutls_s
TL:DR: GNUTLS is liable to crash QEMU when live migration is run
with TLS enabled and a return path channel is present, if approx
64 GB of data is transferred. This is easily triggered in a 16 GB
VM with 4 CPUs, by running 'stress-ng --vm 4 --vm-bytes 80%' to
prevent convergance until 64 GB of RAM
We want some visibility on stderr when the GNUTLS thread
safety countermeasures are activated, to encourage people
to get the real fix deployed (once it exists). Some trace
points will also help if we see any further wierd crash
scenario we've not anticipated.
Reviewed-by: Daniel P. Berrangé
Sign
On Fri, Jul 18, 2025 at 10:52:39AM +0200, Paolo Abeni wrote:
When any host or guest GSO over UDP tunnel offload is enabled the
virtio net header includes the additional tunnel-related fields,
update the size accordingly.
Push the GSO over UDP tunnel offloads all the way down to the tap
device ex
On Fri, Jul 18, 2025 at 10:52:30AM +0200, Paolo Abeni wrote:
If the driver uses any of the extended features (i.e. 64 or above),
store the extended features range (64-127 bits).
At load time, let legacy features initialize the full features range
and pass it to the set helper; sub-states loading
On 7/15/2025 5:25 PM, Mark Cave-Ayland wrote:
> Use QOM casts to convert between VFIOPCIDevice and PCIDevice instead of
> accessing pdev directly.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/vfio/igd.c | 38 +-
> 1 file changed, 21 insertions(+), 17 deletio
On the ARM virt machine, there is currently no way to programmatically
discover the frequency of the UART reference clock solely through the use of
UEFI/ACPI (without the DTB). The SPCR table can include this information
as of revision 3.
Bump the revision to 3 and add the clock frequency of 24 MH
Hi Daniel,
Thank you so much for the review.
On Thu, Jul 17, 2025 at 05:32:14PM +0100, Daniel P. Berrangé wrote:
> On Thu, Jul 17, 2025 at 06:07:25AM +0530, Arun Menon wrote:
> > This is an incremental step in converting vmstate loading
> > code to report error via Error objects instead of direct
Signed-off-by: Vadim Chichikalyuk
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..2a30472d57 100644
--- a/tests/qtest/bios-tables-test-a
1 - 100 of 123 matches
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