[PATCH v8 03/16] backends/igvm: Add IGVM loader and configuration

Adds an IGVM loader to QEMU which processes a given IGVM file and applies the directives within the file to the current guest configuration. The IGVM loader can be used to configure both confidential and non-confidential guests. For confidential guests, the ConfidentialGuestSupport object for the

Re: [PATCH] pc-bios/s390-ccw: link statically

On 11/06/2025 07.54, Sertonix wrote: On Wed Jun 11, 2025 at 6:07 AM CEST, Michael Tokarev wrote: On 10.06.2025 23:36, Sertonix wrote: On Tue Jun 10, 2025 at 10:32 PM CEST, Michael Tokarev wrote: On 10.06.2025 20:58, Sertonix wrote: Adding -pie to LDFLAGS caused s390-ccw.img to become dynamic

[PATCH v8 04/16] hw/i386: Add igvm-cfg object and processing for IGVM files

An IGVM file contains configuration of guest state that should be applied during configuration of the guest, before the guest is started. This patch allows the user to add an igvm-cfg object to an X86 machine configuration that allows an IGVM file to be configured that will be applied to the guest

[PATCH v3 00/11] migration: Some enhancements and cleanups for 10.1

v1: https://lore.kernel.org/r/20250527215850.1271072-1-pet...@redhat.com v2: https://lore.kernel.org/r/20250609161855.6603-1-pet...@redhat.com v3 changelog: - Fix checkpatch issues on spaces etc. - Added Tested-by tags for Mario on relevant patches The series is based on a small patch from Yanfei

[PATCH v3 10/11] migration: Rewrite the migration complete detect logic

There're a few things off here in that logic, rewrite it. When at it, add rich comment to explain each of the decisions. Since this is very sensitive path for migration, below are the list of things changed with their reasonings. (1) Exact pending size is only needed for precopy not postcopy

Re: [PATCH v15 0/4] arm/virt: CXL support via pxb_cxl

On Fri, 13 Jun 2025 14:07:32 +0900 Itaru Kitayama wrote: > On Thu, Jun 12, 2025 at 02:43:34PM +0100, Jonathan Cameron wrote: > > v15: > > - Split the address map calculations and mmio setup into separate > > functions in patch 2, allowing v14 patch 3 to be dropped as not > > x86 and arm

[PATCH v3 06/14] migration/postcopy: Bring blocktime layer to ns level

With 64-bit fields, it is trivial. The caution is when exposing any values in QMP, it was still declared with milliseconds (ms). Hence it's needed to do the convertion when exporting the values to existing QMP queries. Reviewed-by: Fabiano Rosas Signed-off-by: Peter Xu --- migration/postcopy-

[PATCH v3 10/14] migration/postcopy: Cache the tid->vcpu mapping for blocktime

Looking up the vCPU index for each fault can be expensive when there're hundreds of vCPUs. Provide a cache for tid->vcpu instead with a hash table, then lookup from there. When at it, add another counter to record how many non-vCPU faults it gets. For example, the main thread can also access a gu

[PATCH v3 14/14] migration/postcopy: Add latency distribution report for blocktime

Add the latency distribution too for blocktime, using order-of-two buckets. It accounts for all the faults, from either vCPU or non-vCPU threads. With prior rework, it's very easy to achieve by adding an array to account for faults in each buckets. Sample output for HMP (while for QMP it's simply

[PATCH v3 11/11] migration/postcopy: Avoid clearing dirty bitmap for postcopy too

This is a follow up on the other commit "migration/ram: avoid to do log clear in the last round" but for postcopy. https://lore.kernel.org/r/20250514115827.3216082-1-yanfei...@bytedance.com I can observe more than 10% reduction of average page fault latency during postcopy phase with this optimiz

Re: [PATCH 1/6] MAX78000: Add MAX78000FTHR Machine

On Sat, 10 May 2025 at 07:57, wrote: > > This patch adds support for the MAX78000FTHR machine. > > The MAX78000FTHR contains a MAX78000 and a RISC-V core. This patch > implements only the MAX78000, which is Cortex-M4 based. > Details can be found at: > https://www.analog.com/media/en/technical-doc

[PATCH v3 00/14] migration/postcopy: Blocktime tracking overhaul

This series is based on the other series I posted here: Based-on: <20250609161855.6603-1-pet...@redhat.com> https://lore.kernel.org/r/20250609161855.6603-1-pet...@redhat.com v1: https://lore.kernel.org/r/20250527231248.1279174-1-pet...@redhat.com v2: https://lore.kernel.org/r/20250609191259.9053-

[PATCH v3 05/14] migration/postcopy: Drop PostcopyBlocktimeContext.start_time

Now with 64bits, the offseting using start_time is not needed anymore, because the array can always remember the whole timestamp. Then drop the unused parameter in get_low_time_offset() altogether. Reviewed-by: Fabiano Rosas Signed-off-by: Peter Xu --- migration/postcopy-ram.c | 10 --

[PATCH v3 07/14] migration/postcopy: Add blocktime fault counts per-vcpu

Add a field to count how many remote faults one vCPU has taken. So far it's still not used, but will be soon. Reviewed-by: Fabiano Rosas Signed-off-by: Peter Xu --- migration/postcopy-ram.c | 5 + 1 file changed, 5 insertions(+) diff --git a/migration/postcopy-ram.c b/migration/postcopy-r

Re: [PATCH] migration/postcopy: Add latency distribution report for blocktime

On Mon, Jun 09, 2025 at 06:36:07PM -0400, Peter Xu wrote: > Add the latency distribution too for blocktime, using order-of-two buckets. > It accounts for all the faults, from either vCPU or non-vCPU threads. With > prior rework, it's very easy to achieve by adding an array to account for > faults

[PATCH v8 14/16] backends/igvm: Handle policy for SEV guests

Adds a handler for the guest policy initialization IGVM section and builds an SEV policy based on this information and the ID block directive if present. The policy is applied using by calling 'set_guest_policy()' on the ConfidentialGuestSupport object. Signed-off-by: Roy Hopkins Acked-by: Michae

[PATCH v8 13/16] backends/igvm: Process initialization sections in IGVM file

The initialization sections in IGVM files contain configuration that should be applied to the guest platform before it is started. This includes guest policy and other information that can affect the security level and the startup measurement of a guest. This commit introduces handling of the init

Re: [PATCH 2/6] MAX78000: ICC Implementation

On Sat, 10 May 2025 at 07:58, wrote: > > This patch implements the Instruction Cache Controller for the MAX78000 SOC > > Signed-off-by: Jackson Donaldson > --- > hw/arm/Kconfig | 1 + > hw/arm/max78000_soc.c | 20 ++-- > hw/misc/Kconfig| 3 ++ > hw/

[PATCH 03/12] libdecnumber: replace FSF postal address with licenses URL

Some of the GPLv2 boiler-plate still contained the obsolete "51 Franklin Street" postal address. Replace it with the canonical GNU licenses URL recommended by the FSF: https://www.gnu.org/licenses/ Signed-off-by: Sean Wei --- libdecnumber/decContext.c | 5 ++--- libdecnumber/decNumber.c

[PATCH 04/12] include/libdecnumber: replace FSF postal address with licenses URL

Some of the GPLv2 boiler-plate still contained the obsolete "51 Franklin Street" postal address. Replace it with the canonical GNU licenses URL recommended by the FSF: https://www.gnu.org/licenses/ Signed-off-by: Sean Wei --- include/libdecnumber/dconfig.h | 5 ++--- include/libdecn

[PATCH v3 09/14] migration/postcopy: Initialize blocktime context only until listen

Before this patch, the blocktime context can be created very early, because postcopy_ram_supported_by_host() <- migrate_caps_check() can happen during migration object init. The trick here is the blocktime context needs system vCPU information, which seems to be possible to change after that point

[PATCH v3 12/14] migration/postcopy: Optimize blocktime fault tracking with hashtable

Currently, the postcopy blocktime feature maintains vCPU fault information using an array (vcpu_addr[]). It has two issues. Issue 1: Performance Concern The old algorithm was almost OK and fast on inserts, except that the lookup is slow and won't scale if there are a

[PATCH v3 13/14] migration/postcopy: blocktime allows track / report non-vCPU faults

When used to report page fault latencies, the blocktime feature can be almost useless when KVM async page fault is enabled, because in most cases such remote fault will kickoff async page faults, then it's not trackable from blocktime layer. After all these recent rewrites to blocktime layer, it's

[PATCH v3 04/14] migration/postcopy: Make all blocktime vars 64bits

I am guessing it was used to be 32bits because of the atomic ops. Now all the atomic ops are gone and we're protected by a mutex instead, it's ok we can switch to 64 bits. Reasons to move over: - Allow further patches to change the unit from ms to us: with postcopy preempt mode, we're really

[PATCH v3 11/14] migration/postcopy: Cleanup the total blocktime accounting

The variable vcpu_total_blocktime isn't easy to follow. In reality, it wants to capture the case where all vCPUs are stopped, and now there will be some vCPUs starts running. The name now starts to conflict with vcpu_blocktime_total[], meanwhile it's actually not necessary to have the variable at

[PATCH v3 08/14] migration/postcopy: Report fault latencies in blocktime

Blocktime so far only cares about the time one vcpu (or the whole system) got blocked. It would be also be helpful if it can also report the latency of page requests, which could be very sensitive during postcopy. Blocktime itself is sometimes not very important, especially when one thinks about

[PATCH v3 03/14] migration/postcopy: Drop all atomic ops in blocktime feature

Now with the mutex protection it's not needed anymore. Reviewed-by: Fabiano Rosas Signed-off-by: Peter Xu --- migration/postcopy-ram.c | 23 ++- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/migration/postcopy-ram.c b/migration/postcopy-ram.c index 32fa06da

[PATCH v8 10/16] docs/system: Add documentation on support for IGVM

IGVM support has been implemented for Confidential Guests that support AMD SEV and AMD SEV-ES. Add some documentation that gives some background on the IGVM format and how to use it to configure a confidential guest. Signed-off-by: Roy Hopkins Reviewed-by: Daniel P. Berrangé Reviewed-by: Stefano

[PATCH v4 7/7] qemu-options.hx: Document the arm-smmuv3 device

Now that arm,virt can have user-creatable smmuv3 devices, document it. Signed-off-by: Shameer Kolothum --- qemu-options.hx | 6 ++ 1 file changed, 6 insertions(+) diff --git a/qemu-options.hx b/qemu-options.hx index 7eb8e02b4b..3edbde45bb 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @

[PATCH v8 09/16] i386/sev: Implement ConfidentialGuestSupport functions for SEV

The ConfidentialGuestSupport object defines a number of virtual functions that are called during processing of IGVM directives to query or configure initial guest state. In order to support processing of IGVM files, these functions need to be implemented by relevant isolation hardware support code

[PATCH v3 02/14] migration/postcopy: Push blocktime start/end into page req mutex

The postcopy blocktime feature was tricky that it used quite some atomic operations over quite a few arrays and vars, without explaining how that would be thread safe. The thread safety here is about concurrency between the fault thread and the fault resolution threads, possible to access the same

[PATCH v8 07/16] target/i386: Allow setting of R_LDTR and R_TR with cpu_x86_load_seg_cache()

The x86 segment registers are identified by the X86Seg enumeration which includes LDTR and TR as well as the normal segment registers. The function 'cpu_x86_load_seg_cache()' uses the enum to determine which segment to set. However, specifying R_LDTR or R_TR results in an out-of-bounds access of th

Re: [PATCH 11/12] target/xtensa: replace FSF postal address with licenses URL

On Fri, Jun 13, 2025 at 9:54 AM Sean Wei wrote: > > Some of the GPLv2 boiler-plate still contained the > obsolete "51 Franklin Street" postal address. > > Replace it with the canonical GNU licenses URL recommended by the FSF: > https://www.gnu.org/licenses/ > > Signed-off-by: Sean Wei > --- > ta

[PATCH v3] hw/misc/aspeed_scu: Handle AST2600 protection key registers correctly

The AST2600 SCU has two protection key registers (0x00 and 0x10) that both need to be unlocked. (Un-)locking 0x00 modifies both protection key registers, while modifying 0x10 only modifies itself. This commit updates the SCU write logic to reject writes unless both protection key registers are unl

[PATCH v8 00/16] Introduce support for IGVM files

Here is v8 of the set of patches to add support for IGVM files to QEMU. This is based on commit d9ce74873a6a5a7c504379857461e4ae64fcf0cd of qemu. The previous version of this patch series [1] has only received a few comments which are now addressed in this new version. Additionally, the series has

[PATCH v8 16/16] sev: Provide sev_features flags from IGVM VMSA to KVM_SEV_INIT2

IGVM files can contain an initial VMSA that should be applied to each vcpu as part of the initial guest state. The sev_features flags are provided as part of the VMSA structure. However, KVM only allows sev_features to be set during initialization and not as the guest is being prepared for launch.

[PATCH 05/12] include/hw: replace FSF postal address with licenses URL

Some of the GPLv2 boiler-plate still contained the obsolete "51 Franklin Street" postal address. Replace it with the canonical GNU licenses URL recommended by the FSF: https://www.gnu.org/licenses/ Signed-off-by: Sean Wei --- include/hw/i2c/aspeed_i2c.h | 3 +-- include/hw/pci/pci_bridge.h

[PATCH 07/12] util/rcu.c: replace FSF postal address with licenses URL

The LGPLv2.1 boiler-plate in util/rcu.c still contained the obsolete "51 Franklin Street" postal address. Replace it with the canonical GNU licenses URL recommended by the FSF: https://www.gnu.org/licenses/ Signed-off-by: Sean Wei --- util/rcu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 dele

[PATCH 08/12] hw: replace FSF postal address with licenses URL

The GPLv2 boiler-plate in vmxnet3.h and vmw_pvscsi.h still contained the obsolete "51 Franklin Street" postal address. Replace it with the canonical GNU licenses URL recommended by the FSF: https://www.gnu.org/licenses/ Signed-off-by: Sean Wei --- hw/net/vmxnet3.h | 4 ++-- hw/scsi/vmw_pvsc

[PATCH 09/12] scripts: replace FSF postal address with licenses URL

The GPLv2 boiler-plate in scripts/device-crash-test still contained the obsolete "51 Franklin Street" postal address. Replace it with the canonical GNU licenses URL recommended by the FSF: https://www.gnu.org/licenses/ Signed-off-by: Sean Wei --- scripts/device-crash-test | 3 +-- 1 file change

[PATCH 10/12] contrib: replace FSF postal address with licenses URL

The LGPLv2.1 boiler-plate in pdb.c file still contained the obsolete "51 Franklin Street" postal address. Replace it with the canonical GNU licenses URL recommended by the FSF: https://www.gnu.org/licenses/ Signed-off-by: Sean Wei --- contrib/elf2dmp/pdb.c | 4 ++-- 1 file changed, 2 insertions

[PATCH 11/12] target/xtensa: replace FSF postal address with licenses URL

Some of the GPLv2 boiler-plate still contained the obsolete "51 Franklin Street" postal address. Replace it with the canonical GNU licenses URL recommended by the FSF: https://www.gnu.org/licenses/ Signed-off-by: Sean Wei --- target/xtensa/core-dc232b/gdb-config.c.inc | 5 ++--- target/xten

[PATCH 12/12] target/i386/emulate: replace FSF postal address with licenses URL

Some of the LGPLv2.1 boiler-plate still contained the obsolete "51 Franklin Street" postal address. Replace it with the canonical GNU licenses URL recommended by the FSF: https://www.gnu.org/licenses/ Signed-off-by: Sean Wei --- target/i386/emulate/x86_emu.c | 4 ++-- target/i386/emulate/x86_

[PATCH v8 15/16] i386/sev: Add implementation of CGS set_guest_policy()

The new cgs_set_guest_policy() function is provided to receive the guest policy flags, SNP ID block and SNP ID authentication from guest configuration such as an IGVM file and apply it to the platform prior to launching the guest. The policy is used to populate values for the existing 'policy', 'i

[PATCH 00/12] Replace FSF postal address with licenses URL

The boiler-plate licence headers in several parts of QEMU still contain the obsolete “51 Franklin Street" contact line. The Free Software Foundation now recommends using the canonical URL: https://www.gnu.org/licenses/ This patch updates those headers. The patches are comment-only; no sourc

[PATCH 01/12] COPYING: replace FSF postal address with licenses URL

The license text in COPYING (GPLv2), COPYING.LIB (LGPLv2.1), and the linux-headers/LICENSES/preferred/GPL-2.0 file are referenced to the obsolete FSF postal address. Replace it with the canonical GNU licenses URL recommended by the FSF: https://www.gnu.org/licenses/ Signed-off-by: Sean Wei ---

[PATCH 02/12] linux-headers: replace FSF postal address with licenses URL

The GPLv2 boiler-plate in asm-arm/kvm.h and asm-powerpc/kvm.h still contained the obsolete "51 Franklin Street" postal address. Replace it with the canonical GNU licenses URL recommended by the FSF: https://www.gnu.org/licenses/ Signed-off-by: Sean Wei --- linux-headers/asm-arm/kvm.h | 4 ++

Re: [PATCH v15 3/4] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl

On Fri, 13 Jun 2025 17:07:24 +0100 Peter Maydell wrote: > On Fri, 13 Jun 2025 at 16:20, Jonathan Cameron > wrote: > > > > On Fri, 13 Jun 2025 13:57:39 +0100 > > Peter Maydell wrote: > > > > > On Thu, 12 Jun 2025 at 14:45, Jonathan Cameron > > > wrote: > > > > > > > > Code based on i386/pc

Re: [PATCH v2 06/20] amd_iommu: Return an error when unable to read PTE from guest memory

On 6/12/25 6:37 AM, Vasant Hegde wrote: Alejandro, On 5/2/2025 7:45 AM, Alejandro Jimenez wrote: Make amdvi_get_pte_entry() return an error value (-1) in cases where the memory read fails, versus the current return of 0 to indicate failure. The reason is that 0 is also a valid PTE value, an

[PATCH v8 08/16] i386/sev: Refactor setting of reset vector and initial CPU state

When an SEV guest is started, the reset vector and state are extracted from metadata that is contained in the firmware volume. In preparation for using IGVM to setup the initial CPU state, the code has been refactored to populate vmcb_save_area for each CPU which is then applied during guest start

[PATCH v4 5/7] hw/arm/virt: Add an SMMU_IO_LEN macro

From: Nicolin Chen This is useful as the subsequent support for new SMMUv3 dev will also use the same. Signed-off-by: Nicolin Chen Reviewed-by: Donald Dutile Reviewed-by: Eric Auger Tested-by: Nathan Chen Signed-off-by: Shameer Kolothum --- hw/arm/virt.c | 8 +--- 1 file changed, 5 ins

[PATCH v4 4/7] hw/arm/virt: Factor out common SMMUV3 dt bindings code

No functional changes intended. This will be useful when we add support for user-creatable smmuv3 device. Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nathan Chen Signed-off-by: Shameer Kolothum --- hw/arm/virt.c | 54 +++ 1 file

[PATCH v4 0/7] hw/arm/virt: Add support for user creatable SMMUv3 device

Hi All, Changes from v3: https://lore.kernel.org/qemu-devel/20250602154110.48392-1-shameerali.kolothum.th...@huawei.com/ Addressed feedback on v3. Thanks to all. Major changes: 1. Based on Igor's suggestion, moved the associated primary-bus is of type TYPE_PCI_HOST_BRIDGE check to smmu-common.

[PATCH v4 2/7] hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build

Introduces a new struct AcpiIortSMMUv3Dev to hold all the information required for SMMUv3 IORT node and use that for populating the node. The current machine wide SMMUv3 is named as legacy SMMUv3 as we will soon add support for user-creatable SMMUv3 devices. These changes will be useful to have co

[PATCH v4 3/7] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices

With the soon to be introduced user-creatable SMMUv3 devices for virt, it is possible to have multiple SMMUv3 devices associated with different PCIe root complexes. Update IORT nodes accordingly. An example IORT Id mappings for a Qemu virt machine with two PCIe Root Complexes each assocaited with

[PATCH v4 6/7] hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation

Allow cold-plug of smmuv3 device to virt if there is no machine wide legacy smmuv3 or a virtio-iommu is specified. Device tree support for new smmuv3 dev is limited to the case where it is associated with the default pcie.0 RC. Tested-by: Nathan Chen Signed-off-by: Shameer Kolothum --- hw/arm/

[PATCH v4 1/7] hw/arm/smmu-common: Check SMMU has PCIe Root Complex association

Although this change does not affect functionality at present, it is required when we add support for user-creatable SMMUv3 devices in future patches. Tested-by: Nathan Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmu-common.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff -

Re: [PATCH v12 6/7] plugins: Add patcher plugin and test

On 6/11/25 4:24 PM, Rowan Hart wrote: From: novafacing This patch adds a plugin that exercises the virtual and hardware memory read-write API functions added in a previous patch. The plugin takes a target and patch byte sequence, and will overwrite any instruction matching the target byte seque

Re: [PATCH v15 3/4] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl

On Fri, 13 Jun 2025 13:57:39 +0100 Peter Maydell wrote: > On Thu, 12 Jun 2025 at 14:45, Jonathan Cameron > wrote: > > > > Code based on i386/pc enablement. The memory layout places space for 16 > > host bridge register regions after the GIC_REDIST2 in the extended memmap. > > The CFMWs are place

Re: [PATCH v12 0/7] Add additional plugin API functions to read and write memory and registers

On 6/11/25 4:24 PM, Rowan Hart wrote: This patch series adds several new API functions focused on enabling use cases around reading and writing guest memory from QEMU plugins. To support these new APIs, some utility functionality around retrieving information about address spaces is added as well

[PATCH] linux-user/arm: Fix return value of SYS_cacheflush

*/ +env->regs[0] = 0; break; case ARM_NR_set_tls: cpu_set_tls(env, env->regs[0]); --- base-commit: d9ce74873a6a5a7c504379857461e4ae64fcf0cd change-id: 20250613-cache-723a77168c8e Best regards,

Re: [PATCH 3/6] MAX78000 UART implementation

On Sat, 10 May 2025 at 07:57, wrote: > > This patch implements UART support for the MAX78000 SOC > > Signed-off-by: Jackson Donaldson > --- > hw/arm/Kconfig | 1 + > hw/arm/max78000_soc.c | 27 +++- > hw/char/Kconfig | 3 + > hw/char/max78000_uart.

Re: [PATCH v15 2/4] hw/cxl: Make the CXL fixed memory windows devices.

On Fri, 13 Jun 2025 at 14:10, Jonathan Cameron wrote: > For these specific devices (the fixed memory windows) there isn't > any state as they are representing fixed configuration of the system. > The state is all in the host bridges and beyond. I'll add > a comment as you suggest. > > Currently CX

Re: [PATCH v12 0/7] Add additional plugin API functions to read and write memory and registers

Pierrick Bouvier writes: > On 6/11/25 4:24 PM, Rowan Hart wrote: >> This patch series adds several new API functions focused on enabling use >> cases around reading and writing guest memory from QEMU plugins. To support >> these new APIs, some utility functionality around retrieving information

Re: [PATCH v15 3/4] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl

On Fri, 13 Jun 2025 at 16:20, Jonathan Cameron wrote: > > On Fri, 13 Jun 2025 13:57:39 +0100 > Peter Maydell wrote: > > > On Thu, 12 Jun 2025 at 14:45, Jonathan Cameron > > wrote: > > > > > > Code based on i386/pc enablement. The memory layout places space for 16 > > > host bridge register regio

[PATCH v8 06/16] sev: Update launch_update_data functions to use Error handling

The class function and implementations for updating launch data return a code in case of error. In some cases an error message is generated and in other cases, just the error return value is used. This small refactor adds an 'Error **errp' parameter to all functions which consistently set an error

[PATCH v8 05/16] i386/pc_sysfw: Ensure sysfw flash configuration does not conflict with IGVM

When using an IGVM file the configuration of the system firmware is defined by IGVM directives contained in the file. In this case the user should not configure any pflash devices. This commit skips initialization of the ROM mode when pflash0 is not set then checks to ensure no pflash devices have

[PATCH v3 04/11] migration/bg-snapshot: Do not check for SKIP in iterator

It's not possible to happen in bg-snapshot case. Reviewed-by: Juraj Marcin Signed-off-by: Peter Xu --- migration/migration.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/migration/migration.c b/migration/migration.c index 4098870bce..e33e39ac74 100644 --- a/migration

Re: [PATCH v2 02/25] hw/arm/virt: Introduce machine state acpi pcihp flags and props

Hi Eric, On 6/13/25 02:05, Eric Auger wrote: Hi Gustavo, On 6/13/25 5:01 AM, Gustavo Romero wrote: Hi Eric, On 6/12/25 09:55, Igor Mammedov wrote: On Wed, 11 Jun 2025 10:50:04 +0200 Eric Auger wrote: Hi Igor, On 6/11/25 10:45 AM, Igor Mammedov wrote: On Wed, 11 Jun 2025 08:53:28 +0200 Er

[PATCH v8 01/16] meson: Add optional dependency on IGVM library

The IGVM library allows Independent Guest Virtual Machine files to be parsed and processed. IGVM files are used to configure guest memory layout, initial processor state and other configuration pertaining to secure virtual machines. This adds the --enable-igvm configure option, enabled by default,

[PATCH v3 1/3] hw/arm: make cpu targeted by arm_load_kernel the primary CPU.

Currently, arm booting processus assumes that the first_cpu is the CPU that will boot: `arm_load_kernel` is powering off all but the `first_cpu`; `do_cpu_reset` is setting the loader address only for this `first_cpu`. For most of the boards, this isn't an issue as the kernel is loaded and booted o

[PATCH v3 0/3] xlnx-zynqmp: add support to boot on RPUs

This series enhances Xilinx ZynqMP support to allow booting on RPUs. It was validated with home-made binaries. FreeRTOS was tested but without success: outputs/IRQ seems broken. AFAICT, FreeRTOS is expecting Xilinx's QEMU thus I didn't investigate further. I'd still like advice on the 3rd patch ("

[PATCH v3 3/3] hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5

From: Frederic Konrad This wires a second GIC for the Cortex-R5, all the IRQs are split when there is an RPU instanciated. Signed-off-by: Clément Chigot --- hw/arm/xlnx-zynqmp.c | 103 +++ include/hw/arm/xlnx-zynqmp.h | 5 ++ 2 files changed, 98 insert

[PATCH v8 02/16] backends/confidential-guest-support: Add functions to support IGVM

In preparation for supporting the processing of IGVM files to configure guests, this adds a set of functions to ConfidentialGuestSupport allowing configuration of secure virtual machines that can be implemented for each supported isolation platform type such as Intel TDX or AMD SEV-SNP. These funct

[PATCH v3 2/3] hw/intc/arm_gic: introduce a first-cpu-index property

From: Frederic Konrad This introduces a first-cpu-index property to the arm-gic, as some SOCs could have two separate GIC (ie: the zynqmp). Signed-off-by: Clément Chigot Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c| 2 +- hw/intc/arm_gic_common.c | 1 + include/hw/

[PATCH 06/12] include/qemu: replace FSF postal address with licenses URL

The LGPLv2.1 boiler-plate in rcu.h and rcu_queue.h still contained the obsolete "51 Franklin Street" postal address. Replace it with the canonical GNU licenses URL recommended by the FSF: https://www.gnu.org/licenses/ Signed-off-by: Sean Wei --- include/qemu/rcu.h | 4 ++-- include/qemu/r

Re: [PATCH v15 4/4] qtest/cxl: Add aarch64 virt test for CXL

On Fri, 13 Jun 2025 13:32:03 +0100 Peter Maydell wrote: > On Thu, 12 Jun 2025 at 14:45, Jonathan Cameron > wrote: > > > > Add a single complex case for aarch64 virt machine. > > Given existing much more comprehensive tests for x86 cover the > > common functionality, a single test should be enoug

Re: [PATCH v15 2/4] hw/cxl: Make the CXL fixed memory windows devices.

On Fri, 13 Jun 2025 17:08:28 +0100 Peter Maydell wrote: > On Fri, 13 Jun 2025 at 14:10, Jonathan Cameron > wrote: > > For these specific devices (the fixed memory windows) there isn't > > any state as they are representing fixed configuration of the system. > > The state is all in the host bridg

Re: [PATCH v15 3/4] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl

On Thu, 12 Jun 2025 at 14:45, Jonathan Cameron wrote: > > Code based on i386/pc enablement. The memory layout places space for 16 > host bridge register regions after the GIC_REDIST2 in the extended memmap. > The CFMWs are placed above the extended memmap. > > Only create the CEDT table if cxl=on

Re: [PATCH] hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions

Peter Maydell writes: > The AN500 application note documents that it configures the Cortex-M7 > CPU to have 16 MPU regions. We weren't doing this in our emulation, > so the CPU had only the default 8 MPU regions. Set the mpu-ns-regions > property to 16 for this board. > > This bug doesn't affect

[PATCH 0/2] rust: prepare for multiple bindgen invocations

This is a preparation for the splitting of qemu-api in multiple crates. While I didn't do that yet, I am doing this part early just in case it comes in handy for the Rust implementation of tracing. Paolo Paolo Bonzini (2): rust: prepare variable definitions for multiple bindgen invocations r

[PATCH 1/2] rust: prepare variable definitions for multiple bindgen invocations

When splitting the QEMU Rust bindings into multiple crates, the bindgen-generated structs also have to be split so that it's possible to add "impl" blocks (e.g. for Sync/Send or Default, or even for utility methods in cases such as VMStateFlags). Tweak various variable definitions in meson.build,

Re: [PATCH v15 2/4] hw/cxl: Make the CXL fixed memory windows devices.

On Fri, 13 Jun 2025 13:33:51 +0100 Peter Maydell wrote: > On Thu, 12 Jun 2025 at 14:44, Jonathan Cameron > wrote: > > > > Previously these somewhat device like structures were tracked using a list > > in the CXLState in each machine. This is proving restrictive in a few > > cases where we need t

[PATCH 2/2] rust: move rust.bindgen to qemu-api crate

Once qemu-api is split in multiple crates, each of which will have its own invocation of bindgen. There cannot be only one, because there are occasional "impl" blocks for the bindgen-generated structs (e.g. VMStateFlags or QOM classes) that have to reside in the same crate as the bindgen-generated

[PATCH v3 01/11] migration/hmp: Reorg "info migrate" once more

Dave suggested the HMP output for "info migrate" can not only leverage the lines but also better grouping: https://lore.kernel.org/r/aC4_-nMc7FwsMf9p@gallifrey I followed Dave's suggestion, and some more modifications on top: - Added all elements into the picture - Use size_to_str() and d

[PATCH v3 09/11] migration/ram: Add tracepoints for ram_save_complete()

Take notes on start/end state of dirty pages for the whole system. Reviewed-by: Juraj Marcin Signed-off-by: Peter Xu --- migration/ram.c| 5 + migration/trace-events | 1 + 2 files changed, 6 insertions(+) diff --git a/migration/ram.c b/migration/ram.c index c66ad3cf8b..a1d0e8ada2

[PATCH v3 03/11] migration/docs: Move docs for postcopy blocktime feature

Move it out of vanilla postcopy session, but instead a standalone feature. When at it, removing the NOTE because it's incorrect now after introduction of max-postcopy-bandwidth, which can control the throughput even for postcopy phase. Reviewed-by: Juraj Marcin Signed-off-by: Peter Xu --- docs/

[PATCH v8 11/16] docs/interop/firmware.json: Add igvm to FirmwareDevice

Create an enum entry within FirmwareDevice for 'igvm' to describe that an IGVM file can be used to map firmware into memory as an alternative to pre-existing firmware devices. Signed-off-by: Roy Hopkins Acked-by: Michael S. Tsirkin Acked-by: Gerd Hoffman Reviewed-by: Stefano Garzarella --- do

[PATCH v8 12/16] backends/confidential-guest-support: Add set_guest_policy() function

For confidential guests a policy can be provided that defines the security level, debug status, expected launch measurement and other parameters that define the configuration of the confidential platform. This commit adds a new function named set_guest_policy() that can be implemented by each conf

Re: [PATCH v2 0/4] xlnx-zynqmp: add support to boot on RPUs

On Fri, Jun 13, 2025 at 1:58 PM Peter Maydell wrote: > > On Mon, 26 May 2025 at 09:55, Clément Chigot wrote: > > > > This series enhances Xilinx ZynqMP support to allow booting on RPUs and > > ease gdb connections to them. > > > > It was validated with home-made binaries. FreeRTOS was tested but

[PATCH v3 02/11] migration/hmp: Fix postcopy-blocktime per-vCPU results

Unfortunately, it was never correctly shown.. This is only found when I started to look into making the blocktime feature more useful (so as to avoid using bpftrace, even though I'm not sure which one will be harder to use..). So the old dump would look like this: Postcopy vCPU Blocktime: 0-1,

[PATCH v3 07/11] migration: qemu_savevm_complete*() helpers

Since we use the same save_complete() hook for both precopy and postcopy, add a set of helpers to invoke the hook() to dedup the code. Signed-off-by: Peter Xu --- migration/savevm.c | 78 ++ 1 file changed, 44 insertions(+), 34 deletions(-) diff --git

[PATCH v3 08/11] migration/ram: One less indent for ram_find_and_save_block()

The check over PAGE_DIRTY_FOUND isn't necessary. We could indent one less and assert that instead. Reviewed-by: Juraj Marcin Signed-off-by: Peter Xu --- migration/ram.c | 20 +++- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/migration/ram.c b/migration/ram.c in

[PATCH v3 05/11] migration: Drop save_live_complete_postcopy hook

The hook is only defined in two vmstate users ("ram" and "block dirty bitmap"), meanwhile both of them define the hook exactly the same as the precopy version. Hence, this postcopy version isn't needed. No functional change intended. Signed-off-by: Peter Xu --- include/migration/register.h |

[PATCH v3 06/11] migration: Rename save_live_complete_precopy to save_complete

Now after merging the precopy and postcopy version of complete() hook, rename the precopy version from save_live_complete_precopy() to save_complete(). Dropping the "live" when at it, because it's in most cases not live when happening (in precopy). No functional change intended. Signed-off-by: P

[PATCH v3 01/14] migration: Add option to set postcopy-blocktime

Add a global property to allow enabling postcopy-blocktime feature. Reviewed-by: Fabiano Rosas Signed-off-by: Peter Xu --- migration/options.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/migration/options.c b/migration/options.c index 162c72cda4..4e923a2e07 100644 --- a/migration/opti

Re: [PATCH v2 01/12] python: convert packages to PEP517/pyproject.toml

On Fri, Jun 13, 2025 at 4:36 AM Thomas Huth wrote: > On 12/06/2025 22.54, John Snow wrote: > > Newer versions of setuptools increasingly expect that packages are > > defined using the pyproject.toml/PEP517 packaging layout format. With > > 3.9 as our minimum, I believe it's finally appropriate to

[PATCH 0/2] virtio-9p: move G_GNUC_PRINTF to header

v9fs_string_sprintf() and v9fs_path_sprintf() already have G_GNUC_PRINTF annotations in their own *.c files, but the prototypes in the corresponding headers lack them. When another translation unit includes only the header, -Wformat can no longer validate the argument list. This series relocates

[PATCH 1/2] fsdev/9p-marshal: move G_GNUC_PRINTF to header

v9fs_string_sprintf() is annotated with G_GNUC_PRINTF(2, 3) in 9p-marshal.c, but the prototype in fsdev/9p-marshal.h is missing the attribute, so callers that include only the header do not get format checking. Move the annotation to the header and delete the duplicate in the source file. No behav

[PATCH 2/2] hw/9pfs: move G_GNUC_PRINTF to header

v9fs_path_sprintf() is annotated with G_GNUC_PRINTF(2, 3) in hw/9pfs/9p.c, but the prototype in hw/9pfs/9p.h is missing the attribute, so callers that include only the header do not get format checking. Move the annotation to the header and delete the duplicate in the source file. No behavior chan

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