On Thu, Mar 27, 2025 at 7:42 PM Sahil Siddiq wrote:
>
> Hi,
>
> On 3/26/25 1:33 PM, Eugenio Perez Martin wrote:
> > On Mon, Mar 24, 2025 at 3:14 PM Sahil Siddiq wrote:
> >> On 3/24/25 7:29 PM, Sahil Siddiq wrote:
> >>> Implement the insertion of available buffers in the descriptor area of
> >>> p
On Fri, Mar 28, 2025 at 6:22 AM Sahil Siddiq wrote:
>
> Hi,
>
> On 3/26/25 2:04 PM, Eugenio Perez Martin wrote:
> > On Mon, Mar 24, 2025 at 3:34 PM Sahil Siddiq wrote:
> >>
> >> Hi,
> >>
> >> I had a few more queries here as well.
> >>
> >> On 3/24/25 7:29 PM, Sahil Siddiq wrote:
> >>> Detect whe
On Fri, Mar 28, 2025 at 6:34 AM Sahil Siddiq wrote:
>
> Hi,
>
> On 3/26/25 5:36 PM, Eugenio Perez Martin wrote:
> > On Mon, Mar 24, 2025 at 3:00 PM Sahil Siddiq wrote:
> >>
> >> Validate transport device features required for utilizing packed SVQ
> >> that both guests can use with the SVQ and SVQ
On Thu, Mar 20 2025, Sebastian Ott wrote:
> On Tue, 11 Mar 2025, Cornelia Huck wrote:
>> +++ b/target/arm/cpu.h
> [...]
>> +/* REG is ID_XXX */
>> +#define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \
>> +({
John Snow writes:
> Well, I tried. Maybe not very hard. Sorry!
No need to be sorry! Kick-starting discussion with limited effort is
better than a big effort going into a direction that turns out to be
unwanted once we discuss it.
Instead of just rephrasing Returns descriptions, I'd like us to
On 28/03/25 13:29, Cédric Le Goater wrote:
On 3/27/25 21:07, Aditya Gupta wrote:
<...snip...>
Reviewed-by: Cédric Le Goater
Thanks for the tag, and all your reviews and the help in fixes, Cédric !
- Aditya G
Thanks,
C.
On 25/03/28 09:02AM, Cédric Le Goater wrote:
> On 3/27/25 21:07, Aditya Gupta wrote:
> > <...snip...>
>
> In OPAL, the Power11 "CPU: PXYZ generation processor" string seems
> inconsistent with the previous generations :
Yes, that was intentional due to how we wanted to export it as "Power11"
Quo
On 3/25/25 02:22, Philippe Mathieu-Daudé wrote:
On 24/3/25 21:49, Pierrick Bouvier wrote:
On 3/24/25 13:04, Richard Henderson wrote:
On 3/24/25 12:29, Pierrick Bouvier wrote:
On 3/24/25 10:39, Richard Henderson wrote:
On 3/24/25 03:21, Alex Bennée wrote:
+ #ifdef TARGET_BIG_ENDIAN
+ Me
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
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Not used by tb-internal.h, but add an include for
target_page.h in tb-maint.c.
Signed-off-by: Richard Henderson
---
accel/tcg/tb-internal.h | 2 --
accel/tcg/tb-maint.c| 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h
index
Pierrick Bouvier writes:
> This test was randomly failing on our CI, and on dev machines,
> especially with QEMU debug builds.
>
> From the information collected, it's related to an implementation choice
> in edk2 QEMU virt support. The workaround is to disable KASLR, to avoid
> accessing protect
On 3/28/25 13:04, Richard Henderson wrote:
With this, TARGET_PAGE_BITS_MIN no longer exists outside of
page-vary-target.c, as that's the only place that needs the
information.
Based-on: 20250318213209.2579218-1-richard.hender...@linaro.org
("[PATCH v2 00/42] accel/tcg, codebase: Build once patch
On 3/28/25 15:38, Pierrick Bouvier wrote:
Any chance we would rename TARGET_PAGE_BITS__MIN? (MIN_ALL? ALL_MIN? ARCH_MIN? any other
idea)
I know it's restricted to this file only, but the __ is surprising.
I could drop the poisoning. Since there have only ever been two targets using
TARGET_PA
Starting with z15 (or newer) we can execute mmio
instructions from userspace. On older platforms
where we don't have these instructions available
we can fallback to using system calls to access
the PCI mapped resources.
This patch adds helper functions for mmio reads
and writes for s390x.
Reviewe
Move the declarations from exec/exec-all.h to the
private accel/tcg/internal-common.h.
Signed-off-by: Richard Henderson
---
accel/tcg/internal-common.h | 34 ++
include/exec/exec-all.h | 34 --
accel/tcg/translator.c | 1 +
Move the accessor functions for TranslationBlock
into the header related to the structure.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 49 ---
include/exec/translation-block.h | 50
2 files changed, 50 inser
The only place we really need to know the minimum is within
page-vary-target.c. Rename the target/arm TARGET_PAGE_BITS_MIN
to TARGE_PAGE_BITS_LEGACY to emphasize what it really means.
Move the assertions related to minimum page size as well.
Signed-off-by: Richard Henderson
---
include/exec/cpu
On 28/03/2025 15.16, BALATON Zoltan wrote:
On Fri, 28 Mar 2025, Paolo Bonzini wrote:
On 3/27/25 21:50, BALATON Zoltan wrote:
On Thu, 27 Mar 2025, rakeshj wrote:
The GT-64120 PCI controller requires special handling where:
1. Host bridge (device 0) must use native endianness
2. Other devices fo
Don't base the values on TARGET_PAGE_BITS_MIN, but do verify
that TLB_FLAGS_MASK does not overlap minimum page size.
Signed-off-by: Richard Henderson
---
include/exec/tlb-flags.h | 68 +++-
accel/tcg/cputlb.c | 2 ++
2 files changed, 34 insertions(+), 3
The CPU_TLB_DYN_{MIN,MAX}_BITS definitions are not required
outside of cputlb.c and translate-all.c.
Signed-off-by: Richard Henderson
---
accel/tcg/tb-internal.h | 27 ---
accel/tcg/tlb-bounds.h| 32
accel/tcg/cputlb.c| 1 +
On 28/3/25 21:04, Richard Henderson wrote:
Drop some unnecessary includes. Change the offsetof expressions
to be based on CPUState instead of ArchCPU.
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c | 14 ++
accel/tcg/meson.build | 2 +-
2 files changed, 7 inserti
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
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Rename to migration_legacy_page_bits, to make it clear that
we cannot change the value without causing a migration break.
Move to page-vary.h and page-vary-target.c.
Define via TARGET_PAGE_BITS if not TARGET_PAGE_BITS_VARY.
Signed-off-by: Richard Henderson
---
include/exec/page-vary.h | 9
On 3/28/25 13:04, Richard Henderson wrote:
Merge the user-only page_protect function with the user-only
implementation of tb_lock_page0. This avoids pulling
page-protection.h into tb-internal.h.
Signed-off-by: Richard Henderson
---
accel/tcg/tb-internal.h| 11 +++
include/us
On 3/28/25 13:04, Richard Henderson wrote:
Not used by tb-internal.h, but add an include for
target_page.h in tb-maint.c.
Signed-off-by: Richard Henderson
---
accel/tcg/tb-internal.h | 2 --
accel/tcg/tb-maint.c| 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/accel/t
On 3/28/25 13:04, Richard Henderson wrote:
Don't base the values on TARGET_PAGE_BITS_MIN, but do verify
that TLB_FLAGS_MASK does not overlap minimum page size.
Signed-off-by: Richard Henderson
---
include/exec/tlb-flags.h | 68 +++-
accel/tcg/cputlb.c
On 3/28/25 13:04, Richard Henderson wrote:
Move the accessor functions for TranslationBlock
into the header related to the structure.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 49 ---
include/exec/translation-block.h | 50
On 3/28/25 13:04, Richard Henderson wrote:
Move the declarations from exec/exec-all.h to the
private accel/tcg/internal-common.h.
Signed-off-by: Richard Henderson
---
accel/tcg/internal-common.h | 34 ++
include/exec/exec-all.h | 34 ---
On 3/28/25 13:04, Richard Henderson wrote:
Drop some unnecessary includes. Change the offsetof expressions
to be based on CPUState instead of ArchCPU.
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c | 14 ++
accel/tcg/meson.build | 2 +-
2 files changed, 7 inserti
On 3/28/25 13:04, Richard Henderson wrote:
Rename to migration_legacy_page_bits, to make it clear that
we cannot change the value without causing a migration break.
Move to page-vary.h and page-vary-target.c.
Define via TARGET_PAGE_BITS if not TARGET_PAGE_BITS_VARY.
Signed-off-by: Richard Hender
On 3/28/25 13:04, Richard Henderson wrote:
The only place we really need to know the minimum is within
page-vary-target.c. Rename the target/arm TARGET_PAGE_BITS_MIN
to TARGE_PAGE_BITS_LEGACY to emphasize what it really means.
Move the assertions related to minimum page size as well.
s/TARGE_
On 19/03/2025 14:21, Joao Martins wrote:
External email: Use caution opening links or attachments
On 18/03/2025 09:54, Cédric Le Goater wrote:
Rename these routines :
vfio_devices_all_device_dirty_tracking_started ->
vfio_dirty_tracking_devices_is_started_all
vfio_devices_all_dirty_t
On 3/24/2025 2:40 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Saturday, March 1, 2025 11:21 AM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@re
This test was randomly failing on our CI, and on dev machines,
especially with QEMU debug builds.
>From the information collected, it's related to an implementation choice
in edk2 QEMU virt support. The workaround is to disable KASLR, to avoid
accessing protected memory.
Note: this is *not* needed
The number of bits set in PageMask must be even.
Fixes: d40b55bc1b86 ("target/mips: Fix PageMask with variable page size")
Signed-off-by: Richard Henderson
---
target/mips/tcg/system/cp0_helper.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/target/
Use the QEMU PCI MMIO functions to read/write
to NVMe registers, rather than directly accessing
them.
Signed-off-by: Farhan Ali
---
block/nvme.c | 37 +
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/block/nvme.c b/block/nvme.c
index bbf7c23dc
Hi,
Recently on s390x we have enabled mmap support for vfio-pci devices [1].
This allows us to take advantage and use userspace drivers on s390x. However,
on s390x we have special instructions for MMIO access. Starting with z15
(and newer platforms) we have new PCI Memory I/O (MIO) instructions w
On 3/28/25 13:38, Pierrick Bouvier wrote:
This test was randomly failing on our CI, and on dev machines,
especially with QEMU debug builds.
From the information collected, it's related to an implementation choice
in edk2 QEMU virt support. The workaround is to disable KASLR, to avoid
accessing
On 28/3/25 20:06, Farhan Ali wrote:
Use the QEMU PCI MMIO functions to read/write
to NVMe registers, rather than directly accessing
them.
Signed-off-by: Farhan Ali
---
block/nvme.c | 37 +
1 file changed, 21 insertions(+), 16 deletions(-)
@@ -805,16 +8
A page state change is typically followed by an access of the page(s) and
results in another VMEXIT in order to map the page into the nested page
table. Depending on the size of page state change request, this can
generate a number of additional VMEXITs. For example, under SNP, when
Linux is utiliz
On 28/3/25 20:06, Farhan Ali wrote:
Add a generic QEMU API for PCI MMIO reads/writes.
The functions access little endian memory and returns
the result in host cpu endianness.
Signed-off-by: Farhan Ali
---
include/qemu/pci-mmio.h | 116
1 file changed,
On 28/3/25 20:06, Farhan Ali wrote:
Add a generic QEMU API for PCI MMIO reads/writes.
The functions access little endian memory and returns
the result in host cpu endianness.
Signed-off-by: Farhan Ali
---
include/qemu/pci-mmio.h | 116
1 file changed,
When update_pagemask was split from helper_mtc0_pagemask,
we failed to actually write to the new parameter but continue
to write to env->CP0_PageMask. Thus the use within
page_table_walk_refill modifies cpu state and not the local
variable as expected.
Simplify by renaming to compute_pagemask and
Revert ee3863b9d41 and a08d60bc6c2b. The logic behind changing
the system page size because of what the Loongson kernel "prefers"
is flawed.
In the Loongson-2E manual, section 5.5, it is clear that the cpu
supports a 4k page size (along with many others). Therefore we
must continue to support a
The logic behind changing the system page size because of what the
Loongson kernel "prefers" is flawed.
In the Loongson-2E manual, section 5.5, it is clear that the cpu
supports a 4k page size (along with many others). Therefore we
must continue to support a 4k page size.
While in the area, I no
On 28/3/25 10:49, Zheng Huang wrote:
Hi,
This patch fixes a memory leak bug in `sdhci_pci_realize()`. `s->irq` is
not freed in `sdhci_pci_exit()`.
Signed-off-by: Zheng Huang
---
hw/sd/sdhci-pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/sd/sdhci-pci.c b/hw/sd/sdhci-pci.c
in
On Thu, 2025-03-27 at 21:13 +0100, Thomas Huth wrote:
> From: Thomas Huth
>
> Yes, we are all C coders who try to write Python code for testing...
> but still, let's better avoid semicolons at the end of the lines
> to keep "pylint" happy!
>
> Signed-off-by: Thomas Huth
Reviewed-by: Nina Schoe
26.03.2025 19:22, Marco Cavenati wrote:
The SEEK_CUR case in qio_channel_block_seek was incorrectly using the
'whence' parameter instead of the 'offset' parameter when calculating the
new position.
Fixes: 65cf200a51ddc6d0a28ecceac30dc892233cddd7 ("migration: introduce a QIOChannel
impl for Bloc
On 3/28/2025 1:38 PM, Philippe Mathieu-Daudé wrote:
On 28/3/25 20:06, Farhan Ali wrote:
Add a generic QEMU API for PCI MMIO reads/writes.
The functions access little endian memory and returns
the result in host cpu endianness.
Signed-off-by: Farhan Ali
---
include/qemu/pci-mmio.h | 116 +++
On 3/28/2025 1:44 PM, Philippe Mathieu-Daudé wrote:
On 28/3/25 20:06, Farhan Ali wrote:
Add a generic QEMU API for PCI MMIO reads/writes.
The functions access little endian memory and returns
the result in host cpu endianness.
Signed-off-by: Farhan Ali
---
include/qemu/pci-mmio.h | 116 +++
On 3/28/2025 1:41 PM, Philippe Mathieu-Daudé wrote:
On 28/3/25 20:06, Farhan Ali wrote:
Use the QEMU PCI MMIO functions to read/write
to NVMe registers, rather than directly accessing
them.
Signed-off-by: Farhan Ali
---
block/nvme.c | 37 +
1 file chang
10.03.2025 05:35, Chao Liu wrote:
Recently, when I was writing a RISCV test, I found that when VL is set to 0, the
instruction should be nop, but when I tested it, I found that QEMU will treat
all elements as tail elements, and in the case of VTA=1, write all elements
to 1.
After troubleshooting
On 3/18/25 11:13, Pierrick Bouvier wrote:
On 3/18/25 11:06, Peter Maydell wrote:
On Tue, 18 Mar 2025 at 17:52, Pierrick Bouvier
wrote:
On 3/18/25 10:50, Peter Maydell wrote:
On Tue, 18 Mar 2025 at 17:42, Philippe Mathieu-Daudé wrote:
On 18/3/25 05:51, Pierrick Bouvier wrote:
Directly con
On Fri, 28 Mar 2025, Paolo Bonzini wrote:
On 3/27/25 21:50, BALATON Zoltan wrote:
On Thu, 27 Mar 2025, rakeshj wrote:
The GT-64120 PCI controller requires special handling where:
1. Host bridge (device 0) must use native endianness
2. Other devices follow MByteSwap bit in GT_PCI0_CMD
Previous
On 27/3/25 21:13, Thomas Huth wrote:
From: Thomas Huth
Yes, we are all C coders who try to write Python code for testing...
but still, let's better avoid semicolons at the end of the lines
to keep "pylint" happy!
:)
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
tes
On 28/3/25 04:21, Zheng Huang wrote:
Hi,
This patch addresses a memory leak bug in the usages of `timer_del()`.
The issue arisesfrom the incorrect use of the ambiguous timer API
`timer_del()`, which does not free the timer object. The LeakSanitizer
report this issue during fuzzing. The correct AP
From: Troy Lee
Commit 6de4aa8dc544 ("hw/arm/aspeed_ast27x0: Add SoC Support for AST2700
A1") extends ast2700a1 spis_num to 3, but ASPEED_SPIS_NUM defines the
maximum number of spi controller to 2, result in ehci[0] is being
overwritten in runtime.
Signed-off-by: Troy Lee
Fixes: 6de4aa8dc544 ("h
On 28/3/25 21:04, Richard Henderson wrote:
The CPU_TLB_DYN_{MIN,MAX}_BITS definitions are not required
outside of cputlb.c and translate-all.c.
Signed-off-by: Richard Henderson
---
accel/tcg/tb-internal.h | 27 ---
accel/tcg/tlb-bounds.h| 32
Drop some unnecessary includes. Change the offsetof expressions
to be based on CPUState instead of ArchCPU.
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c | 14 ++
accel/tcg/meson.build | 2 +-
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/accel/tcg/t
Merge the user-only page_protect function with the user-only
implementation of tb_lock_page0. This avoids pulling
page-protection.h into tb-internal.h.
Signed-off-by: Richard Henderson
---
accel/tcg/tb-internal.h| 11 +++
include/user/page-protection.h | 1 -
accel/tcg/user-exe
Hi,
This patch fixes a memory leak bug in `sdhci_pci_realize()`. `s->irq` is
not freed in `sdhci_pci_exit()`.
Signed-off-by: Zheng Huang
---
hw/sd/sdhci-pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/sd/sdhci-pci.c b/hw/sd/sdhci-pci.c
index 5268c0dee5..f5296d58ca 100644
--- a/h
On 3/27/25 21:07, Aditya Gupta wrote:
Introduce Power11 ChipTod. The code has been copied from Power10 ChipTod
code as the Power11 core is same as Power10 core.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya
On Fri, 21 Mar, 2025, 3:38 pm Gerd Hoffman, wrote:
> Hi,
>
> > > While digging around in the igvm spec I've seen there is the
> > > concept of 'parameters'. Can this be used to pass on the memory
> > > location of kernel + initrd + cmdline? Maybe the kernel hashes
> too?
> >
>
On 3/27/25 21:07, Aditya Gupta wrote:
Overview
Add support for Power11 powernv machine type.
As Power11 core is same as Power10, hence much of the code has been reused
from Power10.
Split Powernv11 chip/machine code into commits introducing:
chip,machine,xive,phb
This is to try t
On 3/27/25 21:07, Aditya Gupta wrote:
As op-build images haven't been updated from long time (and may not get
updated in future), use buildroot images provided by cedric [1].
Use existing nvme device being used in the test to mount the initrd.
Also replace the check for "zImage loaded message"
On 3/28/25 05:06, Aditya Gupta wrote:
Power8E and Power8NVL variants are not of much use in QEMU now, and not
being maintained either.
Deprecate the 8E and 8NVL variants.
After deprecation, QEMU will print a warning like below when the
CPU/Chips are used:
$ ./build/qemu-system-ppc64 -M po
On 3/27/25 21:13, Thomas Huth wrote:
From: Thomas Huth
Yes, we are all C coders who try to write Python code for testing...
nah, we just anticipated rust functional tests :)
but still, let's better avoid semicolons at the end of the lines
to keep "pylint" happy!
Signed-off-by: Thomas Huth
On 3/27/25 21:07, Aditya Gupta wrote:
With all Power11 support in place, add Power11 PowerNV test.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
tests/functional/test_ppc64_powernv.py | 4
Hi,
This patch fixes assertion error `vector < dev->msix_entries_nr` while
hot-unplugging rocker device. In `rocker_msix_uninit()`, `msix_uninit()`
will clear the field `msix_entries_nr` and free the `msix_entry_used`,
which are used later in `rocker_msix_vectors_unuse()` for msix clearing.
Swapp
On 3/27/25 21:50, BALATON Zoltan wrote:
On Thu, 27 Mar 2025, rakeshj wrote:
The GT-64120 PCI controller requires special handling where:
1. Host bridge (device 0) must use native endianness
2. Other devices follow MByteSwap bit in GT_PCI0_CMD
Previous implementation accidentally swapped all acc
This patch fixes a misconfiguration issue in the read implementation of
the AUX_MU_IIR_REG register. This issue can lead to a transmit interrupt
being incorrectly interpreted as a receive interrupt when the receive
interrupt is disabled and the receive FIFO holds valid bytes.
The AUX_MU_IIR_REG re
On Fri, Mar 28, 2025 at 3:16 PM BALATON Zoltan wrote:
> > It should be fine. You should take into account:
> >
> > - the endianness produced by pci_data_read/pci_data_write (always little
> > endian)
> >
> > - the endianness expected by the guest (big endian under the conditions in
> > the patch)
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