We have some users of the PL011 struct which embed it directly into
their own state structs. This means that the Rust version of the
device must have a state struct that is the same size or smaller
than the C struct.
In commit 9b642097d6b7 ("rust: pl011: switch to safe chardev operation")
the Rust
Hi everyone,
The QEMU v9.2.3 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
https://download.qemu.org/qemu-9.2.3.tar.xz
https://download.qemu.org/qemu-9.2.3.tar.xz.sig (signature)
v9.2.3 is now tagged in the o
Hi everyone,
The QEMU v8.2.10 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
https://download.qemu.org/qemu-8.2.10.tar.xz
https://download.qemu.org/qemu-8.2.10.tar.xz.sig (signature)
v8.2.10 is now tagged in t
Hi everyone,
The QEMU v7.2.17 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
https://download.qemu.org/qemu-7.2.17.tar.xz
https://download.qemu.org/qemu-7.2.17.tar.xz.sig (signature)
v7.2.17 is now tagged in t
This patch adds the new VM state change cb type `VMChangeStateHandlerWithRet`,
which has return value for `VMChangeStateEntry`.
Thus, we can register a new VM state change cb with return value for device.
Note that `VMChangeStateHandler` and `VMChangeStateHandlerWithRet` are mutually
exclusive and
> 2025年3月25日 17:51，Stefano Garzarella 写道：
>
> On Tue, Mar 25, 2025 at 04:39:46PM +0800, Haoqian He wrote:
>>> 2025年3月24日 22:31，Stefano Garzarella 写道：
>>> On Thu, Mar 20, 2025 at 08:21:30PM +0800, Haoqian He wrote:
> 2025年3月19日 23:20，Stefano Garzarella 写道：
> On Fri, Mar 14, 2025 at 06:
From: Qiang Yu
mesa/radeonsi is going to support explicit modifier which
may export a multi-plane texture. For example, texture with
DCC enabled (a compressed format) has two planes, one with
compressed data, the other with meta data for compression.
v2:
* change API qemu_dmabuf_get_fd/offset/
From: Qiang Yu
We need spice version >= 0.15.3 which has spice_qxl_gl_scanout2
API for multi plane scanout support.
v2:
* use new dmabuf API and check length
* check spice_qxl_gl_scanout2 present instead of
bump spice version dependency
Signed-off-by: Qiang Yu
---
meson.build|
From: Qiang Yu
mesa/radeonsi is going to support explicit modifier with this MR:
* https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658
The side effect is some texture will become multi-plane which
breaks qemu. Because qemu currently only support single plane
texture.
For example,
From: Qiang Yu
It's used already, just check it explicitly.
Reviewed-by: Marc-André Lureau
Signed-off-by: Qiang Yu
---
ui/egl-helpers.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/ui/egl-helpers.c b/ui/egl-helpers.c
index d194d004b7..432863d702 100644
--- a/
>-Original Message-
>From: Cédric Le Goater
>Subject: [PATCH for-10.1 13/32] vfio: Move VFIOAddressSpace helpers into
>container-base.c
>
>VFIOAddressSpace is a common object used by VFIOContainerBase which is
>declared in "hw/vfio/vfio-container-base.h". Move the VFIOAddressSpace
>relat
John Snow writes:
> On Wed, Mar 26, 2025 at 2:08 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > A few transitive dependencies were left floating; as a result, pip's
>> > dependency solver can pull in newer dependencies, which we don't
>> > want. Pin them down.
>> >
>> > Signed-off-b
Signed-off-by: Paolo Bonzini
---
include/hw/qdev-properties.h | 1 +
hw/core/qdev-properties.c | 37 ++
rust/hw/timer/hpet/src/hpet.rs | 6 +++---
3 files changed, 41 insertions(+), 3 deletions(-)
diff --git a/include/hw/qdev-properties.h b/include/hw/qde
On 11/03/2025 17.00, Kevin Wolf wrote:
From: Stefan Hajnoczi
Allow virtio-scsi virtqueues to be assigned to different IOThreads. This
makes it possible to take advantage of host multi-queue block layer
scalability by assigning virtqueues that have affinity with vCPUs to
different IOThreads that
On 26/03/2025 10.43, Daniel P. Berrangé wrote:
On Tue, Mar 25, 2025 at 09:00:19PM +0100, Thomas Huth wrote:
From: Thomas Huth
This way we can do a full boot in record-replay mode and
should get a similar test coverage compared to the old
replay test from tests/avocado/replay_linux.py. Thus rem
zoudongjie via writes:
> From: Zhu Yangyang
>
> Calling qmp_block_set_io_throttle() will be blocked for a long time
> when a network disk is configured and the network failure is just about
> to occur.
>
> Therefore, we add a timeout parameter for qmp_block_set_io_throttle to control
> its execu
On Wed, Mar 26, 2025 at 2:47 PM Michael Galaxy wrote:
>
> Excellent find. Thank you very much for checking on the history. Hopefully my
> comments were not too hard to read. =)
Yeah, it's pretty clear.
>
> FYI: I've since left Akamai last year and now work at Nvidia.
>
> Reviewed-by: Michael Gala
On 26/03/2025 13.39, BALATON Zoltan wrote:
On Wed, 26 Mar 2025, Thomas Huth wrote:
On 26/03/2025 07.47, Thomas Huth wrote:
On 25/03/2025 23.42, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/audio/wm8750.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw
On 26.03.25 12:41, Markus Armbruster wrote:
Hanna Czenczek writes:
On 26.03.25 06:38, Markus Armbruster wrote:
Hanna Czenczek writes:
FUSE allows creating multiple request queues by "cloning" /dev/fuse FDs
(via open("/dev/fuse") + ioctl(FUSE_DEV_IOC_CLONE)).
We can use this to implement m
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Inroduce an SMMUCommandBatch and some helpers to batch and issue the
> commands. Currently separate out TLBI commands and device cache commands
> to avoid some errata on certain versions of SMMUs. Later it should check
> IIDR
On Mon, 2025-03-10 at 16:14 +0100, Philippe Mathieu-Daudé wrote:
> In preparation to make @dump-skeys command generic,
> extract s390_qmp_dump_skeys() out of qmp_dump_skeys().
> Register it as CCW qmp_dump_skeys() callback.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/s390x/stora
Hello Marc-André and all,
I am trying to debug an issue where I am unable to get copy-paste to work with
libvirt, qemu and VNC (no spice).
The qemu command line that results from the libvirt vdagent and vnc
configuration contains:
-chardev socket,id=charchannel0,fd=52,server=on,wait=off \
-dev
From: Thomas Huth
This reverts commit e2668ba1ed44ad56f2f1653ff5f53b277d534fac.
This commit made test 162 fail occasionally with:
162 fail [13:06:40] [13:06:40] 0.2s (last: 0.2s) output mismatch
--- tests/qemu-iotests/162.out
+++ tests/qemu-iotests/scratch/qcow2-file-162/162.out.
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Read the underlying SMMUv3 device info and set corresponding IDR
> bits. We need at least one cold-plugged vfio-pci dev associated
> with the smmuv3-accel instance to do this now. Hence fail if it
> is not available.
>
> ToDo
On 3/25/25 15:44, Richard Henderson wrote:
If i/o does not cover the entire first page, allocate a portion
of ram as an i/o device, so that the entire first page is i/o.
While memory_region_init_ram_device_ptr is happy to allocate
the RAMBlock, it does not register the ram for migration.
Do this
On 3/25/25 08:40, Philippe Mathieu-Daudé wrote:
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
In few commits we are going to add more types, so replace
th
On 3/26/25 15:38, Steven Sistare wrote:
On 3/26/2025 3:51 AM, Cédric Le Goater wrote:
Gather all CPR related declarations into "vfio-cpr.h" to reduce exposure
of VFIO internals in "hw/vfio/vfio-common.h". These were introduced in
commit d9fa4223b30a ("vfio: register container for cpr").
Order f
Hi,
Recently on s390x we have enabled mmap support for vfio-pci devices [1].
This allows us to take advantage and use userspace drivers on s390x. However,
on s390x we have special instructions for MMIO access. Starting with z15
(and newer platforms) we have new PCI Memory I/O (MIO) instructions w
On 3/25/25 10:40, Philippe Mathieu-Daudé wrote:
mips_cpu_is_64bit() returns whether the CPU is a
32-bit or a 64-bit one.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu-qom.h | 2 ++
target/mips/cpu.c | 6 ++
2 files changed, 8 insertions(+)
diff --git a/target/mips/cpu-q
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> Now that we can have multiple user-creatable smmuv3-accel devices,
> each associated with different pci buses, update IORT ID mappings
> accordingly.
>
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/virt-acpi-build.c | 113 +++
On 3/25/25 10:40, Philippe Mathieu-Daudé wrote:
mips_env_64bit_enabled() returns whether the CPU is running
in 32-bit or 64-bit (behavior which might change at runtime).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/
On 19/3/25 12:01, Gerd Hoffmann wrote:
Catch lseek errors. Return on errors.
Use autoptr for the GString to simplify cleanup.
Signed-off-by: Gerd Hoffmann
---
hw/uefi/var-service-json.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Da
On Mon, Mar 24, 2025 at 3:34 PM Sahil Siddiq wrote:
>
> Hi,
>
> I had a few more queries here as well.
>
> On 3/24/25 7:29 PM, Sahil Siddiq wrote:
> > Detect when used descriptors are ready for consumption by the guest via
> > packed virtqueues and forward them from the device to the guest.
> >
>
On 3/25/25 15:43, Richard Henderson wrote:
This define isn't used.
Signed-off-by: Richard Henderson
---
target/avr/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 84a8f5cc8c..b49e7a7056 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
On Tue, Mar 25, 2025 at 1:47 PM John Snow wrote:
>
>
> On Tue, Mar 25, 2025 at 5:41 AM Markus Armbruster
> wrote:
>
>> John Snow writes:
>>
>> > This patch changes the qapidoc transmogrifier to generate Return value
>> > documentation for any command that has a return value but hasn't
>> > expl
The SEEK_CUR case in qio_channel_block_seek was incorrectly using the
'whence' parameter instead of the 'offset' parameter when calculating the
new position.
Fixes: 65cf200a51ddc6d0a28ecceac30dc892233cddd7 ("migration: introduce a
QIOChannel impl for BlockDriverState VMState")
Signed-off-by: Mar
On Wed, Mar 26, 2025 at 05:22:30PM +0100, Marco Cavenati wrote:
> The SEEK_CUR case in qio_channel_block_seek was incorrectly using the
> 'whence' parameter instead of the 'offset' parameter when calculating the
> new position.
>
> Fixes: 65cf200a51ddc6d0a28ecceac30dc892233cddd7 ("migration: intro
On 25/03/25, Philippe Mathieu-Daudé wrote:
> - Remove the TARGET_MIPS64 use in 'cpu-qom.h' to
> make it target agnostic
> - Introduce mips_cpu_is_64bit() as a runtime check
> for compile time TARGET_MIPS64 definition
> - Replace the ldtul_p() gdbstub call by ldn_p()
> - Rename few symbols to av
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 16
target/arm/cpu.c | 15 +--
target/arm/cpu.h | 2 --
target/arm/cpu64.c
On 3/25/25 15:44, Richard Henderson wrote:
Now that we can handle the MCU allocating only a portion of the
first page to i/o, increase the page size. Choose 10 as larger
than the i/o on every MCU, just so that this path is tested.
Signed-off-by: Richard Henderson
---
target/avr/cpu-param.h |
Louis-Vincent DERIAN writes:
> Hello,
>
>
>
> My name is Louis-Vincent DERIAN, and I work for STMicroelectronics. We are
> interested in using your software to facilitate
> our development and testing processes. However, we need to know if
> QEMU has ISO 26262 certification.
The QEMU project
On s390x we can now support userspace mmio and mmap
from vfio. This patch uses s390x mmio support to
enable the NVMe userspace driver for s390x.
Signed-off-by: Farhan Ali
---
block/nvme.c | 95 ++--
1 file changed, 77 insertions(+), 18 deletions(-)
Starting with z15 (or newer) we can execute mmio
instructions from userspace. On older platforms
where we don't have these instructions available
we can fallback to using system calls to access
the PCI mapped resources.
This patch adds helper functions for mmio reads
and writes for s390x.
Signed-
On Tue, Mar 25, 2025 at 02:11:40AM +, Suravee Suthikulpanit wrote:
> Currently, the QEMU-emulated AMD IOMMU device use PCI vendor id 0x1022
> (AMD) with device id zero (undefined). Eventhough this does not cause any
> functional issue for AMD IOMMU driver since it normally uses information
> in
On Wed, Mar 26, 2025 at 1:34 PM wrote:
>
> From: Qiang Yu
>
> mesa/radeonsi is going to support explicit modifier which
> may export a multi-plane texture. For example, texture with
> DCC enabled (a compressed format) has two planes, one with
> compressed data, the other with meta data for compre
On Wed, Mar 26, 2025 at 1:34 PM wrote:
>
> From: Qiang Yu
>
> It's used already, just check it explicitly.
>
> Signed-off-by: Qiang Yu
> ---
> ui/egl-helpers.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/ui/egl-helpers.c b/ui/egl-helpers.c
> index d194d00
On Tue, Mar 25, 2025 at 07:47:15AM +0100, Thomas Huth wrote:
> From: Thomas Huth
>
> These tests currently fail if VNC support has not been compiled into
> the QEMU binary. Let's add some checks to skip the tests in that
> case instead.
>
> Signed-off-by: Thomas Huth
> ---
> tests/functional/t
Hi
On Wed, Mar 26, 2025 at 1:34 PM wrote:
>
> From: Qiang Yu
>
> To handle multi plane.
>
> v2:
> * use new dmabuf API and check length
>
> Signed-off-by: Qiang Yu
> ---
> ui/dbus-display1.xml | 37 +++
> ui/dbus-listener.c | 108 ---
>
On Mon, Mar 24, 2025 at 2:59 PM Sahil Siddiq wrote:
>
> This commit refactors vhost_svq_add_split and vhost_svq_add to simplify
> their implementation and prepare for the addition of packed vqs in the
> following commits.
>
> Signed-off-by: Sahil Siddiq
> ---
> No changes from v4 -> v5.
>
You ca
Philippe Mathieu-Daudé writes:
> When TARGET_LONG_BITS == 64, ldtul_p() expand to ldq_p().
> Directly use the expanded form for clarity.
>
> Signed-off-by: Philippe Mathieu-Daudé
Queued to gdbsub/next, thanks.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Philippe Mathieu-Daudé writes:
> Replace the few ldtul_p() calls by a generic ldn_p() ones.
> No logical change.
Queued to gdbstub/next, thanks.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Mon, Mar 24, 2025 at 3:00 PM Sahil Siddiq wrote:
>
> Introduce "struct vring_packed".
>
> Modify VhostShadowVirtqueue so it can support split and packed virtqueue
> formats.
>
> Signed-off-by: Sahil Siddiq
> ---
> Changes from v4 -> v5:
> - This was commit #3 in v4. This has been reordered to
For VDPA devices, Allow configurations where the hardware MAC address
is non-zero while the MAC address in the QEMU command line is zero.
Signed-off-by: Cindy Lu
---
hw/net/virtio-net.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
On Mon, 2025-03-24 at 19:58 +0100, Philippe Mathieu-Daudé wrote:
> Both s390_cpu_list() and s390_set_qemu_cpu_model() are
> defined in cpu_models.c, move their declarations in the
> related "cpu_models.h" header. Use full path to header
> in s390-virtio-ccw.c file.
>
> Suggested-by: Thomas Huth
>
When using a VDPA device, it is important to ensure that the MAC address
is correctly set. In this patch series, we add a new parameter to
enable this check.
Only three MAC setup configurations are acceptable; any other will
fail to boot.
The usage is:
-netdev
type=vhost-vdpa,vhostdev=/dev/v
On Tue, Mar 25, 2025 at 09:00:20PM +0100, Thomas Huth wrote:
> From: Thomas Huth
>
> This way we can do a full boot in record-replay mode and
> should get a similar test coverage compared to the old
> replay test from tests/avocado/replay_linux.py.
>
> Since the aarch64 test was the last avocado
For VDPA devices, Allow configurations where both the hardware MAC address
and QEMU command line MAC address are zero.
Signed-off-by: Cindy Lu
---
hw/net/virtio-net.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 1fd0403d5d..d1
Philippe Mathieu-Daudé writes:
> Last uses of ldtul_be_p() were removed in commit 78920b4ff2b
> ("target/sparc: Use explicit big-endian LD/ST API"), and of
> ldtul_le_p() in 39631d57d7c ("target/riscv: Use explicit
> little-endian LD/ST API"). Remove these legacy macros.
I'm guessing these are c
On Tue, Mar 25, 2025 at 1:39 PM Philippe Mathieu-Daudé
wrote:
>
> When the cache-controller feature is not implemented,
> log potential ASI access as unimplemented.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/sparc/ldst_helper.c | 8
> 1 file changed, 8 insertions(+)
>
> di
On Wed, Mar 26, 2025 at 05:26:32PM +0800, zoudongjie wrote:
> From: Zhu Yangyang
>
> Calling qmp_block_set_io_throttle() will be blocked for a long time
> when a network disk is configured and the network failure is just about
> to occur.
>
> This series add a timeout parameter for qmp_block_set
Am 25.03.2025 um 21:49 hat ~h0lyalg0rithm geschrieben:
> From: Suraj Shirvankar
>
> Signed-off-by: Suraj Shirvankar
> ---
> util/fdmon-io_uring.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
As Stefan already mentioned, the commit message should say why we want
to set this fl
Next iteration of the id register patches; only small changes.
Changed from v3:
- added R-bs (thanks!)
- added missing SPDX header
- merged patch introducing accessors for kvm to the first user
- skip over sysregs outside of the id register range when generating
register definitions again
Also
From: Eric Auger
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate the storage of those
ID regs from named
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 40 -
target/arm/cpu.c | 29
target/arm/cpu.h | 2 --
From: Eric Auger
Also add kvm add accessors for storing host features into idregs.
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 57 ---
target/arm/cpu-sysr
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 74 +++
target/arm/cpu.h | 4 ---
target/arm/cpu64.c| 8 ++---
target/arm/h
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 5 +-
target/arm/cpu-features.h | 10 ++--
target/arm/cpu.c | 8 +--
target/arm/cpu.h | 3 -
target/arm/c
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 6 +++---
target/arm/cpu.h | 1 -
target/arm/cpu64.c| 7 ++-
target/arm/helper.c | 2 +-
target/arm/kvm
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> If a vSMMU is configured as a accelerated one, HW IOTLB will be used
> and all cache invalidation should be done to the HW IOTLB too, v.s.
> the emulated iotlb. In this case, an iommu notifier isn't registered,
> as the device
Generated against Linux 6.14-rc1.
Reviewed-by: Sebastian Ott
Signed-off-by: Cornelia Huck
---
target/arm/cpu-sysregs.h.inc | 43 +---
1 file changed, 30 insertions(+), 13 deletions(-)
diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
index
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 12 ++--
target/arm/cpu-features.h | 36 +-
target/arm/cpu.c | 24 +++
target/arm/cpu.h | 7 --
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 8 ++--
target/arm/cpu-features.h | 18
target/arm/cpu.h | 6 ---
target/arm/cpu64.c| 16 +++
targ
From: Eric Auger
Introduce scripts that automate the generation of system register
definitions from a given linux source tree arch/arm64/tools/sysreg.
Invocation of
./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TREE
in scripts directory generates target/arm/cpu-sysregs.h.inc
containing d
On Wed, Mar 26, 2025 at 06:13:44PM +0100, Kevin Wolf wrote:
> Am 25.03.2025 um 21:49 hat ~h0lyalg0rithm geschrieben:
> > From: Suraj Shirvankar
> >
> > Signed-off-by: Suraj Shirvankar
> > ---
> > util/fdmon-io_uring.c | 8 +++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
>
> As Stef
On Mon, 2025-03-24 at 19:58 +0100, Philippe Mathieu-Daudé wrote:
> Register s390_cpu_list() as CPUClass:list_cpus callback
> and remove the cpu_list definition.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/s390x/cpu.h | 3 ---
> target/s390x/cpu.c | 1 +
> 2 files changed, 1 insertio
On 3/25/25 15:43, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/avr/cpu.h| 10 ++
target/avr/helper.c | 36 ++--
2 files changed, 28 insertions(+), 18 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index b49e7
This silently fixes issues resulting from trying to allocate 0 bytes.
Fixes error, for example, for writing byte 0x20 to port 0x3c0, then word 0xf09
to port 0x3b4 when CPU is initiated, which shouldn't break.
Signed-off-by: donno2048
---
util/memfd.c | 10 +++---
1 file changed, 7 insertio
On Wed, Mar 26, 2025 at 04:52:54PM +0100, Valentin David wrote:
> Without it, it seems the data gets garbage at the end of the string.
>
> Signed-off-by: Valentin David
> ---
> hw/smbios/smbios.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
>
Hello,
My name is Louis-Vincent DERIAN, and I work for STMicroelectronics. We are
interested in using your software to facilitate our development and testing
processes. However, we need to know if QEMU has ISO 26262 certification.
Could you please provide us with information about the ISO 26262
Reviewed-by: Clément Chigot
On Tue, Mar 25, 2025 at 1:39 PM Philippe Mathieu-Daudé
wrote:
>
> Keep CPUSPARCState for architectural fields, move Leon3
> hardware specific fields to SPARCCPU.
>
> Reset the Leon3 specific 'cache_control' field in
> leon3_cpu_reset() instead of sparc_cpu_reset_hold
On 3/25/25 15:43, Richard Henderson wrote:
Integrate the i/o 0x00-0x1f and 0x38-0x3f loopbacks into
the cpu registers with normal address space accesses.
We no longer need to trap accesses to the first page within
avr_cpu_tlb_fill but can wait until a write occurs.
Signed-off-by: Richard Henders
On 3/25/25 08:40, Philippe Mathieu-Daudé wrote:
mips_env_64bit_enabled() returns whether the CPU is running
in 32-bit or 64-bit (behavior which might change at runtime).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/
On 3/25/25 08:40, Philippe Mathieu-Daudé wrote:
MIPS MMU API declared in tcg-internal.h has public linkage.
In order to avoid name clashing with other targets, prefix
the API with 'mips_'.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/tcg-internal.h | 2 +-
target/mips/cpu.c
On 3/25/25 08:40, Philippe Mathieu-Daudé wrote:
"target/foo/cpu-qom.h" can not use any target specific definitions.
Currently "target/mips/cpu-qom.h" defines TYPE_MIPS_CPU depending
on the mips(32)/mips64 build type. This doesn't scale in a
heterogeneous context where we need to access both type
Hi,
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> With nested translation, the underlying HW could support those two fields.
> Allow them according to the updated idr registers after the hw_info ioctl.
s/idr/IDR
>
> When substreams are enabled (S1CDMax != 0), S1DSS field de
On 26/03/25 13:39, Cédric Le Goater wrote:
On 3/25/25 18:38, Aditya Gupta wrote:
<...snip...>
On 25/03/25 22:45, Cédric Le Goater wrote:
One nice about it IIRC was being able to tune the number of
PHBs per chip, which reduced booting time (for 16s) and also
provided support to test various ch
On 26/03/25 16:12, Cédric Le Goater wrote:
[ ... ]
You could use a buildroot image instead. :
https://github.com/buildroot/buildroot/blob/master/configs/qemu_ppc64le_powernv8_defconfig
Images pushed here :
https://github.com/legoater/qemu-ppc-boot/tree/main/buildroot/qemu_ppc64le_powernv8-
There is no need for aio_context_use_g_source() now that epoll(7) and
io_uring(7) file descriptor monitoring works with the glib event loop.
AioContext doesn't need to be notified that GSource is being used.
Signed-off-by: Stefan Hajnoczi
---
include/block/aio.h | 3 ---
tests/uni
On Mon, 2025-03-10 at 16:14 +0100, Philippe Mathieu-Daudé wrote:
> The storage keys are part of the machine memory.
>
> Introduce the TYPE_DUMP_SKEYS_INTERFACE type,
> allowing machine using storage keys to dump them
> when a DumpSKeysInterface::qmp_dump_skeys() callback
> is provided.
>
> Signed
test-nested-aio-poll relies on internal details of how fdmon-poll.c
handles AioContext polling. Skip it when other fdmon implementations are
in use.
Note that this test is only built on POSIX systems so it is safe to
include "util/aio-posix.h".
Signed-off-by: Stefan Hajnoczi
---
tests/unit/test
The io_uring(7) file descriptor monitor cannot enter polling mode
because it needs to submit a POLL_ADD SQE every time a file descriptor
becomes active. Submitting SQEs only happens in FDMonOps->wait() outside
of polling mode.
Fix this using the multi-shot mechanism introduced in Linux 5.13 and
li
On Tue, Mar 25, 2025 at 09:49:38PM +0100, ~h0lyalg0rithm wrote:
> From: Suraj Shirvankar
>
Please include the rationale for this change in the commit description.
This way anyone reading the git log will be able to understand the
intent behind this change. Something like:
IORING_SETUP_SINGLE_
Recently, we removed ipv6 restriction[0] from RDMA migration, add a
test for it.
[0]
https://lore.kernel.org/qemu-devel/20250326095224.9918-1-jinpu.w...@ionos.com/
Cc: Jack Wang
Cc: Michael R. Galaxy
Cc: Peter Xu
Cc: Yu Zhang
Signed-off-by: Li Zhijian
---
This test is added based on [1]
S
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
second release candidate for the QEMU 10.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu.org/qemu-10.0.0-rc1.tar.xz
http://download.qe
Hello Jinqian
On 3/25/25 09:00, yangjinqian via wrote:
Hi,
I'm observing intermittent failures when enabling the HNS3 network port in VM
using
QEMU with the mainline kernel.
Would you mind opening a gitlab issue with more details on the
context, host, guest, HW ?
https://gitlab.com/qem
On 3/26/2025 2:46 PM, Dongli Zhang wrote:
> Hi Dapeng,
>
> PATCH 1-4 from the below patchset are already reviewed. (PATCH 5-10 are for
> PMU
> registers reset).
>
> https://lore.kernel.org/all/20250302220112.17653-1-dongli.zh...@oracle.com/
>
> They require only trivial modification. i.e.:
>
> h
On Wed, Mar 26, 2025 at 02:38:04PM +0100, Eric Auger wrote:
> > +/* Update batch->ncmds to the number of execute cmds */
> > +int smmuv3_accel_issue_cmd_batch(SMMUState *bs, SMMUCommandBatch *batch)
> > +{
> > +SMMUv3AccelState *s_accel = ARM_SMMUV3_ACCEL(bs);
> > +uint32_t total = batch->n
AioContext's glib integration only supports ppoll(2) file descriptor
monitoring. epoll(7) and io_uring(7) disable themselves and switch back
to ppoll(2) when the glib event loop is used. The main loop thread
cannot use epoll(7) or io_uring(7) because it always uses the glib event
loop.
Future QEMU
This series hooks the epoll and io_uring file descriptor monitoring
implementations up to the glib event loop so that even the main loop thread can
use them. Until now the main loop thread was stuck using ppoll(2) because the
glib event loop semantics weren't supported by fdmon-epoll.c and
fdmon-io
On 3/7/25 12:15, Fabiano Rosas wrote:
> From: Steve Sistare
>
> Unlike cpr-reboot mode, cpr-transfer mode cannot save volatile ram blocks
> in the migration stream file and recreate them later, because the physical
> memory for the blocks is pinned and registered for vfio. Add a blocker
> for vo
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