[Stable-9.2.3 52/69] target/arm: Make DisasContext.{fp, sve}_access_checked tristate

From: Richard Henderson The check for fp_excp_el in assert_fp_access_checked is incorrect. For SME, with StreamingMode enabled, the access is really against the streaming mode vectors, and access to the normal fp registers is allowed to be disabled. C.f. sme_enabled_check. Convert sve_access_ch

[Stable-9.2.3 57/69] docs/about/emulation: Fix broken link

From: Santiago Monserrat Campanello semihosting link to risc-v changed Signed-off-by: Santiago Monserrat Campanello Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717 Reviewed-by: Alistair Francis Reviewed-by: Thomas Huth Message-ID: <20250305102632.91376-1-santimons...@gmail.com> S

[Stable-9.2.3 58/69] target/riscv: fix access permission checks for CSR_SSP

From: Deepak Gupta Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access to CSR_SSP in M-mode. Gated to CSR_SSP is not gated via `xSSE`. But rather rules clearly specified in section "22.2.1. Shadow Stack Poin

[Stable-9.2.3 67/69] target/riscv: fix handling of nop for vstart >= vl in some vector instruction

From: Chao Liu Recently, when I was writing a RISCV test, I found that when VL is set to 0, the instruction should be nop, but when I tested it, I found that QEMU will treat all elements as tail elements, and in the case of VTA=1, write all elements to 1. After troubleshooting, it was found that

[Stable-9.2.3 63/69] target/ppc: Fix facility interrupt checks for VSX

From: Nicholas Piggin Facility interrupt checks in general should come after the ISA version check, because the facility interrupt and facility type themselves are ISA dependent and should not appear on CPUs where the instruction does not exist at all. This resolves a QEMU crash booting NetBSD/m

[Stable-8.2.10 49/51] linux-user/riscv: Fix handling of cpu mask in riscv_hwprobe syscall

From: Richard Henderson The third argument of the syscall contains the size of the cpu mask in bytes, not bits. Nor is the size rounded up to a multiple of sizeof(abi_ulong). Cc: qemu-sta...@nongnu.org Reported-by: Andreas Schwab Fixes: 9e1c7d982d7 ("linux-user/riscv: Add syscall riscv_hwprobe

[Stable-7.2.17 33/34] target/ppc: Fix e200 duplicate SPRs

From: Nicholas Piggin DSRR0/1 registers are in the BookE ISA not e200 specific, so remove the duplicate e200 register definitions. Cc: Roman Kapl Cc: qemu-sta...@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2768 Fixes: 0e3bf4890906 ("ppc: add DBCR based debugging") Signed-

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