On 3/24/25 14:11, Pierrick Bouvier wrote:
On 3/23/25 12:37, Richard Henderson wrote:
On 3/20/25 15:29, Pierrick Bouvier wrote:
This does not hurt, even if they are not used.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/a
On 3/23/25 10:37, Richard Henderson wrote:
Prepare for offset_io being non-zero in do_stb.
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 9608e59584..3323f32c22 100
On 3/23/25 10:37, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
hw/avr/atmega.h | 20
hw/avr/atmega.c | 22 +-
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h
index a99ee15c7e..f031e6c
On 3/23/25 10:37, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 7cfd3d1093..9608e59584 100644
--- a/target/avr/helper.c
+++ b/ta
On 3/23/25 10:37, Richard Henderson wrote:
Prepare for offset_io being non-zero when accessing from gdb.
Signed-off-by: Richard Henderson
---
target/avr/cpu.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 080f6f3
On 3/23/25 10:37, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/avr/cpu-param.h | 8 +--
hw/avr/atmega.c| 54 ++
2 files changed, 35 insertions(+), 27 deletions(-)
diff --git a/target/avr/cpu-param.h b/target/avr/cp
On 3/23/25 10:37, Richard Henderson wrote:
We want to be able to do more common work on MachineClass.
Pass the class name as a string in .class_data.
Signed-off-by: Richard Henderson
---
hw/avr/arduino.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
Reviewed-by: P
On 3/23/25 10:37, Richard Henderson wrote:
Avoid direct use of address_space_memory.
Make use of the softmmu cache of the i/o page.
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
Reviewed-by: Pierrick Bouvier
On 3/24/25 18:22, Richard Henderson wrote:
On 3/24/25 14:31, Pierrick Bouvier wrote:
On 3/23/25 12:48, Richard Henderson wrote:
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
hw/arm/armv7m.c | 12
1 file changed, 8 insertions(+), 4 deletions(
Hi,
> > Going ship the distro kernel as igvm image would work too. Will
> > simplify the measurement pre-calculation. Also there is no need to pass
> > around any parameters, everything (how the firmware finds the UKI etc)
> > can be arranged at igvm build time then. Disadvantage: This introd
This patch series refactors QEMU's FUSE export module to leverage coroutines
for read/write operations,
addressing concurrency limitations and aligning with QEMU's asynchronous I/O
model. The changes
demonstrate measurable performance improvements while simplifying resource
management.
1. techn
From: Qiang Yu
mesa/radeonsi is going to support explicit midifier which
may export a multi-plane texture. For example, texture with
DCC enabled (a compressed format) has two planes, one with
compressed data, the other with meta data for compression.
Signed-off-by: Qiang Yu
---
hw/display/vhos
From: Qiang Yu
mesa/radeonsi is going to support explicit modifier with this MR:
* https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658
The side effect is some texture will become multi-plane which
breaks qemu. Because qemu currently only support single plane
texture.
For example,
From: Qiang Yu
It's used already, just check it explicitly.
Signed-off-by: Qiang Yu
---
ui/egl-helpers.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/ui/egl-helpers.c b/ui/egl-helpers.c
index 72a1405782..45b1b0b700 100644
--- a/ui/egl-helpers.c
+++ b/ui/egl-he
From: Qiang Yu
0 is used as DRM_FORMAT_MOD_LINEAR already.
Signed-off-by: Qiang Yu
---
hw/display/vhost-user-gpu.c | 3 ++-
hw/display/virtio-gpu-udmabuf.c | 4 +++-
ui/egl-helpers.c| 3 ++-
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/display/vhost-use
From: Qiang Yu
To handle multi plane.
Signed-off-by: Qiang Yu
---
ui/dbus-display1.xml | 37
ui/dbus-listener.c | 103 ---
2 files changed, 133 insertions(+), 7 deletions(-)
diff --git a/ui/dbus-display1.xml b/ui/dbus-display1.xml
in
From: Qiang Yu
Signed-off-by: Qiang Yu
---
meson.build| 2 +-
ui/spice-display.c | 65 +++---
2 files changed, 34 insertions(+), 33 deletions(-)
diff --git a/meson.build b/meson.build
index 9d9c11731f..b87704a83b 100644
--- a/meson.build
+++ b/m
> -Original Message-
> From: Nicolin Chen
> Sent: Thursday, March 20, 2025 5:03 PM
> To: Shameerali Kolothum Thodi
> Cc: Donald Dutile ; qemu-...@nongnu.org; qemu-
> de...@nongnu.org; eric.au...@redhat.com; peter.mayd...@linaro.org;
> j...@nvidia.com; berra...@redhat.com; nath...@nvidi
Hello Aditya,
On 3/8/25 21:51, Aditya Gupta wrote:
Overview
Add support for Power11 powernv machine type, to emulate PowerNV VMs
running on Power11.
Could you please consider deprecating the POWER8NVL and POWER8E CPUs
and associated chips and machines ? I think keeping POWER8 is
Signed-off-by: Changzhi Xie
This commit refactors the FUSE export to process read and write operations
using coroutines, improving concurrency and avoiding blocking the main loop.
The main changes include:
1. Move read_from_fuse_export into coroutine
2. Move read/write processing into coroutin
On 3/24/25 08:13, Aditya Gupta wrote:
Hi Cedric,
On 09/03/25 19:38, Cédric Le Goater wrote:
On 3/8/25 21:51, Aditya Gupta wrote:
<...snip...>
static void pnv_chip_power8_instance_init(Object *obj)
{
Pnv8Chip *chip8 = PNV8_CHIP(obj);
@@ -1966,6 +1996,20 @@ static void pnv_chip_power1
From: Qiang Yu
Signed-off-by: Qiang Yu
---
include/ui/egl-helpers.h | 5 ++-
ui/dbus-listener.c | 19 +
ui/egl-helpers.c | 86 +---
ui/spice-display.c | 58 ++-
4 files changed, 116 insertions(+), 52 deleti
On 3/20/25 15:29, Pierrick Bouvier wrote:
This identifier is poisoned, so it can't be used from common code
anyway. We replace all occurrences with its definition directly.
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h| 12
linux-user/syscall_defs.h | 2 +-
bsd
On 3/20/25 15:30, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
hw/arm/meson.build | 112 ++---
1 file changed, 56 insertions(+), 56 deletions(-)
Reviewed-by: Richard Henderson
r~
On 23/3/25 20:07, Richard Henderson wrote:
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition,
have each target set the 'mttcg_supported' field in the TCGCPUOps
structure.
Since so far we only emulate one target architecture at a ti
On Mon, Mar 24, 2025 at 12:00:06AM +0100, Philippe Mathieu-Daudé wrote:
> The break in the QEMU_OPTION_machine case is mis-placed.
I think that's largely a bikeshed colouring question. If you
look at other places in the outer switch using a block in
the case, eg
case FOO:
{
On 24/03/25 13:05, Cédric Le Goater wrote:
On 3/24/25 08:13, Aditya Gupta wrote:
Hi Cedric,
<...snip...>
When I do this, every function using Pnv10Chip* will need to be
duplicated to use Pnv11Chip*.
I will do that.
But what do you say about changing Pnv10 chip to Pnv1x chip ? It may
only
On Sun, Mar 23, 2025 at 10:35:54PM +0100, Daan De Meyer wrote:
> We have to make sure the array of bytes read from the path= file
> is null-terminated, otherwise we run into a buffer overrun later on.
>
> Fixes: bb99f4772f54017490e3356ecbb3df25c5d4537f ("hw/smbios: support loading
> OEM strings v
On 23/03/2025 23.40, Philippe Mathieu-Daudé wrote:
Register sparc_cpu_list() as CPUClass:list_cpus callback.
Reduce its scope and remove the cpu_list definition.
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu.h | 3 ---
target/sparc/cpu.c | 3 ++-
2 files changed, 2 insertions(+
On 23/03/2025 23.40, Philippe Mathieu-Daudé wrote:
Some targets define cpu_list to a method listing their
CPUs on stdout. In order to make list_cpus() generic,
introduce the CPUClass::list_cpus() callback.
When no callback is registered, list_cpus() defaults
to the cpu_list definition.
Signed-of
On 23/03/2025 23.40, Philippe Mathieu-Daudé wrote:
Register x86_cpu_list() as CPUClass:list_cpus callback.
Reduce its scope and remove the cpu_list definition.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.h | 3 ---
target/i386/cpu.c | 3 ++-
2 files changed, 2 insertions(+), 4
Hi
On Mon, Mar 24, 2025 at 12:20 PM wrote:
>
> From: Qiang Yu
>
> Signed-off-by: Qiang Yu
> ---
> meson.build| 2 +-
> ui/spice-display.c | 65 +++---
> 2 files changed, 34 insertions(+), 33 deletions(-)
>
> diff --git a/meson.build b/meson.buil
On 23/03/2025 23.40, Philippe Mathieu-Daudé wrote:
Register sparc_cpu_list() as CPUClass:list_cpus callback
and remove the cpu_list definition.
Copy-n-paste error in both, subject and patch description: This should be
about s390x, not sparc.
diff --git a/target/s390x/cpu.h b/target/s390x/cp
For some registers with width 8 bytes, its name is something like
PCH_PIC_INT_ID_LO and PCH_PIC_INT_ID_HI. From hardware manual,
register name is PCH_PIC_INT_ID instead. Here name PCH_PIC_INT_ID
is used, and PCH_PIC_INT_ID + 4 is used for PCH_PIC_INT_ID_HI.
Signed-off-by: Bibo Mao
---
hw/intc/lo
For memory region iomem32_low, generic write callback is used.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 140 +++-
1 file changed, 73 insertions(+), 67 deletions(-)
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
index 01e6f
Add iomem32_high region register write operation emulation in generic
write function loongarch_pch_pic_write(), and use this function for
iomem32_high region.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 28 +---
1 file changed, 5 insertions(+), 23 deletions(
Add trace event trace_loongarch_pch_pic_read(), replaces the following
three events:
trace_loongarch_pch_pic_low_readw()
trace_loongarch_pch_pic_high_readw()
trace_loongarch_pch_pic_readb()
The similiar with write trace event.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 24 ++
Parameter address for read and write callback in MemoryRegionOps is
relative offset with base address of this MemoryRegionOps. It can
be directly used as offset and offset calculation can be removed.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 34 --
Add iomem8 region register read operation emulation in generic read
function loongarch_pch_pic_read(), and use this function for iomem8
region.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 32 +++-
1 file changed, 11 insertions(+), 21 deletions(-)
diff -
Register PCH_PIC_INT_ID constains version and supported irq number
information, and it is read only register. The detailed value can
be set at initial stage, rather than read callback.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c| 17 ++---
include/hw/intc/loon
For memory region iomem32_low, generic read callback is used.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 71 +
1 file changed, 48 insertions(+), 23 deletions(-)
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
index 10b423
Rename memory region iomem32_low with iomem, also change ops name
as follows:
loongarch_pch_pic_reg32_low_ops --> loongarch_pch_pic_ops
loongarch_pch_pic_low_readw --> loongarch_pch_pic_read
loongarch_pch_pic_low_writew --> loongarch_pch_pic_write
Signed-off-by: Bibo Mao
---
hw/i
Since memory region iomem supports memory access size with 1/2/4/8,
it can be used for memory region iomem8 and iomem32_high. Now remove
memory region iomem8 and iomem32_high, merge them into iomem together.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c| 66 +---
On 23/03/2025 23.40, Philippe Mathieu-Daudé wrote:
Register ppc_cpu_list() as CPUClass:list_cpus callback.
Reduce its scope and remove the cpu_list definition.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu.h | 4
target/ppc/cpu_init.c | 3 ++-
2 files changed, 2 inserti
On 23/03/2025 23.40, Philippe Mathieu-Daudé wrote:
Since we removed all definitions of cpu_list, the #ifdef
check is always true. Remove it, inlining cpu_list().
Signed-off-by: Philippe Mathieu-Daudé
---
cpu-target.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
The meaning of macro definition STATUS_LO_START is simliar with
PCH_PIC_INT_STATUS, only that offset is different, the same for
macro POL_LO_START. Now remove these duplicated macro definitions.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c| 20 ++--
include
This series patchset is to clean up with memory regions of loongarch pch
pic interrupt controller. Originally there are three iomem regions:
iomem32_low, iomem8, iomem32_highm. Since these regions only support
4 bytes/1 byte/4 bytes access, it is divided into three regions.
Now it is merged into o
Add iomem8 region register write operation emulation in generic write
function loongarch_pch_pic_write(), and use this function for iomem8
region.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 31 ++-
1 file changed, 10 insertions(+), 21 deletions(-)
diff
The original iomem region only supports 4 bytes access size, set it ok
with 1/2/4/8 bytes. Also unaligned memory access is not supported.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/hw/intc/loongarch_p
Since Sapphire Rapids starts, VMX instrocude a new bit
SAVE_IA32_PERF_GLOBAL_CTRL in VMCS VM-EXIT control field to manage if
vmx can save guest PERF_GLOBAL_CTRL MSR.
This patch enables this feature.
Signed-off-by: Dapeng Mi
---
target/i386/cpu.c | 12
target/i386/cpu.h | 1 +
2 fi
From: Xiaoyao Li
Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent
work prior to create any vcpu. This is for i386 TDX because it needs
call TDX_INIT_VM before creating any vcpu.
The specific implemnet of i386 will be added in the future patch.
Signed-off-by: Xiaoyao Li
Acked-by:
After introducing mediated vPMU, mediated vPMU must be enabled by
explicitly calling KVM_CAP_PMU_CAPABILITY to enable. Thus call
KVM_CAP_PMU_CAPABILITY to enable/disable PMU base on user configuration.
Suggested-by: Zhao Liu
Signed-off-by: Dapeng Mi
---
target/i386/kvm/kvm.c | 17 ++
This small patch series enables the newly introduced KVM x86 mediated
vPMU solution. As KVM maintainer's suggestion, KVM mediated vPMU is
disabled by default unless user explicitly calls KVM_CAP_PMU_CAPABILITY
ioctl to enable it.
As for mediated vPMU, it's a new pass-through vPMU solution which is
When the cpu is created, qemu_add_vm_change_state_handler
is called in the kvm_arch_init_vcpu function to create
the VMChangeStateEntry resource.
However, the resource is not released when the cpu is destroyed.
This results in a qemu process segment error when the virtual
machine restarts after th
When the cpu is created, qemu_add_vm_change_state_handler
is called in the kvm_arch_init_vcpu function to create
the VMChangeStateEntry resource.
However, the resource is not released when the cpu is destroyed.
This results in a qemu process segment error when the virtual
machine restarts after th
VFIO uses migration_file_set_error() in a couple of places where an
'Error **' parameter is not provided. In MemoryListener handlers :
vfio_listener_region_add
vfio_listener_log_global_stop
vfio_listener_log_sync
and in callback routines for IOMMU notifiers :
vfio_iommu_map_notify
vfio
With the latest 7A1000 user manual, interrupt status register ISR is
read only. Here discard write operation with ISR register.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic
From: Thomas Huth
A bunch of tests are using "-netdev user" but fail to check
for the availability of SLIRP in the binary, so these tests
fail if QEMU has been configured with "--disable-slirp"
(most of the tests are disabled by default with a decorator,
that's likely why nobody noticed this prob
From: Nikita Shubin
Add STM32 DMA model and include it in STM32F100 SoC.
The model is fully compatible with GD32F30x DMA.
To: qemu-devel@nongnu.org
Cc: Paolo Bonzini
Cc: Alistair Francis
Cc: Peter Maydell
Cc: qemu-...@nongnu.org
Cc: Alexandre Iooss
Cc: Fabiano Rosas
Cc: Laurent Vivier
Cc:
Alex Bennée writes:
> The current helper.h functions rely on hard coded assumptions about
> target endianess to use the tswap macros. We also end up double
> swapping a bunch of values if the target can run in multiple endianess
> modes. Avoid this by getting the target to pass the endianess and
On Mon, Mar 24, 2025 at 1:13 PM Gerd Hoffman wrote:
>
> Hi,
>
> > > Going ship the distro kernel as igvm image would work too. Will
> > > simplify the measurement pre-calculation. Also there is no need to pass
> > > around any parameters, everything (how the firmware finds the UKI etc)
> > > c
Hi,
On Fri, 21 Mar 2025 at 19:34, Fabiano Rosas wrote:
> Well, I can't speak for everyone, of course, but generally the less
> layers on top of the object of your work the better.
* Yes, true.
> There are several ways of accessing QMP, some examples I have lying
> around:
>
> ==
> $QEMU ... -
On Wed, Mar 19, 2025 at 05:36:20PM +0100, Juraj Marcin wrote:
> From: Juraj Marcin
>
> The default idle period for TCP connection could be even 2 hours.
> However, in some cases, the application needs to be aware of a
> connection issue much sooner.
>
> This is the case, for example, for postcop
The current helper.h functions rely on hard coded assumptions about
target endianess to use the tswap macros. We also end up double
swapping a bunch of values if the target can run in multiple endianess
modes. Avoid this by getting the target to pass the endianess and size
via a MemOp and fixing up
Reviewed-by: Pierrick Bouvier
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
---
include/gdbstub/commands.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/gdbstub/commands.h b/include/gdbstub/commands.h
index 40f0514fe9..bff3674872 100644
--- a/inclu
This is a pretty simple conversion given a single set of registers and
an existing helper to probe endianess.
Signed-off-by: Alex Bennée
---
v2
- use mb_cpu_is_big_endian
- use explicit MO_32 size
- handle differing size of env->ear between user/system
---
target/microblaze/gdbstub.c | 49
The aim of this work is to get rid of the endian aware helpers in
gdbstub/helpers.h which due to their use of tswap() mean target
gdbstubs need to be built multiple times. While this series doesn't
actually build each stub once it introduces a new helper -
gdb_get_register_value() which takes a Mem
It's not used outside of the gdbstub code.
Reviewed-by: Pierrick Bouvier
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
---
target/ppc/cpu.h | 1 -
target/ppc/gdbstub.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
On Mon, Mar 24, 2025 at 12:19 PM wrote:
>
> From: Qiang Yu
>
> 0 is used as DRM_FORMAT_MOD_LINEAR already.
>
> Signed-off-by: Qiang Yu
Reviewed-by: Marc-André Lureau
> ---
> hw/display/vhost-user-gpu.c | 3 ++-
> hw/display/virtio-gpu-udmabuf.c | 4 +++-
> ui/egl-helpers.c
For some of the helpers we need a temporary variable to copy from
although we could add some helpers to return pointers into env in
those cases if we wanted to.
Signed-off-by: Alex Bennée
---
v2
- use MO32/MO64 varients for reg sizes
- use wrappers for 32/64 bit regs
- do SVE Z registers i
On Mon, Mar 24, 2025 at 01:30:16PM +0400, Marc-André Lureau wrote:
> Hi
>
> On Mon, Mar 24, 2025 at 12:20 PM wrote:
> >
> > From: Qiang Yu
Please provide non-empty commit messages.
> >
> > Signed-off-by: Qiang Yu
> > ---
> > meson.build| 2 +-
> > ui/spice-display.c | 65 +++
From: Nikita Shubin
Signed-off-by: Nikita Shubin
---
tests/qtest/meson.build | 1 +
tests/qtest/stm32-dma-test.c | 415 +++
2 files changed, 416 insertions(+)
create mode 100644 tests/qtest/stm32-dma-test.c
diff --git a/tests/qtest/meson.build b/tests/qt
From: Nikita Shubin
Add STM32 DMA support for stm32f100 SoC.
Signals from periphery to DMA are not connected, as no STM32 periphery
currently supports DMA.
Signed-off-by: Nikita Shubin
---
hw/arm/Kconfig | 1 +
hw/arm/stm32f100_soc.c | 51 +
Hi
On Mon, Mar 24, 2025 at 12:19 PM wrote:
>
> From: Qiang Yu
>
> mesa/radeonsi is going to support explicit midifier which
> may export a multi-plane texture. For example, texture with
> DCC enabled (a compressed format) has two planes, one with
> compressed data, the other with meta data for c
On Wed, Mar 19, 2025 at 05:36:19PM +0100, Juraj Marcin wrote:
> From: Juraj Marcin
>
> Commit aec21d3175 (qapi: Add InetSocketAddress member keep-alive)
> introduces the keep-alive flag, which enables the SO_KEEPALIVE socket
> option, but only on client-side sockets. However, this option is also
Hi
On Mon, Mar 24, 2025 at 12:19 PM wrote:
>
> From: Qiang Yu
>
> It's used already, just check it explicitly.
>
> Signed-off-by: Qiang Yu
> ---
> ui/egl-helpers.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/ui/egl-helpers.c b/ui/egl-helpers.c
> index 72
From: Nikita Shubin
STMicroelectronics STM32 SoCs integrate DMA engine that supports:
* Independent concurrent DMA transfers using 7/5 DMA channels
* Generation of interrupts on various conditions during execution
* PERIPH to MEMORY transactions, invoked by peripheral device models
* MEMORY to M
By passing the explicit state of LE/BE via the memop we can avoid the
messing about we do with ppc_maybe_bswap_register() at least for
supplying register values to gdbstub.
The fact we still need the helper for setting the values probably
indicates we could do with a reverse helper, possibly to se
For some of the helpers we need a temporary variable to copy from
although we could add some helpers to return pointers into env in
those cases if we wanted to.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Alex Bennée
---
v2
- use new wrappers
- explicit MO_32 usage and reg32/64 helpers
---
We can handle larger sized memops now, expand the range of the assert.
Fixes: 4b473e0c60 (tcg: Expand MO_SIZE to 3 bits)
Signed-off-by: Alex Bennée
---
v2
- instead of 128 use 1 << MO_SIZE for future proofing
---
include/exec/memop.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Mainly as an aid to myself getting confused too many bswaps deep into
the code.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Alex Bennée
---
target/ppc/cpu.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index efab54a068..1e833ade0
When things go wrong we want to assert on the register that failed to
be able to figure out what went wrong.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbst
On 3/24/25 1:48 AM, Michael Tokarev wrote:
10.03.2025 05:35, Chao Liu wrote:
Recently, when I was writing a RISCV test, I found that when VL is set to 0, the
instruction should be nop, but when I tested it, I found that QEMU will treat
all elements as tail elements, and in the case of VTA=1,
Macro PCH_PIC_HTMSI_VEC_OFFSET and PCH_PIC_ROUTE_ENTRY_OFFSET is renamed
as PCH_PIC_HTMSI_VEC and PCH_PIC_ROUTE_ENTRY separately, it is easier to
understand.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c| 20 ++--
hw/loongarch/virt.c| 2
Hi Cedric,
On 09/03/25 19:38, Cédric Le Goater wrote:
On 3/8/25 21:51, Aditya Gupta wrote:
<...snip...>
static void pnv_chip_power8_instance_init(Object *obj)
{
Pnv8Chip *chip8 = PNV8_CHIP(obj);
@@ -1966,6 +1996,20 @@ static void
pnv_chip_power10_instance_init(Object *obj)
Pn
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/s390x/ipl.h | 1 +
include/exec/cpu-all.h | 3 ---
include/exec/exec-all.h | 1 +
include/exec/tlb-flags.h| 1 +
linux-user/sparc/target_syscall.h | 2 ++
hw/alpha/dp
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/arm/armv7m.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 98a69846119..854498ac51c 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -140,7 +140,7 @@ s
On 3/24/25 21:58, Pierrick Bouvier wrote:
This series focuses on removing compilation units duplication in hw/arm. We
start with this architecture because it should not be too hard to transform it,
and should give us some good hints on the difficulties we'll meet later.
We first start by making
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index d4705210370..d4d05d82315 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -20,7 +2
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 2 --
include/exec/cpu_ldst.h | 1 +
target/alpha/cpu.h | 1 +
target/arm/cpu.h| 1 +
target/avr/cpu.h| 1 +
target/hexagon/cpu.h| 1 +
target/hppa/cpu.h | 1 +
target/i386
We prevent common code to use this define by mistake.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/poison.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/exec/poison.h b/include/exec/poison.h
index f267da60838..a09e0c12631 100644
--- a/include/
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 63
include/exec/tlb-flags.h | 87
accel/tcg/cputlb.c | 1 +
accel/tcg/user-exec.c| 1 +
sem
We prepare to remove cpu.h from cpu-all.h, which will transitively
remove it from accel/tcg/tb-internal.h, and thus from most of tcg
compilation units.
Note: this was caught by a test regression for s390x-softmmu.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/
To eliminate TARGET_AARCH64, we need to make various definitions common
between 32 and 64 bit Arm targets.
Added registers are used only by aarch64 code, and the only impact is on
the size of CPUARMState, and added zarray
(ARMVectorReg zarray[ARM_MAX_VQ * 16]) member (+64KB)
It could be eventually
This series focuses on removing compilation units duplication in hw/arm. We
start with this architecture because it should not be too hard to transform it,
and should give us some good hints on the difficulties we'll meet later.
We first start by making changes in global headers to be able to not
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 4
cpu-target.c | 4
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 74017a5ce7c..b1067259e6b 100644
--- a/include/
We introduce later a mechanism to skip cpu definitions inclusion, so we
can detect it here, and call the correct runtime function instead.
Signed-off-by: Pierrick Bouvier
---
include/exec/target_page.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/exec/target_page.h b/include/ex
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
target/alpha/cpu.h | 1 +
target/arm/cpu.h| 1 +
target/avr/cpu.h| 1 +
target/hppa/cpu.h | 1 +
target/i386/cpu.h | 1 +
target/loongarch/cpu.h | 1 +
target/m68k/
On 24/03/2025 19.58, Philippe Mathieu-Daudé wrote:
Both s390_cpu_list() and s390_set_qemu_cpu_model() are
defined in cpu_models.c, move their declarations in the
related "cpu_models.h" header. Use full path to header
in s390-virtio-ccw.c file.
Suggested-by: Thomas Huth
Signed-off-by: Philippe M
On 24/03/2025 20.04, Philippe Mathieu-Daudé wrote:
On 24/3/25 20:02, Richard Henderson wrote:
On 3/24/25 11:58, Philippe Mathieu-Daudé wrote:
Register s390_cpu_list() as CPUClass:list_cpus callback
and remove the cpu_list definition.
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/cp
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