The HACE models in AST2600 and AST2700 are nearly identical. Based on the
AST2600 test cases, new tests have been added for AST2700.
Implemented test functions for SHA-256, SHA-384, SHA-512, and MD5.
Added scatter-gather and accumulation test variants.
For AST2700, the HACE controller base address
Add the TCGCPUOps::guest_default_memory_order field and have
each target initialize it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Reviewed-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
---
include/accel/tcg/cpu-ops.h | 8
target/alpha/cpu.c | 2
+Igor
On 2025/3/21 下午2:47, Markus Armbruster wrote:
Bibo Mao writes:
In function virt_cpu_unplug(), it will send cpu unplug message to
interrupt controller extioi and ipi irqchip. If there is problem in
this function, system should continue to run and keep state the same
before cpu is remove
From: Zhu Yangyang
Calling qmp_block_set_io_throttle() will be blocked for a long time
when a network disk is configured and the network failure is just about
to occur.
Therefore, we add a timeout parameter for qmp_block_set_io_throttle to control
its execution duration.
The default value of ti
On 2025/3/21 下午2:47, Markus Armbruster wrote:
Bibo Mao writes:
In function virt_cpu_unplug(), it will send cpu unplug message to
interrupt controller extioi and ipi irqchip. If there is problem in
this function, system should continue to run and keep state the same
before cpu is removed.
I
The following changes since commit 1dae461a913f9da88df05de6e2020d3134356f2e:
Update version for v10.0.0-rc0 release (2025-03-18 10:18:14 -0400)
are available in the Git repository at:
https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-10.0-2-20250321
for you to fetch changes up to
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH for-10.1 13/32] vfio: Move VFIOAddressSpace helpers into
>container-base.c
>
>+John
>
>On 3/20/25 10:36, Duan, Zhenzhong wrote:
>>
>>
>>> -Original Message-
>>> From: Cédric Le Goater
>>> Subject: [PATCH for-10.1 1
Rather than use the hardcoded define throughout the tree for the
PNOR LPC address, keep it within the PnvPnor object.
This should solve a dead code issue in the BMC HIOMAP checks where
Coverity (correctly) reported that the sanity checks are dead code.
We would like to keep the sanity checks witho
From: Harsh Prateek Bora
When POWER10 CPU was made as default, we missed keeping POWER9 as
default for older pseries releases (pre-9.0) at that time.
This caused breakge in default cpu evaluation for older pseries
machines and hence this fix.
Fixes: 51113013f3 ("ppc/spapr: change pseries machine
On Thu, Mar 20, 2025 at 11:13:04AM -0700, Farhan Ali wrote:
> Hi,
>
> I have been experimenting with the QEMU Userspace NVMe driver on s390x
> architecture. I have noticed an issue when assigning multiple virtqueues and
> multiple iothreads to the block device. The driver works well with a single
Catch lseek errors. Return on read errors.
Fixes: CID 1593154
Fixes: CID 1593157
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Gerd Hoffmann
Message-ID: <20250319141159.1461621-4-kra...@redhat.com>
---
hw/uefi/var-service-json.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-
Allow the device being added to loongarch virt VMs.
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Gerd Hoffmann
Message-ID: <20250319141159.1461621-6-kra...@redhat.com>
---
hw/loongarch/virt.c | 2 ++
hw/uefi/Kconfig | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/
Catch lseek errors. Return on errors.
Use autoptr for the GString to simplify cleanup.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Gerd Hoffmann
Message-ID: <20250319141159.1461621-3-kra...@redhat.com>
---
hw/uefi/var-service-json.c | 15 +++
1 file changed, 11 insertions(+)
On 21.03.25 04:36, Ani Sinha wrote:
On Thu, Mar 20, 2025 at 7:24 PM Alexander Graf wrote:
Hey Gerd,
On 18.03.25 12:11, Gerd Hoffman wrote:
Hi,
Maybe not from the user's point of view, but surely for the vmfwupdate
interface design and for the launch measurement calculations.
When usi
From: Laurent Vivier
Add a chapter to explain how to use passt(1) instead of '-net user'.
passt(1) can be connected to QEMU using UNIX socket or vhost-user.
With vhost-user, migration of the VM is allowed and internal state of
passt(1) is transfered from one side to the other
Bug: https://gitlab
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH for-10.1 24/32] vfio: Introduce new files for dirty
>tracking
>definitions and declarations
>
>On 3/20/25 10:52, Duan, Zhenzhong wrote:
>>
>>
>>> -Original Message-
>>> From: Cédric Le Goater
>>> Subject: [PATCH f
On 21/03/25, Philippe Mathieu-Daudé wrote:
> We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled
> frontends, otherwise we use a default value of TCG_MO_ALL.
>
> In order to simplify, require the definition for all targets,
> defining it for hexagon, m68k, rx, sh4 and tricore.
>
> Signed-o
On 21/03/25, Philippe Mathieu-Daudé wrote:
> Now that TCG_GUEST_DEFAULT_MO is always defined,
> simplify the tcg_req_mo() macro.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> accel/tcg/internal-target.h | 9 +
> accel/tcg/tcg-all.c | 3 ---
> 2 files changed, 1 insertion(+),
On 21/3/25 15:39, Anton Johansson wrote:
On 21/03/25, Philippe Mathieu-Daudé wrote:
In order to use TCG with multiple targets, replace the
compile time use of TCG_GUEST_DEFAULT_MO by a runtime
access to tcg_ctx->guest_mo.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-target.h
The following changes since commit 1dae461a913f9da88df05de6e2020d3134356f2e:
Update version for v10.0.0-rc0 release (2025-03-18 10:18:14 -0400)
are available in the Git repository at:
https://repo.or.cz/qemu/armbru.git tags/pull-error-2025-03-21
for you to fetch changes up to a725bc970e3091
Allow the device being added to riscv virt VMs.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Gerd Hoffmann
Message-ID: <20250319141159.1461621-5-kra...@redhat.com>
---
hw/riscv/virt.c | 2 ++
hw/uefi/Kconfig | 2 +-
2 files changed, 3 insertions(+), 1 del
On Sun, 9 Mar 2025 at 10:35, Paolo Bonzini wrote:
>
> Generalize timer_and_addr() to decode all registers into a single enum
> HPETRegister, and use the TryInto derive to separate valid and
> invalid values.
>
> The main advantage lies in checking that all registers are enumerated
> in the "match"
We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled
frontends, otherwise we use a default value of TCG_MO_ALL.
In order to simplify, require the definition for all targets,
defining it for hexagon, m68k, rx, sh4 and tricore.
Signed-off-by: Philippe Mathieu-Daudé
---
target/hexagon/cpu-pa
Due to a missing "& 0x18", timer registers are not decoded correctly.
This breaks the tests/functional/test_x86_64_tuxrun.py functional
test.
Fixes: 519088b7cf6 ("rust: hpet: decode HPET registers into enums", 2025-03-06)
Reported-by: Peter Maydell
Signed-off-by: Paolo Bonzini
---
rust/hw/timer
On Fri, Mar 21, 2025 at 10:25:15AM +0100, Cédric Le Goater wrote:
> > > +struct vfio_info_cap_header *
> > > +vfio_get_region_info_cap(struct vfio_region_info *info, uint16_t id);
> >
> > This can be static in fact.
>
> It is used by vfio_device_get_region_info_type() and
> vfio_device_has_regio
Hi,
> I think if we want to embrace IGVM, we should embrace it fully and make it
> replace the region list. At the end of the day, IGVM is effectively a region
> list plus data.
>
> How difficult would it be to put up a prototype that uses only IGVM as
> vmfwupdate payload? We can definitely a
On 3/20/25 10:40, John Levon wrote:
On Tue, Mar 18, 2025 at 10:53:58AM +0100, Cédric Le Goater wrote:
Gather all helper routine declarations into "helpers.h" to reduce
exposure of VFIO internals in "hw/vfio/vfio-common.h".
Signed-off-by: Cédric Le Goater
Reviewed-by: John Levon
but
+str
v1:
1. Added support for 64-bit DMA in the HACE model
2. Refactored the do_hash operation in the HACE model
3. Fixed a crash caused by out-of-bound memory access in HACE
4. Added more trace events and implemented dumping of source hash data and
resulting digests to improve debugging
5. Ref
According to the AST2700 design, the data source address is 64-bit, with
R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0].
Similarly, the digest address is 64-bit, with R_HASH_DEST_HI storing bits
[63:32] and R_HASH_DEST storing bits [31:0].
Ideally, sg_addr should be 64-bit
Currently, the hash data source and digest result buffer addresses are set to
32-bit. However, the AST2700 CPU is a 64-bit Cortex-A35 architecture, and its
DRAM base address is also 64-bit.
To support AST2700, update the hash data source address and digest result buffer
address to use 64-bit addre
This cleanup follows significant changes in commit 4c1d0af4a28d, making the
model more readable.
- Deleted "iov_cache" and "iov_count" from "AspeedHACEState".
- Removed "reconstruct_iov" function and related logic.
- Simplified "do_hash_operation" by eliminating redundant checks.
Signed-off-by: J
The HACE model in AST2600 and AST1030 is identical. Referencing the AST2600
test cases, new tests have been created for AST1030.
Implemented test functions for SHA-256, SHA-384, SHA-512, and MD5.
Added scatter-gather and accumulation test variants.
For AST1030, the HACE controller base address sta
The test cases for the ASPEED HACE model were originally placed in
aspeed_hace-test.c. However, this test file only supports ARM32. To enable
compatibility with all ASPEED SoCs, including the AST2700, which uses the
AArch64 architecture, this update introduces a new source file,
aspeed-hace-utils.c
1. Disabled by default. Uncomment "#define DEBUG_HACE 1" to enable it.
2. Uses the "qemu_hexdump" API to dump the digest result.
3. Uses the "iov_hexdump" API to dump the source vector, which contains the
source plaintext.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 12
Introduced SHA-384 test functions to verify hashing operations.
Extended support for scatter-gather (`_sg`) and accumulation (`_accum`) tests.
Updated test result vectors for SHA-384 validation.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed-hace-utils.h | 6 ++
tests/qtest/aspeed-hace-utils.
Hi Cedric,
> Subject: [PATCH v1 02/22] hw/misc/aspeed_hace: Fix buffer overflow in
> has_padding function
>
> The maximum padding size is either 64 or 128 bytes and should always be
> smaller than "req_len". If "padding_size" exceeds "req_len", then "req_len -
> padding_size" underflows due to "u
Pierrick Bouvier writes:
> On 3/20/25 12:30, Pierrick Bouvier wrote:
>> On 3/19/25 11:22, Alex Bennée wrote:
>>> The current helper.h functions rely on hard coded assumptions about
>>> target endianess to use the tswap macros. We also end up double
>>> swapping a bunch of values if the target can
When cryptodev_lkcf_set_op_desc() fails, we report an error, but
continue anyway. This is wrong. We then pass a non-null @local_error
to various functions, which could easily fail error_setv()'s assertion
on failure.
Fail the function instead.
When qcrypto_akcipher_new() fails, we fail the func
On Tue, Mar 11 2025, Marc Zyngier wrote:
> On Tue, 11 Mar 2025 16:28:10 +,
> Cornelia Huck wrote:
>>
>> - I'm open to changing the source of the definitions from the sysregs
>> file to the JSON definitions published by Arm; however, I first wanted
>> to get the code using it right
On Tue, Mar 11 2025, Richard Henderson wrote:
> On 3/11/25 09:28, Cornelia Huck wrote:
>> From: Eric Auger
>>
>> This new header contains macros that define aarch64 registers.
>> In a subsequent patch, this will be replaced by a more exhaustive
>> version that will be generated from linux arch/
On 3/21/25 05:57, Philippe Mathieu-Daudé wrote:
In order to use TCG with multiple targets, replace the
compile time use of TCG_GUEST_DEFAULT_MO by a runtime
access to tcg_ctx->guest_mo.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-target.h | 4 +---
1 file changed, 1 insertio
On Thu, 2025-03-20 at 16:09 -0400, Stefan Hajnoczi wrote:
> On Thu, Mar 20, 2025 at 12:34 PM Miles Glenn wrote:
> > Hello,
> >
> > I am attempting to simulate a system with multiple CPU
> > architectures. To do this I am starting a unique QEMU process for each
> > CPU architecture that is needed
From: Bibo Mao
The Error ** argument must be NULL, &error_abort, &error_fatal, or a
pointer to a variable containing NULL. Passing an argument of the
latter kind twice without clearing it in between is wrong: if the
first call sets an error, it no longer points to NULL for the second
call.
virt_
The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor, and its DRAM
address space is also 64-bit. To support future AST2700 updates, the source
hash buffer address data type is being updated to 64-bit.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 8 +---
1 file changed, 5 i
From: Zhao Liu
The `size` field of the VMStateField with VMS_ARRAY_OF_POINTER flag
should stores the size of pointer, which depends on platform.
Currently, `*const`, `*mut`, `NonNull`, `Box<>` and their wrapper are
supported, and they have the same size as `usize`.
Store the size (of `usize`) w
On 3/21/25 11:34, Philippe Mathieu-Daudé wrote:
Use the OnOffAuto type as 3-state.
Since the TCGState instance is zero-initialized, the
mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO).
In tcg_init_machine(), if mttcg_enabled is still AUTO,
set a default value (effectively inlining the
de
From: Zhao Liu
The use of "bindings::*" masks incomplete path of VMStateFlags.
Include complete crate path of VMStateFlags in vmstate_clock, and clean
up "bindings::*" in device_class.rs of pl011.
Signed-off-by: Zhao Liu
Link: https://lore.kernel.org/r/20250318130219.1799170-16-zhao1@intel
From: Zhao Liu
Array type vmstate has the VMStateField with `num` equals its length.
When the varray vmstate is built based a array type, the `num` field
should be cleaned to 0, because varray uses `num_offset` instead of
`num` to store elements number information.
Signed-off-by: Zhao Liu
Link
From: Zhao Liu
`num_offset` is a member of `VMStateField`, and there's no need to use
"." to access this field in a `VMStateField` instance.
Signed-off-by: Zhao Liu
Link: https://lore.kernel.org/r/20250318130219.1799170-3-zhao1@intel.com
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/
From: Zhao Liu
At present, Rust side has a timer binding "timer::Timer", so the vmstate
for timer should base on that binding instead of the raw
"binding::QEMUTimer".
It's possible to apply impl_vmstate_transparent for cell::Opaque and
then impl_vmstate_forward for timer::Timer. But binding::QEM
On 3/20/25 15:29, Pierrick Bouvier wrote:
We introduce later a mechanism to skip cpu definitions inclusion, so we
can detect it here, and call the correct runtime function instead.
Signed-off-by: Pierrick Bouvier
---
include/exec/target_page.h | 3 +++
1 file changed, 3 insertions(+)
diff -
On 3/21/25 12:27, Richard Henderson wrote:
On 3/21/25 11:09, Pierrick Bouvier wrote:
Mmm, ok I guess. Yesterday I would have suggested merging this with
page-vary.h, but
today I'm actively working on making TARGET_PAGE_BITS_MIN a global constant.
When you mention this, do you mean "constant
On 21/03/25, Philippe Mathieu-Daudé wrote:
> Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition,
> have each target set the 'mttcg_supported' field in the TCGCPUOps
> structure.
>
> Since so far we only emulate one target architecture at a time,
> tcg_init_machine() gets whether MTT
From: Zhao Liu
Add a unit test to cover some patterns accepted by vmstate_of and
vmstate_struct macros, which correspond to the following C version
macros:
* VMSTATE_BOOL_V
* VMSTATE_U64
* VMSTATE_STRUCT_VARRAY_UINT8
* (no C version) MULTIPLY variant of VMSTATE_STRUCT_VARRAY_UINT32
* VMSTAT
This restores the linting baseline in qapidoc. The order of some imports
have changed slightly due to configuring isort a little better: isort
was having difficulty understanding that "compat" and "qapidoc_legacy"
were local modules because docs/sphinx "isn't a python package".
Signed-off-by: John
This restores the linting baseline in QAPI.
Signed-off-by: John Snow
---
scripts/qapi/backend.py | 2 ++
1 file changed, 2 insertions(+)
diff --git a/scripts/qapi/backend.py b/scripts/qapi/backend.py
index 14e60aa67af..49ae6ecdd33 100644
--- a/scripts/qapi/backend.py
+++ b/scripts/qapi/backend.
A few transitive dependencies were left floating; as a result, pip's
dependency solver can pull in newer dependencies, which we don't
want. Pin them down.
Signed-off-by: John Snow
---
python/tests/minreqs.txt | 4
1 file changed, 4 insertions(+)
diff --git a/python/tests/minreqs.txt b/pyth
Directly condition associated calls in target/arm/helper.c for now.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h| 8
target/arm/helper.c | 6 ++
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b1c3e463267..c1a0faed
From: Bibo Mao
Temporary variable ret is assigned at last line and return, it can
be removed and return directly.
Signed-off-by: Bibo Mao
Reviewed-by: Markus Armbruster
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250320032158.1762751-6-maob...@loongson.cn>
Signed-off-by: Markus Armbrus
The Error ** argument must be NULL, &error_abort, &error_fatal, or a
pointer to a variable containing NULL. Passing an argument of the
latter kind twice without clearing it in between is wrong: if the
first call sets an error, it no longer points to NULL for the second
call.
xen_bus_realize() is
xen_bus_realize() reports a failure to set up a watch as error, but it
doesn't treat it as one: it simply continues. Report a warning
instead.
Signed-off-by: Markus Armbruster
Message-ID: <20250314143500.2449658-3-arm...@redhat.com>
Reviewed-by: Stefano Stabellini
---
hw/xen/xen-bus.c | 7 +++-
On Thu, Mar 20 2025, Sebastian Ott wrote:
> On Tue, 11 Mar 2025, Cornelia Huck wrote:
>> +++ b/scripts/gen-cpu-sysregs-header.awk
> [...]
>> +BEGIN {
>> +print ""
>> +} END {
>> +print ""
>> +}
>> +
>> +# skip blank lines and comment lines
>> +/^$/ { next }
>> +/^[\t ]*#/ { next }
>> +
>>
On 3/21/25 11:05, Richard Henderson wrote:
On 3/20/25 15:29, Pierrick Bouvier wrote:
We introduce later a mechanism to skip cpu definitions inclusion, so we
can detect it here, and call the correct runtime function instead.
Signed-off-by: Pierrick Bouvier
---
include/exec/target_page.h | 3
From: Zhao Liu
The VMState type bound is not used in with_varray_flag().
And for vmstate_struct, Rust cannot infer the type of `num` from the
call_func_with_field(), so this causes the compiling error because it
complains "cannot satisfy `_: VMState`" in with_varray_flag().
Note Rust can infer
On 3/21/25 13:11, Pierrick Bouvier wrote:
On 3/21/25 12:27, Richard Henderson wrote:
On 3/21/25 11:09, Pierrick Bouvier wrote:
Mmm, ok I guess. Yesterday I would have suggested merging this with
page-vary.h, but
today I'm actively working on making TARGET_PAGE_BITS_MIN a global constant.
W
On 3/19/25 13:21, Joao Martins wrote:
On 18/03/2025 09:54, Cédric Le Goater wrote:
Rename these routines :
vfio_devices_all_device_dirty_tracking_started ->
vfio_dirty_tracking_devices_is_started_all
vfio_devices_all_dirty_tracking_started->
vfio_dirty_tracking_devices_is_starte
The pylint config is being left in place because the settings differ
enough from the python/ directory settings that we need a chit-chat on
how to merge them O:-)
Everything else can go.
Signed-off-by: John Snow
---
scripts/qapi/.flake8| 3 ---
scripts/qapi/.isort.cfg | 7 ---
scripts/q
On Fri, Mar 21, 2025 at 11:33:31AM +0530, Manish wrote:
> Hi Daniel, Peter,
>
> Please let me know if this latest patch looks good?
>
>
> On 17/03/25 7:22 am, Manish Mishra wrote:
> > We allocate extra metadata SKBs in case of a zerocopy send. This metadata
> > memory is accounted for in the OPT
Now that TCG_GUEST_DEFAULT_MO is always defined,
simplify the tcg_req_mo() macro.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Reviewed-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
---
accel/tcg/internal-target.h | 9 +
accel/tcg/tcg-all.c | 3 ---
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 2 --
linux-user/qemu.h | 3 +++
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index d2895fb55b1..74017a5ce7c 100644
--
On Fri, Mar 21, 2025 at 2:42 PM Marc-André Lureau <
marcandre.lur...@redhat.com> wrote:
> Hi
>
> On Fri, Mar 21, 2025 at 7:40 AM wrote:
> >
> > From: Hyman Huang
> >
> > Our goal is to migrate VMs that are configured with qemu-vdagent-typed
> > chardev while allowing the agent to continue workin
qemu_tcg_mttcg_enabled() is specific to 1/ TCG and
2/ system emulation. Move the prototype declaration
to "system/tcg.h", reducing 'mttcg_enabled' variable
scope.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 9 -
include/system/tcg.h | 8
accel/
Multi-threaded TCG only concerns system emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/tcg/tcg-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index fb903992faa..60a26acc503 100644
--- a/target/r
On 3/21/25 04:46, Alex Bennée wrote:
Pierrick Bouvier writes:
On 3/19/25 11:22, Alex Bennée wrote:
The aim of this work is to get rid of the endian aware helpers in
gdbstub/helpers.h which due to their use of tswap() mean target
gdbstubs need to be built multiple times. While this series does
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
Multi-threaded TCG only concerns system emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/tcg/tcg-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
qemu_tcg_mttcg_enabled() is specific to 1/ TCG and
2/ system emulation. Move the prototype declaration
to "system/tcg.h", reducing 'mttcg_enabled' variable
scope.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 9
Pierrick Bouvier writes:
> On 3/19/25 11:22, Alex Bennée wrote:
>> The aim of this work is to get rid of the endian aware helpers in
>> gdbstub/helpers.h which due to their use of tswap() mean target
>> gdbstubs need to be built multiple times. While this series doesn't
>> actually build each stu
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
target/ppc/mmu-hash64.h | 2 ++
target/i386/tcg/system/excp_helper.c | 1 +
target/i386/xsave_helper.c | 1 +
target/riscv/vector_helper.c
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
1 file changed, 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 3/21/25 04:36, Alex Bennée wrote:
Pierrick Bouvier writes:
On 3/20/25 12:30, Pierrick Bouvier wrote:
On 3/19/25 11:22, Alex Bennée wrote:
The current helper.h functions rely on hard coded assumptions about
target endianess to use the tswap macros. We also end up double
swapping a bunch of
Now that TCG_GUEST_DEFAULT_MO is always defined,
simplify the tcg_req_mo() macro.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-target.h | 9 +
accel/tcg/tcg-all.c | 3 ---
2 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/accel/tcg/internal-target.h b
On 3/20/25 15:29, Pierrick Bouvier wrote:
We include this header where needed. When includes set already have
ifdef CONFIG_USER_ONLY, we add it here, else, we don't condition the
include.
Signed-off-by: Pierrick Bouvier
---
hw/s390x/ipl.h | 1 +
include/exec/cpu-all.h
From: Peter Maydell
Currently we require everywhere that wants to know if there
is an HPET device to check for "CONFIG_HPET || CONFIG_X_HPET_RUST".
Factor out whether the HPET device is Rust or C into a separate
Kconfig stanza, so that CONFIG_HPET means "there is an HPET",
and whether this has pu
The following changes since commit 1dae461a913f9da88df05de6e2020d3134356f2e:
Update version for v10.0.0-rc0 release (2025-03-18 10:18:14 -0400)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to fetch changes up to 64acc23c9793e86f281134
On 21/03/2025 16.58, Peter Maydell wrote:
The arm_aspeed_bletchley timeout takes more than its
current 120s timeout on a debug Rust config:
$ time (cd build/rust; PYTHONPATH=../../python:../../tests/functional
QEMU_TEST_QEMU_BINARY=./qemu-system-arm ./pyvenv/bin/python3
../../tests/functional/
Add a new assertion that is similar to "const { assert!(...) }" but can be used
outside functions and with older versions of Rust. A similar macro is found in
Linux, whereas the "static_assertions" crate has a const_assert macro that
produces worse error messages.
Suggested-by: Peter Maydell
Sig
From: Zhao Liu
The vmstate has too many combinations of VMStateFlags and VMStateField.
Currently, the best way to test is to ensure that the Rust vmstate
definition is consistent with the (possibly corresponding) C version.
Add a unit test to cover some patterns accepted by vmstate_of macro,
whi
From: Zhao Liu
When pass a varray to vmstate_struct, the `type` parameter should be the
type of the element in the varray, for example:
vmstate_struct!(HPETState, timers, [0 .. num_timers], VMSTATE_HPET_TIMER,
BqlRefCell).with_version_id(0)
But this breaks current type check, be
Targets know whether they are big-endian more than they know if
the endianness is different from the host: the former is mostly
a constant, at least in machine creation code, while the latter
has to be computed with TARGET_BIG_ENDIAN != HOST_BIG_ENDIAN or
something like that.
load_aout, however, t
From: Zhao Liu
In C version, VMSTATE_VALIDATE accepts the function pointer, which is
used to check if some conditions of structure could meet, although the
C version macro doesn't accept any structure as the opaque type.
But it's hard to integrate VMSTATE_VALIDAE into vmstate_struct, a new
macro
From: Zhao Liu
The varry of structure created by vmstate_struct is different with
vmstate_of. This is because vmstate_struct uses the `vmsd` to traverse
the vmstates of structure's fields, rather than treating the structure
directly as a well-defined vmstate.
Therefore, there's no need to check
Due to a missing "& 0x18", timer registers are not decoded correctly.
This breaks the tests/functional/test_x86_64_tuxrun.py functional
test.
Fixes: 519088b7cf6 ("rust: hpet: decode HPET registers into enums", 2025-03-06)
Reported-by: Peter Maydell
Tested-by: Peter Maydell
Reviewed-by: Peter May
The arm_aspeed_bletchley timeout takes more than its
current 120s timeout on a debug Rust config:
$ time (cd build/rust; PYTHONPATH=../../python:../../tests/functional
QEMU_TEST_QEMU_BINARY=./qemu-system-arm ./pyvenv/bin/python3
../../tests/functional/test_arm_aspeed_bletchley.py)
TAP version 13
Facility interrupt checks in general should come after the ISA version
check, because the facility interrupt and facility type themselves are
ISA dependent and should not appear on CPUs where the instruction does
not exist at all.
This resolves a QEMU crash booting NetBSD/macppc due to
qemu: fa
On 21/03/25, Philippe Mathieu-Daudé wrote:
> In order to use TCG with multiple targets, replace the
> compile time use of TCG_GUEST_DEFAULT_MO by a runtime
> access to tcg_ctx->guest_mo.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> accel/tcg/internal-target.h | 4 +---
> 1 file changed, 1 i
On 21/3/25 13:57, Philippe Mathieu-Daudé wrote:
Add the TCGCPUOps::guest_default_memory_order field and have
each target initialize it.
Use it to set TCGContext::guest_mo in tb_gen_code(), removing
the need for the TCG_GUEST_DEFAULT_MO definition.
Signed-off-by: Philippe Mathieu-Daudé
---
in
On 3/21/25 05:57, Philippe Mathieu-Daudé wrote:
Now that TCG_GUEST_DEFAULT_MO is always defined,
simplify the tcg_req_mo() macro.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-target.h | 9 +
accel/tcg/tcg-all.c | 3 ---
2 files changed, 1 insertion(+), 11 del
On 3/21/25 05:57, Philippe Mathieu-Daudé wrote:
We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled
frontends, otherwise we use a default value of TCG_MO_ALL.
In order to simplify, require the definition for all targets,
defining it for hexagon, m68k, rx, sh4 and tricore.
Signed-off-by:
On 3/21/25 06:02, Philippe Mathieu-Daudé wrote:
On 20/3/25 21:16, Pierrick Bouvier wrote:
On 3/20/25 12:52, Pierrick Bouvier wrote:
On 3/19/25 11:22, Alex Bennée wrote:
The aim of this work is to get rid of the endian aware helpers in
gdbstub/helpers.h which due to their use of tswap() mean ta
On 3/21/25 05:57, Philippe Mathieu-Daudé wrote:
Add the TCGCPUOps::guest_default_memory_order field and have
each target initialize it.
Use it to set TCGContext::guest_mo in tb_gen_code(), removing
the need for the TCG_GUEST_DEFAULT_MO definition.
Signed-off-by: Philippe Mathieu-Daudé
---
in
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