RE: [PATCH 07/39] target/hexagon: Implement wait helper

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

Re: [RFC PATCH v2 03/20] hw/arm/smmuv3-accel: Add initial infrastructure for smmuv3-accel device

On Mon, Mar 17, 2025 at 07:07:52PM +0100, Eric Auger wrote: > On 3/17/25 6:54 PM, Nicolin Chen wrote: > > On Wed, Mar 12, 2025 at 04:15:10PM +0100, Eric Auger wrote: > >> On 3/11/25 3:10 PM, Shameer Kolothum wrote: > >>> Based on SMMUv3 as a parent device, add a user-creatable smmuv3-accel > >>> de

[PATCH 7/9] cxl-mailbox-utils: 0x5603 - FMAPI Get DC Region Extent Lists

From: Anisa Su FM DCD Management command 0x5603 implemented per CXL r3.2 Spec Section 7.6.7.6.4 Very similar to previously implemented command 0x4801. Signed-off-by: Anisa Su --- hw/cxl/cxl-mailbox-utils.c | 84 ++ 1 file changed, 84 insertions(+) diff --gi

RE: [PATCH 19/39] target/hexagon: Implement hexagon_tlb_fill()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 20/39] target/hexagon: Implement siad inst

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 24/39] target/hexagon: Add exec-start-addr prop

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:29 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 25/39] target/hexagon: Add hexagon_cpu_mmu_index()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:29 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 26/39] target/hexagon: Decode trap1, rte as COF

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:29 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 28/39] target/hexagon: Implement modify_ssr, resched, pending_interrupt

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:29 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 29/39] target/hexagon: Add pkt_ends_tb to translation

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:29 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

Re: [RFC PATCH v2 03/20] hw/arm/smmuv3-accel: Add initial infrastructure for smmuv3-accel device

On Mon, Mar 17, 2025 at 04:24:53PM -0300, Jason Gunthorpe wrote: > On Mon, Mar 17, 2025 at 12:10:19PM -0700, Nicolin Chen wrote: > > Another question: how does an emulated device work with a vSMMUv3? > > I could imagine that all the accel steps would be bypassed since > > !sdev->idev. Yet, the emul

[PATCH v6 16/18] include/exec/memory: move devend functions to memory-internal.h

Only system/physmem.c and system/memory.c use those functions, so we can move then to internal header. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- include/exec/memory-internal.h | 19 +++ include/exec/memory.h | 18 -- 2 files chan

[PATCH v6 13/18] system/xen: remove inline stubs

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Pierrick Bouvier --- include/system/xen-mapcache.h | 41 --- include/system/xen.h | 21 +++--- 2 files changed, 3 insertions(+), 59 deletions(-) diff --git a/include/system/xen-mapcache.h b/i

[PATCH v6 05/18] exec/memory.h: make devend_memop "target defines" agnostic

Will allow to make system/memory.c common later. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- include/exec/memory.h | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index da21e9150b5..069021

[PATCH v6 12/18] hw/xen: add stubs for various functions

Those symbols are used by system/physmem.c, and are called only if xen_enabled() (which happens only if CONFIG_XEN is set and xen is available). So we can crash the stubs in case those are called, as they are linked only when CONFIG_XEN is not set. Acked-by: Richard Henderson Reviewed-by: Anthon

[PATCH v6 11/18] exec/ram_addr: call xen_hvm_modified_memory only if xen is enabled

Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- include/exec/ram_addr.h | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index f5d574261a3..92e8708af76 100644 --- a/include/exec/ram_addr.h +++ b/inclu

RE: [PATCH 09/39] target/hexagon: Implement arch_get_system_reg()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 15/39] target/hexagon: Implement hex_tlb_entry_get_perm()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 14/39] target/hexagon: Add system event, cause codes

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 08/39] target/hexagon: Implement get_exe_mode()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

Re: [RFC PATCH v2 03/20] hw/arm/smmuv3-accel: Add initial infrastructure for smmuv3-accel device

On Mon, Mar 17, 2025 at 12:10:19PM -0700, Nicolin Chen wrote: > Another question: how does an emulated device work with a vSMMUv3? > I could imagine that all the accel steps would be bypassed since > !sdev->idev. Yet, the emulated iotlb should cache its translation > so we will need to flush the io

RE: [PATCH 10/39] target/hexagon: Implement arch_{s, g}et_{thread, system}_reg()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 11/39] target/hexagon: Add representation to count cycles

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

[PATCH 9/9] cxl-mailbox-utils: 0x5605 - FMAPI Initiate DC Release

From: Anisa Su FM DCD Managment command 0x5605 implemented per CXL r3.2 Spec Section 7.6.7.6.6 Signed-off-by: Anisa Su --- hw/cxl/cxl-mailbox-utils.c | 94 ++ 1 file changed, 94 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-util

[PATCH 2/9] cxl-mailbox-utils: 0x5600 - FMAPI Get DCD Info

From: Anisa Su FM DCD Management command 0x5600 implemented per CXL 3.2 Spec Section 7.6.7.6.1 Signed-off-by: Anisa Su --- hw/cxl/cxl-mailbox-utils.c | 67 ++ hw/cxl/i2c_mctp_cxl.c | 6 +++- 2 files changed, 72 insertions(+), 1 deletion(-) diff --git

[PATCH 5/9] cxl_events.h: move definition for dynamic_capacity_uuid and enum for DC event types

From: Anisa Su move definition for dynamic_capacity_uuid and enum for DC event types to cxl_events.h from cxl_type3.c for shared use in next patch Signed-off-by: Anisa Su --- hw/mem/cxl_type3.c | 15 --- include/hw/cxl/cxl_events.h | 15 +++ 2 files changed, 15

[PATCH 0/9] CXL: FMAPI DCD Management Commands 0x5600-0x5605

From: Anisa Su This patchset adds support for 6 FM API DCD Management commands (0x5600-0x5605) according to the CXL r3.2 Spec. It is based on the following branch: https://gitlab.com/jic23/qemu/-/tree/cxl-2025-02-20. The code was tested with libcxlmi, which runs in the QEMU VM and sends 56xxh co

[PATCH 4/9] cxl-mailbox-utils: 0x5601 - FMAPI Get Host Region Config

From: Anisa Su FM DCD Management command 0x5601 implemented per CXL r3.2 Spec Section 7.6.7.6.2 Signed-off-by: Anisa Su --- hw/cxl/cxl-mailbox-utils.c | 97 ++ 1 file changed, 97 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-uti

[PATCH 1/9] cxl/type3: Add supported block sizes bitmask to CXLDCRegion struct

From: Anisa Su Add supported_blk_size field to CXLDCRegion struct in preparation for next patch. It is needed by command 0x5600 Get DC Region Config. Signed-off-by: Anisa Su --- hw/mem/cxl_type3.c | 3 +++ include/hw/cxl/cxl_device.h | 1 + 2 files changed, 4 insertions(+) diff --git

[PATCH 8/9] cxl-mailbox-utils: 0x5604 - FMAPI Initiate DC Add

From: Anisa Su FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section 7.6.7.6.5 Signed-off-by: Anisa Su --- hw/cxl/cxl-mailbox-utils.c | 173 hw/mem/cxl_type3.c | 8 +- include/hw/cxl/cxl_device.h | 4 + 3 files changed, 181 in

[PATCH 6/9] cxl-mailbox-utils: 0x5602 - FMAPI Set DC Region Config

From: Anisa Su FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section 7.6.7.6.3 Signed-off-by: Anisa Su --- hw/cxl/cxl-mailbox-utils.c | 100 +++ hw/mem/cxl_type3.c | 2 +- include/hw/cxl/cxl_device.h | 3 ++ include/hw/cxl/cxl_m

[PATCH 3/9] cxl/type3: Add dsmas_flags to CXLDCRegion struct

From: Anisa Su Add dsmas_flags field to DC Region struct in preparation for next command, which returns the dsmas flags in the response. Signed-off-by: Anisa Su --- hw/mem/cxl_type3.c | 2 ++ include/hw/cxl/cxl_device.h | 1 + 2 files changed, 3 insertions(+) diff --git a/hw/mem/cxl_

[PATCH for-10.1 2/9] gdbstub: Allow gdb_core_xml_file to be set at runtime

Currently the CPUClass:gdb_core_xml_file setting is a simple 'const char *' which the CPU class must set to a fixed string. Allow the CPU class to instead set a new method gdb_get_core_xml_file() which returns this string. This will allow Arm CPUs to use different XML files for AArch32 vs AArch64

Re: [PATCH v6 13/18] system/xen: remove inline stubs

On 3/17/25 11:34, Pierrick Bouvier wrote: Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Pierrick Bouvier --- include/system/xen-mapcache.h | 41 --- include/system/xen.h | 21 +++--- 2 files changed, 3 insertions(+), 59 deletions(-)

RE: [PATCH 27/39] target/hexagon: Implement hexagon_find_last_irq()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:29 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

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