Richard Henderson writes:
> These expand inline to the *_mmuidx_ra api with
> a lookup of the target's cpu_mmu_index().
>
> Signed-off-by: Richard Henderson
This is where my re-based bisect broke. Fixed by moving cpu.h
modified target/ppc/tcg-excp_helper.c
@@ -19,6 +19,7 @@
#include "qemu/o
On 11/03/25 10:41, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
Add the MDST, MDDT, MDRT tables offsets and structures as per current
skiboot upstream:
commit bc7b85db1e7e ("opal-ci: Remove centos7")
These structures will be later populated when preserving memory reg
With Machine Mode Lockdown (mseccfg.MML) set and RLB not set, checks on pmpcfg
writes would match the wrong cases of Smepmp truth table.
The existing code allows writes for the following cases:
- L=1, X=0: cases 8, 10, 12, 14
- L=0, RWX!=WX: cases 0-2, 4-6
This leaves cases 3, 7, 9, 11, 13, 15 for
Signed-off-by: Loïc Lefort
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/pmp.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index e1e5ca589e..7d65dc24a5 100644
--- a/target/riscv/pmp.c
+++ b/target/ri
On 3/13/25 11:47, ltaylorsimp...@gmail.com wrote:
What we are trying to model is an instance of a Hexagon that has a number of
threads and some resources that are shared. The shared resources include the
TLB and global S registers. The initial thought was to tie the shared
resources to the t
On Thu, Mar 13, 2025 at 2:30 PM Markus Armbruster wrote:
> John Snow writes:
>
> > On Thu, Mar 13, 2025, 11:57 AM Markus Armbruster
> wrote:
> >
> >> John Snow writes:
> >>
> >> > On Thu, Mar 13, 2025 at 10:41 AM Markus Armbruster >
> >> > wrote:
> >> >
> >> >> John Snow writes:
> >> >>
> >>
Use vaddr only for the newest api, because it has the least
number of uses and therefore is the easiest to audit.
Signed-off-by: Richard Henderson
---
accel/tcg/atomic_template.h | 16 ++---
include/exec/cpu_ldst.h | 48 ++---
accel/tcg/cputlb.c
Remove useless check in pmp_is_locked, the function will return 0 in either
case.
Signed-off-by: Loïc Lefort
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/pmp.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 845915e0c8..c685f7f2c5 1
Signed-off-by: Loïc Lefort
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/pmp.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index c5f6cdaccb..845915e0c8 100644
--- a/target/riscv/pmp.c
+++ b/target/ris
On Thu, Mar 13, 2025 at 06:13:24PM +0530, Prasad Pandit wrote:
> +int qemu_savevm_state_postcopy_prepare(QEMUFile *f)
> +{
> +int ret = 0;
> +SaveStateEntry *se;
> +
> +QTAILQ_FOREACH(se, &savevm_state.handlers, entry) {
> +if (strcmp(se->idstr, "ram")) {
> +continue
On 3/12/25 20:45, Richard Henderson wrote:
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them. The inlines
for user-only are unused.
Signed-off-by: Richard Henderson
---
include/hw/intc/armv7m_nvic.h | 14 --
1 file changed, 14 deleti
On 3/12/25 20:45, Richard Henderson wrote:
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them.
Signed-off-by: Richard Henderson
---
include/hw/s390x/css.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/s390x/css.h b/include/hw/s39
On 3/12/25 20:45, Richard Henderson wrote:
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
include/system/ram_addr.h | 2 +-
include/{exec => system}/ramblock.h | 9 -
hw/display/virtio-gpu-udmabuf.c | 2 +-
hw/hyperv/hv-balloon.c
On 3/12/25 20:45, Richard Henderson wrote:
Many of the headers used by these require CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
hw/core/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/core/meson.build b/hw/core/meson.build
index b5a545a0ed..
On 3/12/25 20:45, Richard Henderson wrote:
While RISCVCPUConfig.satp_mode is unused for user-only,
this header is used from disas/riscv.h, whose users are
only built once. The savings of 4 bytes isn't worth it.
Signed-off-by: Richard Henderson
---
target/riscv/cpu_cfg.h | 2 --
1 file chang
Implement the register command of "ibm,configure-kernel-dump" RTAS call.
The register just verifies the structure of the fadump memory structure
passed by kernel, and set fadump_registered in spapr state to true.
We also store the passed fadump memory structure, which will later be
used for preser
On 3/12/25 20:45, Richard Henderson wrote:
This is include/system, so CONFIG_USER_ONLY will never be true.
Some build configurations have this symbol missing.
https://github.com/pbo-linaro/qemu-ci/actions/runs/13826820446
Signed-off-by: Richard Henderson
---
include/system/cpu-timers.h |
These patches fix Smepmp implementation to make it compliant with the spec.
First patch limits RLB to CSR changes since RLB should not affect privilege
evaluation. Patch 2 extracts some common code into a function (to be used in
patch 3). Patch 3 fixes validation of pmpcfg CSR writes in order to m
On 3/12/25 20:45, Richard Henderson wrote:
While setup_post and has_memory will not be used for
CONFIG_USER_ONLY, let the struct have constant layout.
Signed-off-by: Richard Henderson
---
include/qemu/accel.h | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/incl
On 3/12/25 20:44, Richard Henderson wrote:
While some of these files are built exactly once, due
to being in only libuser_ss or libsystem_ss, some of
the includes that they depend on require CONFIG_USER_ONLY.
So make use of the common infrastructure to allow that.
Signed-off-by: Richard Henderso
On 3/13/25 10:11, Pierrick Bouvier wrote:
-uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
- int mmu_idx, uintptr_t ra);
Not related to the change, but the naming _ra is very confusing, since it means the
opposite of what it seems. *NO* requirement al
On 11/03/25 10:48, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
When MPIPL is used, OPAL/Linux registers memory regions to be preserved
on a Memory-Preserving boot ('crashkernel boot').
The regions are added to two tables: MDST and MDDT (source and
destination tables)
The
Richard Henderson writes:
> CONFIG_USER_ONLY == !CONFIG_SYSTEM_ONLY.
> Therefore it's cleaner to just add to user_ss.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Thu, Mar 13, 2025, 11:57 AM Markus Armbruster wrote:
> John Snow writes:
>
> > On Thu, Mar 13, 2025 at 10:41 AM Markus Armbruster
> > wrote:
> >
> >> John Snow writes:
> >>
> >> > On Thu, Mar 13, 2025 at 2:47 AM Markus Armbruster
> wrote:
> >> >
> >> >> John Snow writes:
> >> >>
> >> >> >
On 3/12/25 20:44, Richard Henderson wrote:
We assert that env immediately follows CPUState in cpu-all.h.
Change the offsetof expressions to be based on CPUState instead
of ArchCPU.
Nice change.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 13
The idea of adding a timeout parameter sounds good to me.
I think it's safe to call bdrv_drained_end() after the timeout fails,
but I'm not 100% sure. Maybe Kevin has thoughts on this.
I left comments on the patches.
Stefan
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Those functions are used by system/physmem.c, and are called only if
xen is enabled (which happens only if CONFIG_XEN is not set).
So we can crash in case those are called.
Acked-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/xen/xen_stubs.c | 56 +
Richard Henderson writes:
> Convert the existing includes with sed.
>
> Signed-off-by: Richard Henderson
> ---
> include/{exec => system}/ram_addr.h | 7 +++
> accel/kvm/kvm-all.c | 2 +-
> accel/tcg/cputlb.c | 2 +-
> accel/tcg/translate-all.c | 2
On 3/12/25 20:44, Richard Henderson wrote:
Split out the *_mmu api, which no longer uses
target specific argument types.
Signed-off-by: Richard Henderson
---
include/exec/cpu-ldst-common.h | 122 +
include/exec/cpu_ldst.h| 108 +
Only system/physmem.c and system/memory.c use those functions, so we can
move then to internal header.
Signed-off-by: Pierrick Bouvier
---
include/exec/memory-internal.h | 19 +++
include/exec/memory.h | 18 --
2 files changed, 19 insertions(+), 18 deleti
On 3/12/25 20:44, Richard Henderson wrote:
These expand inline to the *_mmuidx_ra api with
a lookup of the target's cpu_mmu_index().
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 144 +---
accel/tcg/ldst_common.c.inc | 108
On 3/12/25 20:44, Richard Henderson wrote:
These expand inline to the *_data_ra api with ra == 0.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 123 ++--
accel/tcg/ldst_common.c.inc | 89 --
2 files changed, 104 i
On 3/13/25 09:39, Pierrick Bouvier wrote:
Only system/physmem.c and system/memory.c use those functions, so we can
move then to internal header.
Signed-off-by: Pierrick Bouvier
---
include/exec/memory-internal.h | 19 +++
include/exec/memory.h | 18 --
On 3/12/25 20:44, Richard Henderson wrote:
These expand inline to the *_mmu api with a lookup of
the target's cpu_mmu_index() and ra == 0.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 31 +++
accel/tcg/cputlb.c | 28 -
On 3/12/25 20:44, Richard Henderson wrote:
These expand inline to the *_mmu api with trivial
massaging of the arguments.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 163
accel/tcg/ldst_common.c.inc | 118 --
On 3/12/25 20:44, Richard Henderson wrote:
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
hw/display/vga_int.h | 2 +-
include/hw/char/parallel-isa.h| 2 +-
include/hw/dma/i8257.h| 2 +-
include/hw/ide/ide-bus.h | 2 +-
i
On 13/3/25 19:05, Richard Henderson wrote:
On 3/13/25 09:59, Pierrick Bouvier wrote:
+static inline int
+cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra);
For my person
John Snow writes:
> On Thu, Mar 13, 2025, 11:57 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > On Thu, Mar 13, 2025 at 10:41 AM Markus Armbruster
>> > wrote:
>> >
>> >> John Snow writes:
>> >>
>> >> > On Thu, Mar 13, 2025 at 2:47 AM Markus Armbruster
>> >> > wrote:
>> >> >
>> >>
On 3/13/25 10:46, Pierrick Bouvier wrote:
On 3/12/25 20:44, Richard Henderson wrote:
Copy to libuser_ss and libsystem_ss.
This file uses semihosting/semihost.h, which has separate
implementations with and without CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
gdbstub/meson.build | 4
On Thu, 13 Mar 2025 at 07:16, Akihiko Odaki wrote:
>
> PMCNTENCLR_EL0 and PMINTENCLR_EL1 clears written bits so we need an
> alternative raw write functions, which will be used to copy KVM kernel
> coprocessor state into userspace.
>
> Signed-off-by: Akihiko Odaki
> ---
> target/arm/helper.c | 6
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
system/ioport.c| 1 -
system/meson.build | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/system/ioport.c b/system/ioport.c
index 55c2a752396..89daae9d602 100644
--- a/system/ioport.c
+++ b/system/ioport.
Needed so compilation units including it can be common.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/memory-internal.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
index 100c1237ac2..b729f
Defining functions allows to use them from common code, by not depending
on TARGET_BIG_ENDIAN.
Remove previous macros from exec/cpu-all.h.
By moving them out of cpu-all.h, we'll be able to break dependency on
cpu.h for memory related functions coming in next commits.
Reviewed-by: Richard Henderson
Will allow to make system/memory.c common later.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/memory.h | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index da21e9150b5..069021
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
system/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/system/meson.build b/system/meson.build
index eec07a94513..bd82ef132e7 100644
--- a/system/meson.build
+++ b/system/meson.build
@@ -3,7 +3,6 @
we'll use it in system/memory.c.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/memory.h | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 069021ac3ff..70177304a92 100644
-
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
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On 3/12/25 20:44, Richard Henderson wrote:
These expand inline to the *_mmu api with trivial
massaging of the arguments.
I hope they feel relaxed after that :).
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 163
accel/tcg/ldst_com
The following changes since commit 825b96dbcee23d134b691fc75618b59c5f53da32:
Merge tag 'migration-20250310-pull-request' of
https://gitlab.com/farosas/qemu into staging (2025-03-11 09:32:07 +0800)
are available in the Git repository at:
https://repo.or.cz/qemu/kevin.git tags/for-upstream
f
Hi,
patch 12 (adding xen stubs, so would need someone from hw/xen) and 15
are missing reviews.
Thanks,
Pierrick
On 3/13/25 09:38, Pierrick Bouvier wrote:
The main goal of this series is to be able to call any memory ld/st function
from code that is *not* target dependent. As a positive side
Needed so compilation units including it can be common.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/ram_addr.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index e4c28fbec9b..f5d574261
On 3/12/25 20:44, Richard Henderson wrote:
Use vaddr only for the newest api, because it has the least
number of uses and therefore is the easiest to audit.
Signed-off-by: Richard Henderson
---
accel/tcg/atomic_template.h | 16 ++---
include/exec/cpu_ldst.h | 48 +
On 3/12/25 20:44, Richard Henderson wrote:
Perform aligned atomic reads in translator_ld, if possible.
According to
https://lore.kernel.org/qemu-devel/20240607101403.1109-1-jim@sifive.com/
this is required for RISC-V Ziccif.
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c |
Steve Sistare writes:
> Fix bugs where the realize method re-initializes some memory regions during
> CPR. See the individual commit messages for details.
>
> Steve Sistare (4):
> migration: cpr_is_incoming
> pflash: fix cpr
> hw/loader: fix roms during cpr
> hw/qxl: fix cpr
>
> hw/bloc
On 3/12/25 20:44, Richard Henderson wrote:
The mmap_lock is user-only, whereas watchpoint.c
is only compiled for system mode.
Signed-off-by: Richard Henderson
---
accel/tcg/watchpoint.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c
inde
On 3/13/25 09:59, Pierrick Bouvier wrote:
+static inline int
+cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra);
For my personal culture, is that strictly equivalent to d
On 3/12/25 20:44, Richard Henderson wrote:
Split out mmap_lock, et al from page-protection.h
to a new header.
Signed-off-by: Richard Henderson
---
accel/tcg/internal-target.h| 1 +
include/exec/mmap-lock.h | 33 +
include/exec/page-protection.h | 2
On 3/12/25 20:44, Richard Henderson wrote:
Convert the existing includes with
sed -i ,exec/memory.h,system/memory.h,g
Move the include within cpu-all.h into a !CONFIG_USER_ONLY block.
Signed-off-by: Richard Henderson
---
hw/arm/strongarm.h| 2 +-
hw/display/apple
On 3/12/25 20:44, Richard Henderson wrote:
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
hw/net/i82596.h | 2 +-
hw/s390x/ipl.h| 2 +-
include/hw/misc/lasi.h| 2 +-
include/hw/nubus/nub
On 3/12/25 20:44, Richard Henderson wrote:
Add a new family of translator load functions which take
an absolute endianness value in the form of MO_BE/MO_LE.
Expand the other translator_ld* functions on top of this.
Remove exec/tswap.h from translator.c.
Is there a need further down the road to
On 3/12/25 20:44, Richard Henderson wrote:
Cache the mmu index in DisasContextBase.
Perform the read on host endianness, which lets us
share code with the translator_ld fast path.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 1 +
accel/tcg/translator.c| 57 ++
On 3/12/25 20:44, Richard Henderson wrote:
We already have two subdirectories for which we need
to build files twice, for user vs system modes.
Move this handling to the top level.
This cannot be combined with user_ss or system_ss,
because the formulation has not been extended to support
configu
Hey Alex,
On Thu, Mar 13, 2025 at 05:30:30PM +0100, Alexander Graf wrote:
> I have a few concerns with IGVM:
>
> 1) Parsing is non-trivial. Parsing them in QEMU may open security issues.
There is an IGVM parsing library under MIT license and written in Rust
with C-bindings. The currently propose
On 3/12/25 20:44, Richard Henderson wrote:
Copy to libuser_ss and libsystem_ss.
This file uses semihosting/semihost.h, which has separate
implementations with and without CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
gdbstub/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 d
On 13/3/25 17:36, Pierrick Bouvier wrote:
On 3/12/25 20:44, Richard Henderson wrote:
All this is working toward building accel/tcg/translator.c once,
but it got late and I decided to stop at a convenient milestone.
In the process, I discovered that we have already added files to
common_ss which
On Thu, Mar 13, 2025 at 06:38:44PM +0100, Jörg Rödel wrote:
> Hey Alex,
>
> On Thu, Mar 13, 2025 at 05:30:30PM +0100, Alexander Graf wrote:
> > I have a few concerns with IGVM:
> >
> > 1) Parsing is non-trivial. Parsing them in QEMU may open security issues.
>
> There is an IGVM parsing library
Saanjh Sengupta writes:
> Hi,
>
> What we are trying to achieve is that the QEMU should run for a particular
> number of instructions, let's say for example
> 1 instructions and then pause it's emulation. After a resume trigger is
> received to the QEMU it must resume it's
> emulation and s
Hi Harsh,
Thank you for the reviews.
On 11/03/25 10:08, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
During MPIPL (aka fadump), OPAL triggers the S0 SBE interrupt to trigger
MPIPL.
Currently QEMU treats it as "Unimplemented", handle the interrupts by
just logging that th
On 11/03/25 10:15, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
<...snip...>
diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c
index 62c94a04a2df..a6bf13650f2d 100644
--- a/hw/ppc/pnv_sbe.c
+++ b/hw/ppc/pnv_sbe.c
@@ -21,6 +21,8 @@
#include "qapi/error.h"
#include "qemu/
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Wednesday, March 12, 2025 6:40 PM
> To: Brian Cain ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; quic_mathb...@quicinc.com;
> a...@rev.ng; a...@rev.ng; quic_mlie...@quicinc.com;
> ltaylorsimp...@gmail.com; alex.be
On 11/03/25 10:20, Harsh Prateek Bora wrote:
<...snip...>
--- a/hw/ppc/pnv_sbe.c
+++ b/hw/ppc/pnv_sbe.c
@@ -82,6 +82,8 @@
#define SBE_CONTROL_REG_S0 PPC_BIT(14)
#define SBE_CONTROL_REG_S1 PPC_BIT(15)
+static uint64_t mpipl_skiboot_base = 0x3000 /*default
S
On 3/13/25 09:22, Alex Bennée wrote:
Richard Henderson writes:
These expand inline to the *_mmuidx_ra api with
a lookup of the target's cpu_mmu_index().
Signed-off-by: Richard Henderson
This is where my re-based bisect broke. Fixed by moving cpu.h
modified target/ppc/tcg-excp_helper.c
@
When Smepmp is supported, mseccfg.RLB allows bypassing locks when writing CSRs
but should not affect interpretation of actual PMP rules.
This is not the case with the current implementation where pmp_hart_has_privs
calls pmp_is_locked which implements mseccfg.RLB bypass.
This commit implements th
On 3/13/25 02:58, Philippe Mathieu-Daudé wrote:
On 13/3/25 04:44, Richard Henderson wrote:
Split out mmap_lock, et al from page-protection.h
to a new header.
Signed-off-by: Richard Henderson
---
accel/tcg/internal-target.h | 1 +
include/exec/mmap-lock.h | 33 +
On 3/12/25 20:45, Richard Henderson wrote:
Some of the headers used require CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
system/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/system/meson.build b/system/meson.build
index c83d80fa24..2aab3e97f4 1
On 3/13/25 10:14, Pierrick Bouvier wrote:
+#ifdef CONFIG_ATOMIC64
+ case 8:
+ if (QEMU_IS_ALIGNED(pc, 8)) {
+ uint64_t t = qatomic_read__nocheck((uint64_t *)host);
+ stl_he_p(dest, t);
Should it be stq_he_p?
Good eyes, thanks.
This would have only appeared as d
On 3/13/25 10:21, Pierrick Bouvier wrote:
On 3/12/25 20:44, Richard Henderson wrote:
uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, vaddr pc)
{
- uint64_t raw, tgt;
+ uint64_t val;
- if (translator_ld(env, db, &raw, pc, sizeof(raw))) {
- tgt = tswap64(raw);
On 2025/3/13 下午6:32, Markus Armbruster wrote:
Bibo Mao writes:
There is NULL pointer checking function error_propagate() already,
it is not necessary to add checking for function parameter. Here remove
NULL pointer checking with function parameter.
Signed-off-by: Bibo Mao
---
hw/loongar
On Thu Mar 13, 2025 at 8:49 PM AEST, Philippe Mathieu-Daudé wrote:
> On 13/3/25 07:13, Thomas Huth wrote:
>> On 13/03/2025 03.34, Stefan Hajnoczi wrote:
>>> On Tue, Mar 11, 2025 at 8:59 PM Nicholas Piggin
>>> wrote:
The following changes since commit
825b96dbcee23d134b691fc75618b5
On Sat, Mar 08, 2025 at 06:16:18PM +0800, zoudongjie wrote:
> From: Zhu Yangyang
>
> bdrv_drained_begin() is blocked for a long time when network storage is used
> and the network link has just failed.
> Therefore, the timeout period is set here.
>
> Signed-off-by: Zhu Yangyang
> ---
> block/b
Retrieve peer hashing capability instead of hardcoding.
Signed-off-by: Akihiko Odaki
---
include/hw/virtio/virtio-net.h | 5 ++-
hw/net/virtio-net.c| 71 ++
net/vhost-vdpa.c | 4 +--
3 files changed, 64 insertions(+), 16 deletio
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
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Description: PGP signature
Move virtio_net_get_features() to the later part of the file so that
it can call other functions.
Signed-off-by: Akihiko Odaki
---
hw/net/virtio-net.c | 146 ++--
1 file changed, 73 insertions(+), 73 deletions(-)
diff --git a/hw/net/virtio-net.c b
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Missing "i" in "mssing" in the subject.
On 12/03/2025 20.03, Alex Bennée wrote:
I could have sworn I had this is a previous iteration of the patches
but I guess it got lost in a re-base. As we are going to call
vulkaninfo to probe for "bad" drivers we need to skip if the binary
isn't available
eBPF RSS virtio-net support was written in assumption that there is only
one alternative RSS implementation: 'in-qemu' RSS. It is no longer true,
and we now have yet another implementation; namely the peer RSS.
Signed-off-by: Akihiko Odaki
---
docs/devel/ebpf_rss.rst | 23 ---
nclr_write },
+ .writefn = pmintenclr_write,
+ .raw_writefn = raw_write },
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_R,
---
base-commit: 825b96dbcee23d134b691fc75618b59c5f53da32
change-id: 20250313-cl
On 13/03/2025 08.13, Thomas Huth wrote:
Missing "i" in "mssing" in the subject.
On 12/03/2025 20.03, Alex Bennée wrote:
I could have sworn I had this is a previous iteration of the patches
but I guess it got lost in a re-base. As we are going to call
vulkaninfo to probe for "bad" drivers we ne
On Mon, 10 Mar 2025 16:23:35 +
Alireza Sanaee wrote:
> Add cache topology to PPTT table. With this patch, both ACPI PPTT table
> and device tree will represent the same cache topology given users
> input.
>
> Signed-off-by: Alireza Sanaee
> Co-developed-by: Jonathan Cameron
> Signed-off-by
This patch set solves errors reported by coccinelle tool with commands:
spatch --sp-file scripts/coccinelle/*.cocci --dir target/loongarch/
spatch --sp-file scripts/coccinelle/*.cocci --dir hw/loongarch/
The main problem is that qemu should fail to run when feature is forced
to enabled however
Temporary variable ret is assigned at last line and return, it can
be removed and return directly.
Signed-off-by: Bibo Mao
---
target/loongarch/tcg/tlb_helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c
b/target/loongarch/tcg/tlb_
For some paravirt KVM features, if user forces to enable it however
KVM does not support, qemu should fail to run. Here set error message
and return directly in function kvm_arch_init_vcpu().
Signed-off-by: Bibo Mao
---
target/loongarch/kvm/kvm.c | 4
1 file changed, 4 insertions(+)
diff -
The tests have been converted to the functional framework, so
we should not talk about Avocado here anymore.
Fixes: f7d6b772200 ("tests/functional: Convert BananaPi tests to the functional
framework")
Fixes: 380f7268b7b ("tests/functional: Convert the OrangePi tests to the
functional framework")
On Mon, 10 Mar 2025 16:23:34 +
Alireza Sanaee wrote:
> Prepare to update `build_pptt` function to add cache description
> functionalities, thus add binaries in this patch.
>
> Signed-off-by: Alireza Sanaee
FWIW table will changes so this patch is needed...
Reviewed-by: Jonathan Cameron
>
On Wed, Mar 12, 2025 at 11:28:04AM +0530, Harsh Prateek Bora wrote:
> When POWER10 CPU was made as default, we missed keeping POWER9 as
> default for older pseries releases (pre-10.0) at that time.
> This caused breakge in default cpu evaluation for older pseries
> machines and hence this fix.
>
>
On Thu, Mar 13, 2025 at 2:40 PM Jörg Rödel wrote:
>
> Hi Ani,
>
> On Fri, Feb 14, 2025 at 09:04:07PM +0530, Ani Sinha wrote:
> > VM firmware update is a mechanism where the virtual machines can use their
> > preferred and trusted firmware image in their execution environment without
> > having to
On 13/3/25 09:10, Michael Tokarev wrote:
05.03.2025 18:39, Philippe Mathieu-Daudé wrote:
There is no TARGET_ARM_64 definition. Luckily enough,
when TARGET_AARCH64 is defined, TARGET_ARM also is.
Fixes: 733766cd373 ("hw/arm: introduce xenpvh machine")
Signed-off-by: Philippe Mathieu-Daudé
---
I could have sworn I had this is a previous iteration of the patches
but I guess it got lost in a re-base. As we are going to call
vulkaninfo to probe for "bad" drivers we need to skip if the binary
isn't available.
Fixes: 9f7e493d11 (tests/functional: skip vulkan tests with nVidia)
Signed-off-by:
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