On Thu, Mar 13, 2025 at 04:39:15PM +0530, Ani Sinha wrote:
> Right so what we are proposing is generic enough so that if the VM
> wants to use an IGVM container as opposed to an actual firmware image
> in a FUKI, that is totally possible. Then you need to have that IGVM
> setup the memory in a well
Add functional test for AST2700a1-fc machine.
Signed-off-by: Steven Lee
Change-Id: I87584164b2632c58d2e051fd92d9e280347bcf19
---
tests/functional/test_aarch64_ast2700fc.py | 38 +-
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/tests/functional/test_aarch64_as
Bibo Mao writes:
> There is NULL pointer checking function error_propagate() already,
> it is not necessary to add checking for function parameter. Here remove
> NULL pointer checking with function parameter.
>
> Signed-off-by: Bibo Mao
> ---
> hw/loongarch/virt.c | 12 +++-
> 1 file ch
On 3/7/25 5:39 PM, Jason Chien wrote:
When the IOMMU detects that bus->iommu_ops has been registered, indicating
the presence of an ATU, it sets the bus's downstream memory region to ensure
transactions are directed to the IOMMU.
Signed-off-by: Jason Chien
---
Reviewed-by: Daniel Henrique
On 2/25/25 1:00 PM, Loïc Lefort wrote:
With Machine Mode Lockdown (mseccfg.MML) set and RLB not set, checks on pmpcfg
writes would match the wrong cases of Smepmp truth table.
The existing code allows writes for the following cases:
- L=1, X=0: cases 8, 10, 12, 14
- L=0, RWX!=WX: cases 0-2, 4
On 2/25/25 1:00 PM, Loïc Lefort wrote:
Signed-off-by: Loïc Lefort
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/pmp.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index e0ea436f8e..e4fee10d9
On 2/25/25 1:00 PM, Loïc Lefort wrote:
Remove useless check in pmp_is_locked, the function will return 0 in either
case.
Signed-off-by: Loïc Lefort
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/pmp.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target/riscv/pmp.c b
Hello Peter,
On Sat, 8 Mar 2025 at 04:18, Peter Xu wrote:
> [1]
> Please move all of them at the entry of postcopy_start().
> I still like the name I provided because it's more generic, above [1].
> Maybe it should be SECTION_PART. So we provide all iterator a chance to
> do something right bef
Hi Gerd,
On Thu, Mar 13, 2025 at 01:05:13PM +0100, Gerd Hoffman wrote:
> // regions_addr points to an array of this structure
> struct vmfwupdate_regions {
> uint64_t size;
> uint64_t src_addr; // source address (before update)
> uint64_t dst_addr; // destination address (a
Hi Shameer,
On 3/12/25 6:28 PM, Shameerali Kolothum Thodi wrote:
>
>> -Original Message-
>> From: Daniel P. Berrangé
>> Sent: Wednesday, March 12, 2025 4:39 PM
>> To: Shameerali Kolothum Thodi
>> Cc: eric.au...@redhat.com; qemu-...@nongnu.org; qemu-
>> de...@nongnu.org; peter.mayd...@l
This patch replaces the use of a helper function with direct tcg ops generation
in order to emulate whole register loads and stores. This is done in order to
improve the performance of QEMU.
We still use the helper function when vstart is not 0 at the beginning of the
emulation of the whole registe
Previous versions:
- RFC v1:
https://lore.kernel.org/all/20241218170840.1090473-1-paolo.sav...@embecosm.com/
- RFC v2:
https://lore.kernel.org/all/20241220153834.16302-1-paolo.sav...@embecosm.com/
- RFC v3:
https://lore.kernel.org/all/20250122164905.13615-1-paolo.sav...@embecosm.com/
Version v
John Snow writes:
> On Thu, Mar 13, 2025 at 2:54 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > This also creates the `qapi-qsd-index` and `qapi-qga-index` QMP indices.
>> >
>> > Signed-off-by: John Snow
>>
>> [...]
>>
>> > diff --git a/qga/qapi-schema.json b/qga/qapi-schema.json
>
On Sat, Mar 08, 2025 at 06:16:17PM +0800, zoudongjie wrote:
> From: Zhu Yangyang
>
> The bdrv_drained_begin() function is a blocking function. In scenarios where
> network storage
> is used and network links fail, it may block for a long time.
> Therefore, we add a timeout parameter to control t
On 13/3/25 11:07, Philippe Mathieu-Daudé wrote:
On 13/3/25 04:45, Richard Henderson wrote:
Uninline the user-only stubs from hw/core/cpu.h.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 23 ---
common-user/watchpoint-stub.c | 28 +++
On Thu, 13 Mar 2025 09:24:56 +
Jonathan Cameron wrote:
> On Mon, 10 Mar 2025 16:23:35 +
> Alireza Sanaee wrote:
>
> > Add cache topology to PPTT table. With this patch, both ACPI PPTT
> > table and device tree will represent the same cache topology given
> > users input.
> >
> > Signed
On 13/3/25 07:13, Thomas Huth wrote:
On 13/03/2025 03.34, Stefan Hajnoczi wrote:
On Tue, Mar 11, 2025 at 8:59 PM Nicholas Piggin
wrote:
The following changes since commit
825b96dbcee23d134b691fc75618b59c5f53da32:
Merge tag 'migration-20250310-pull-request' of https://gitlab.com/
farosa
On 13/3/25 04:44, Richard Henderson wrote:
CONFIG_USER_ONLY == !CONFIG_SYSTEM_ONLY.
Therefore it's cleaner to just add to user_ss.
Signed-off-by: Richard Henderson
---
accel/tcg/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
From: Nicholas Piggin
Assets are uniquely identified by human-readable-ish url, so make an
AssetError exception class that prints url with error message.
A property 'transient' is used to capture whether the client may retry
or try again later, or if it is a serious and likely permanent error.
T
From: Yu-Ming Chang
For privilege version 1.12 or newer, C always implies Zca. We can only
check ext_zca to allow 16-bit aligned PC addresses. For older privilege
versions, we only check C.
Signed-off-by: Yu-Ming Chang
---
target/riscv/cpu.h | 12
target/riscv
On Thu, Mar 13, 2025 at 2:39 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Akin to the :module: override option, the :namespace: options allows you
> > to forcibly override the contextual namespace associatied with a
> > definition.
> >
> > We don't necessarily actually need this, but I
John Snow writes:
> On Thu, Mar 13, 2025 at 10:41 AM Markus Armbruster
> wrote:
>
>> John Snow writes:
>>
>> > On Thu, Mar 13, 2025 at 2:47 AM Markus Armbruster
>> > wrote:
>> >
>> >> John Snow writes:
>> >>
>> >> > This patch does three things:
>> >> >
>> >> > 1. Record the current namespac
On 2/23/2025 19:57, Jason Wang wrote:
On Sat, Feb 22, 2025 at 3:08 AM Konstantin Shkolnyy wrote:
Add .set_vnet_le() function that always returns success, assuming that
vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and
outputs the message:
"backend does not support LE
On Wed, Mar 12, 2025 at 03:33:12PM -0400, Gregory Price wrote:
> On Wed, Mar 12, 2025 at 06:05:43PM +, Jonathan Cameron wrote:
> >
> > Longer term I remain a little unconvinced by whether this is the best
> > approach
> > because I also want a single management path (so fake CCI etc) and that
On Thu, Mar 13, 2025 at 2:54 AM Markus Armbruster wrote:
> John Snow writes:
>
> > This also creates the `qapi-qsd-index` and `qapi-qga-index` QMP indices.
> >
> > Signed-off-by: John Snow
>
> [...]
>
> > diff --git a/qga/qapi-schema.json b/qga/qapi-schema.json
> > index 995594aaf43..35ec0e7db3
Richard Henderson writes:
> All this is working toward building accel/tcg/translator.c once,
> but it got late and I decided to stop at a convenient milestone.
>
>
> I know there is overlap with other in-flight patches, but it
> seemed easiest to just start from master.
I guess that was why the
On Thu, Mar 13, 2025 at 7:01 PM Jörg Rödel wrote:
>
> Hi Gerd,
>
> On Thu, Mar 13, 2025 at 01:05:13PM +0100, Gerd Hoffman wrote:
> > // regions_addr points to an array of this structure
> > struct vmfwupdate_regions {
> > uint64_t size;
> > uint64_t src_addr; // source address (befor
Generate an index-per-namespace for the QAPI domain. Due to a limitation
with Sphinx's architecture, these indices must be defined during setup
time and cannot be dynamically created on-demand when a namespace
directive is encountered.
Owing to that limitation, add a configuration value to conf.py
Makes live migration more robust. Commit 4c0cfc72b31a ("pflash_cfi01:
write flash contents to bdrv on incoming migration") elaborates in
detail on the motivation.
Cc: Peter Krempa
Signed-off-by: Gerd Hoffmann
---
hw/uefi/var-service-core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
John Snow writes:
> On Thu, Mar 13, 2025 at 2:47 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > This patch does three things:
>> >
>> > 1. Record the current namespace context in pending_xrefs so it can be
>> >used for link resolution later,
>> > 2. Pass that recorded namespace
On 3/12/25 12:12 AM, Arun Kodilkar, Sairaj wrote:
Hi Alejandro,
On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
[...]
--- a/hw/i386/amd_iommu.h
+++ b/hw/i386/amd_iommu.h
@@ -25,6 +25,8 @@
#include "hw/i386/x86-iommu.h"
#include "qom/object.h"
+#define GENMASK64(h, l) (((~0ULL) >> (63
There is NULL pointer checking function error_propagate() already,
it is not necessary to add checking for function parameter. Here remove
NULL pointer checking with function parameter.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletion
> The devil lies in "same order of setup calls". Without a way to define
> this order through the vmfwupdate interface there is a lot of implicit
> knowledge required about how KVM/QEMU setup the TEE context to calculate
> the expected after-reset launch measurement. Even worse, the exact way
> thi
This commit expands the probe_pages helper function in
target/riscv/vector_helper.c to handle also the cases in which we need access to
the flags raised while probing the memory and the host address.
This is done in order to provide a unified interface to probe_access and
probe_access_flags.
The ne
Kevin Wolf writes:
> Am 12.03.2025 um 15:37 hat Markus Armbruster geschrieben:
>> bdrv_activate() returns failure without setting an error when
>> !bs->drv. This is suspicious. Turns out it used to succeed then,
>> until commit 5416645fcf82 changed it to return -ENOMEDIUM.
>>
>> Return zero in
On 2/25/25 1:00 PM, Loïc Lefort wrote:
When Smepmp is supported, RLB allows bypassing locks when writing CSRs but
should not affect interpretation of actual PMP rules.
pmp_is_locked is changed to only check LOCK bit and a new pmp_is_readonly
function is added that checks both LOCK bit and mse
On Thu, Mar 13, 2025 at 4:57 PM Jörg Rödel wrote:
>
> On Thu, Mar 13, 2025 at 04:39:15PM +0530, Ani Sinha wrote:
> > Right so what we are proposing is generic enough so that if the VM
> > wants to use an IGVM container as opposed to an actual firmware image
> > in a FUKI, that is totally possible.
On 2/25/25 1:00 PM, Loïc Lefort wrote:
Signed-off-by: Loïc Lefort
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/pmp.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index ddb7e0d23c..b7f1430f
Previous version:
- v1:
https://lore.kernel.org/all/20250221162036.61521-1-paolo.sav...@embecosm.com/
Add reviewer information and rebase on top of riscv-to-apply.next branch.
Cc: Richard Handerson
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Bin Meng
Cc: Weiwei Li
Cc: Daniel Henrique Barbo
From: Peter Maydell
On my machine the arm_replay test takes over 2 minutes to run
in a config with Rust enabled and debug enabled:
$ time (cd build/rust ; PYTHONPATH=../../python:../../tests/functional
QEMU_TEST_QEMU_BINARY=./qemu-system-arm ./pyvenv/bin/python3
../../tests/functional/test_arm_r
On 3/13/25 04:34, Saanjh Sengupta wrote:
Hi,
What we are trying to achieve is that the QEMU should run for a
particular number of instructions, let's say for example 1
instructions and then pause it's emulation. After a resume trigger is
received to the QEMU it must resume it's emulation
On Thu, Mar 13, 2025 at 4:57 PM Jörg Rödel wrote:
>
> On Thu, Mar 13, 2025 at 04:39:15PM +0530, Ani Sinha wrote:
> > Right so what we are proposing is generic enough so that if the VM
> > wants to use an IGVM container as opposed to an actual firmware image
> > in a FUKI, that is totally possible.
A previous change made the OpRegion and LPC quirks independent of the
existing legacy mode, update the documentation accordingly. More related
topics, like creating EFI Option ROM of IGD for OVMF, how to solve the
VFIO_DMA_MAP Invalid Argument warning, as well as details on IGD memory
internals, ar
On Thu, Mar 13, 2025 at 10:41 AM Markus Armbruster
wrote:
> John Snow writes:
>
> > On Thu, Mar 13, 2025 at 2:47 AM Markus Armbruster
> wrote:
> >
> >> John Snow writes:
> >>
> >> > This patch does three things:
> >> >
> >> > 1. Record the current namespace context in pending_xrefs so it can b
On 3/12/25 20:44, Richard Henderson wrote:
All this is working toward building accel/tcg/translator.c once,
but it got late and I decided to stop at a convenient milestone.
In the process, I discovered that we have already added files to
common_ss which indirectly depend on CONFIG_USER_ONLY. So
On Thu, Mar 13, 2025 at 2:47 AM Markus Armbruster wrote:
> John Snow writes:
>
> > This patch does three things:
> >
> > 1. Record the current namespace context in pending_xrefs so it can be
> >used for link resolution later,
> > 2. Pass that recorded namespace context to find_obj() when res
Hi Ani,
On Fri, Feb 14, 2025 at 09:04:07PM +0530, Ani Sinha wrote:
> VM firmware update is a mechanism where the virtual machines can use their
> preferred and trusted firmware image in their execution environment without
> having to depend on a untrusted party to provide the firmware bundle. This
They are now accessible through exec/memory.h instead, and we make sure
all variants are available for common or target dependent code.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 12
include/exec/memory_ldst.h.inc | 4
Hi Jörg,
On 13.03.25 16:39, Jörg Rödel wrote:
On Thu, Mar 13, 2025 at 08:23:44PM +0530, Ani Sinha wrote:
Note that even with this approach where the hypervisor *thinks* it's
dealing with a real firmware, you can imagine a small rust based
firmware image that is loaded by the guest in the firmwa
On 3/12/25 20:44, Richard Henderson wrote:
CONFIG_USER_ONLY == !CONFIG_SYSTEM_ONLY.
Therefore it's cleaner to just add to user_ss.
Signed-off-by: Richard Henderson
---
accel/tcg/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/meson.build b/accel/
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/tswap.h | 11 ++-
cpu-target.c | 1 +
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/include/exec/tswap.h b/include/exec/tswap.h
index ecd4faef015..2683da0adb7 100644
--- a/include/ex
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/ram_addr.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index f5d574261a3..92e8708af76 100644
--- a/include/exec/ram_addr.h
+++ b/inclu
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/tcg/tcg-op.h | 1 +
target/ppc/helper_regs.h | 2 ++
hw/ppc/spapr_nested.c | 1 +
hw/sh4/sh7750.c| 1 +
page-vary-target.c | 2 +-
target/ppc/tcg-excp_helper.c | 1 +
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
system/memory.c| 17 +
system/meson.build | 2 +-
2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/system/memory.c b/system/memory.c
index 4c829793a0a..eddd21a6cdb 100644
--- a/system/memory.c
This function is used by system/physmem.c will be turn into common code
in next commit.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/system/kvm.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/system/kvm.h b/include/system/kvm.h
i
They are now accessible through exec/memory.h instead, and we make sure
all variants are available for common or target dependent code.
Move stl_phys_notdirty function as well.
Cached endianness agnostic version rely on st/ld*_p, which is available
through tswap.h.
Reviewed-by: Richard Henderson
Previous commit changed files relying transitively on it.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/exec-all.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index dd5c40f2233..19b0eda44a7 100644
--- a/i
On 10/3/25 05:11, Duan, Zhenzhong wrote:
Hi Philippe,
-Original Message-
From: Philippe Mathieu-Daudé
Subject: [PATCH v2 15/21] hw/vfio/pci: Check CONFIG_IOMMUFD at runtime
using iommufd_builtin()
Convert the compile time check on the CONFIG_IOMMUFD definition
by a runtime one by call
The main goal of this series is to be able to call any memory ld/st function
from code that is *not* target dependent. As a positive side effect, we can
turn related system compilation units into common code.
The first 5 patches remove dependency of memory API to cpu headers and remove
dependency
Reduce misc-target.json by one target specific command.
Error message is returned for machines not implementing
TYPE_DUMP_SKEYS_INTERFACE:
$ qemu-system-aarch64 -M virt -S -qmp stdio
{"QMP": {"version": {"qemu": {"micro": 50, "major": 9}}, "capabilities":
["oob"]}}
{ "execute": "qmp_capabi
On 11/03/25 10:53, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
Add offsets for the processor state captured during MPIPL dump.
This is incomplete. And might be implemented in future if the effort to
implement MPIPL is resumed again.
Please use RFC prefix in next iterati
Add skeleton for handle "ibm,configure-kernel-dump" rtas call in QEMU.
Verify basic details mandated by the PAPR, such as number of
inputs/output, and add handling for the three fadump commands:
regiser/unregister/invalidate.
Currently fadump register will always return HARDWARE ERROR, since it's
While the first kernel boots, it registers memory regions for fadump
such as:
* CPU state data (has to be populated by the platform)
* HPTE state data (has to be populated by the platform)
* Real Mode Regions (platform should copy it to requested
destination addresses)
* OS d
Overview
=
Implemented Firmware Assisted Dump (fadump) on PSeries machine in QEMU.
Fadump is an alternative dump mechanism to kdump, in which we the firmware
does a memory preserving boot, and the second/crashkernel is booted fresh
like a normal system reset, instead of the crashed kernel
According to PAPR:
R1–7.3.30–3. When the platform receives an ibm,os-term RTAS call, or
on a system reset without an ibm,nmi-interlock RTAS call, if the
platform has a dump structure registered through the
ibm,configure-kernel-dump call, the platform must process each
registere
Platform (ie. QEMU) is expected to pass few device tree properties for
details for fadump:
* "ibm,configure-kernel-dump-sizes": Space required to store dump data
for firmware provided dump sections (ie. CPU & HPTE regions)
* "ibm,configure-kernel-dump-version": Versions of fadump supported
On 3/13/25 11:05, Richard Henderson wrote:
On 3/13/25 09:59, Pierrick Bouvier wrote:
+static inline int
+cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra);
For my person
On 11/03/25 11:11, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
Linux expect a "ibm,opal/dump" node to know whether MPIPL (aka fadump)
is supported on the hardware.
Export the "ibm,opal/dump" node in QEMU's device tree for Linux to know
that PowerNV supports MPIPL.
With t
On 3/13/25 10:48, Philippe Mathieu-Daudé wrote:
On 13/3/25 17:36, Pierrick Bouvier wrote:
On 3/12/25 20:44, Richard Henderson wrote:
All this is working toward building accel/tcg/translator.c once,
but it got late and I decided to stop at a convenient milestone.
In the process, I discovered th
On 3/12/25 20:45, Richard Henderson wrote:
Poison CONFIG_USER_ONLY and CONFIG_SOFTMMU unless
the compilation unit is in specific_ss, libuser_ss,
or libsystem_ss. This is intended to prevent files
being incorrectly added to common_ss.
Remove #ifndef CONFIG_USER_ONLY / #error / #endif blocks.
All
On 3/12/25 20:45, Richard Henderson wrote:
Semihosting is not enabled for user-only.
Avoid the test for that case.
Signed-off-by: Richard Henderson
---
target/mips/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index b207106d
On 3/12/25 20:45, Richard Henderson wrote:
Semihosting is not enabled for user-only.
Avoid the test for that case.
Signed-off-by: Richard Henderson
---
target/xtensa/translate.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/xtensa/translate.c b/targ
On 3/12/25 20:45, Richard Henderson wrote:
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
include/{exec => system}/ram_addr.h | 7 +++
accel/kvm/kvm-all.c | 2 +-
accel/tcg/cputlb.c | 2 +-
accel/tcg/translate-all.c
On 3/12/25 20:45, Richard Henderson wrote:
The implementation of cpu_mmu_index was split between
cpu-common.h and cpu-all.h, depending on CONFIG_USER_ONLY.
Unify within a new header and include only where needed.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h| 6 --
On 3/12/25 20:45, Richard Henderson wrote:
Uninline the user-only stubs from hw/core/cpu.h.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 23 ---
common-user/watchpoint-stub.c | 28
common-user/meson.build | 1 +
On 3/12/25 20:45, Richard Henderson wrote:
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them.
Signed-off-by: Richard Henderson
---
include/exec/cpu-common.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/include/exec/cpu-common.h b/incl
On 3/13/25 9:26 AM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>> -Original Message-
>> From: Eric Auger
>> Sent: Wednesday, March 12, 2025 6:31 PM
>> To: Shameerali Kolothum Thodi
>> ; qemu-...@nongnu.org;
>> qemu-devel@nongnu.org
>> Cc: peter.mayd...@linaro.org; j...@nvidia.com; n
Hello Stefan, Thomas,
Thanks for reporting this. I'll try to spend some time to figure out the
issue and perhaps propose a new image for this test, if needed.
Regards,
Niek
On Thu, Mar 13, 2025 at 8:39 AM Stefan Hajnoczi wrote:
> On Thu, Mar 13, 2025 at 1:48 PM Thomas Huth wrote:
> >
> > On 1
On 3/13/25 11:17, Richard Henderson wrote:
On 3/13/25 10:33, Pierrick Bouvier wrote:
On 3/12/25 20:44, Richard Henderson wrote:
Add a new family of translator load functions which take
an absolute endianness value in the form of MO_BE/MO_LE.
Expand the other translator_ld* functions on top of t
Hi,
What we are trying to achieve is that the QEMU should run for a particular
number of instructions, let's say for example 1 instructions and then pause
it's emulation. After a resume trigger is received to the QEMU it must resume
it's emulation and start the instruction count from 10001
On Thu, Mar 13, 2025 at 12:40 PM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
>
>
> On 2/25/25 1:00 PM, Loïc Lefort wrote:
> > When Smepmp is supported, RLB allows bypassing locks when writing CSRs
> but
> > should not affect interpretation of actual PMP rules.
> >
> > pmp_is_locked
On Thu, Mar 13, 2025 at 08:23:44PM +0530, Ani Sinha wrote:
> Note that even with this approach where the hypervisor *thinks* it's
> dealing with a real firmware, you can imagine a small rust based
> firmware image that is loaded by the guest in the firmware region.
> This tiny firmware then jumps t
Hi,
On 2/24/25 9:54 PM, Sebastian Huber wrote:
Further customize the -bios and -kernel options behaviour for the
microchip-icicle-kit machine. If "-bios none -kernel filename" is
specified, then do not load a firmware and instead only load and start
the kernel image.
Signed-off-by: Sebastian H
On Thu, 6 Mar 2025 at 16:39, Peter Maydell wrote:
>
> In the Arm ARM, rule R_TYTWB states that returning to AArch32
> is an illegal exception return if:
> * AArch32 is not supported at any exception level
> * the target EL is configured for AArch64 via SCR_EL3.RW
>or HCR_EL2.RW or via CPU st
Richard Henderson writes:
> These expand inline to the *_mmuidx_ra api with
> a lookup of the target's cpu_mmu_index().
>
> Signed-off-by: Richard Henderson
This is where my re-based bisect broke. Fixed by moving cpu.h
modified target/ppc/tcg-excp_helper.c
@@ -19,6 +19,7 @@
#include "qemu/o
On 11/03/25 10:41, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
Add the MDST, MDDT, MDRT tables offsets and structures as per current
skiboot upstream:
commit bc7b85db1e7e ("opal-ci: Remove centos7")
These structures will be later populated when preserving memory reg
With Machine Mode Lockdown (mseccfg.MML) set and RLB not set, checks on pmpcfg
writes would match the wrong cases of Smepmp truth table.
The existing code allows writes for the following cases:
- L=1, X=0: cases 8, 10, 12, 14
- L=0, RWX!=WX: cases 0-2, 4-6
This leaves cases 3, 7, 9, 11, 13, 15 for
Signed-off-by: Loïc Lefort
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/pmp.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index e1e5ca589e..7d65dc24a5 100644
--- a/target/riscv/pmp.c
+++ b/target/ri
On 3/13/25 11:47, ltaylorsimp...@gmail.com wrote:
What we are trying to model is an instance of a Hexagon that has a number of
threads and some resources that are shared. The shared resources include the
TLB and global S registers. The initial thought was to tie the shared
resources to the t
On Thu, Mar 13, 2025 at 2:30 PM Markus Armbruster wrote:
> John Snow writes:
>
> > On Thu, Mar 13, 2025, 11:57 AM Markus Armbruster
> wrote:
> >
> >> John Snow writes:
> >>
> >> > On Thu, Mar 13, 2025 at 10:41 AM Markus Armbruster >
> >> > wrote:
> >> >
> >> >> John Snow writes:
> >> >>
> >>
Use vaddr only for the newest api, because it has the least
number of uses and therefore is the easiest to audit.
Signed-off-by: Richard Henderson
---
accel/tcg/atomic_template.h | 16 ++---
include/exec/cpu_ldst.h | 48 ++---
accel/tcg/cputlb.c
Remove useless check in pmp_is_locked, the function will return 0 in either
case.
Signed-off-by: Loïc Lefort
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/pmp.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 845915e0c8..c685f7f2c5 1
Signed-off-by: Loïc Lefort
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/pmp.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index c5f6cdaccb..845915e0c8 100644
--- a/target/riscv/pmp.c
+++ b/target/ris
On Thu, Mar 13, 2025 at 06:13:24PM +0530, Prasad Pandit wrote:
> +int qemu_savevm_state_postcopy_prepare(QEMUFile *f)
> +{
> +int ret = 0;
> +SaveStateEntry *se;
> +
> +QTAILQ_FOREACH(se, &savevm_state.handlers, entry) {
> +if (strcmp(se->idstr, "ram")) {
> +continue
On 3/12/25 20:45, Richard Henderson wrote:
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them. The inlines
for user-only are unused.
Signed-off-by: Richard Henderson
---
include/hw/intc/armv7m_nvic.h | 14 --
1 file changed, 14 deleti
On 3/12/25 20:45, Richard Henderson wrote:
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them.
Signed-off-by: Richard Henderson
---
include/hw/s390x/css.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/s390x/css.h b/include/hw/s39
On 3/12/25 20:45, Richard Henderson wrote:
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
include/system/ram_addr.h | 2 +-
include/{exec => system}/ramblock.h | 9 -
hw/display/virtio-gpu-udmabuf.c | 2 +-
hw/hyperv/hv-balloon.c
On 3/12/25 20:45, Richard Henderson wrote:
Many of the headers used by these require CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
hw/core/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/core/meson.build b/hw/core/meson.build
index b5a545a0ed..
On 3/12/25 20:45, Richard Henderson wrote:
While RISCVCPUConfig.satp_mode is unused for user-only,
this header is used from disas/riscv.h, whose users are
only built once. The savings of 4 bytes isn't worth it.
Signed-off-by: Richard Henderson
---
target/riscv/cpu_cfg.h | 2 --
1 file chang
Implement the register command of "ibm,configure-kernel-dump" RTAS call.
The register just verifies the structure of the fadump memory structure
passed by kernel, and set fadump_registered in spapr state to true.
We also store the passed fadump memory structure, which will later be
used for preser
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