From: Nicolin Chen
Add a helper to allocate an iommufd device's virtual device (in the user
space) per a viommu instance.
Signed-off-by: Nicolin Chen
Signed-off-by: Shameer Kolothum
---
backends/iommufd.c | 26 ++
backends/trace-events| 1 +
include/system/i
Subsequent patches for smmuv3-accel will make use of this
Signed-off-by: Nicolin Chen
Signed-off-by: Shameer Kolothum
---
hw/arm/smmu-common.c | 48 ++--
include/hw/arm/smmu-common.h | 6 +
2 files changed, 36 insertions(+), 18 deletions(-)
diff --g
From: Nicolin Chen
Allocate and associate a vDEVICE object for the Guest device
with the vIOMMU. This will help the kernel to do the
vSID --> sid translation whenever required (eg: device specific
invalidations).
Signed-off-by: Nicolin Chen
Signed-off-by: Shameer Kolothum
---
hw/arm/smmuv3-ac
Until now, a SCSIDevice's I/O requests have run in a single AioContext.
In order to support multiple IOThreads it will be necessary to move to
the concept of a per-SCSIRequest AioContext.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Kevin Wolf
---
include/hw/scsi/scsi.h | 1 +
hw/scsi/scsi-bus.
Subsequently smmuv3-accel will provide these callbacks
Signed-off-by: Shameer Kolothum
---
hw/arm/smmu-common.c | 27 +++
include/hw/arm/smmu-common.h | 5 +
2 files changed, 32 insertions(+)
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 83c
From: Nicolin Chen
When nested translation is enabled, there are 2-stage translation
occuring to two different address spaces: stage-1 in the iommu as,
while stage-2 in the system as.
If a device attached to the vSMMU doesn't enable stage-1 translation,
e.g. vSTE sets to Config=Bypass, the syste
From: Nicolin Chen
Inroduce an SMMUCommandBatch and some helpers to batch and issue the
commands. Currently separate out TLBI commands and device cache commands
to avoid some errata on certain versions of SMMUs. Later it should check
IIDR register to detect if underlying SMMU hw has such an erra
From: Nicolin Chen
With nested translation, the underlying HW could support those two fields.
Allow them according to the updated idr registers after the hw_info ioctl.
When substreams are enabled (S1CDMax != 0), S1DSS field determines
the behavior of a transaction.
Signed-off-by: Nicolin Chen
From: Nicolin Chen
Use the provided smmuv3-accel helper functions to issue the
command to physical SMMUv3.
Signed-off-by: Nicolin Chen
Signed-off-by: Shameer Kolothum
---
hw/arm/smmuv3-internal.h | 11
hw/arm/smmuv3.c | 58 +++-
2 files ch
Now that we can have multiple user-creatable smmuv3-accel devices,
each associated with different pci buses, update IORT ID mappings
accordingly.
Signed-off-by: Shameer Kolothum
---
hw/arm/virt-acpi-build.c | 113 +--
1 file changed, 97 insertions(+), 16 delet
From: Nicolin Chen
Read the underlying SMMUv3 device info and set corresponding IDR
bits. We need at least one cold-plugged vfio-pci dev associated
with the smmuv3-accel instance to do this now. Hence fail if it
is not available.
ToDo: The above requirement will be relaxed in future when we add
aio_dispatch_handler() adds handlers to ctx->poll_aio_handlers if
polling should be enabled. If we call adjust_polling_time() for all
polling handlers before this, new polling handlers are still left at
poll->ns = 0 and polling is only actually enabled after the next event.
Move the adjust_polling_
The size mask currently encompasses reserved bits [11:9]. Extract only the
corrects bits encoding size (i.e. [8:0]).
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.h | 10 +-
1 file changed, 5 inserti
Correctly calculate the Device Table size using the format encoded in the
Device Table Base Address Register (MMIO Offset h).
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 4 ++--
1 file changed, 2 i
On 11/03/2025 15.00, Eric Auger wrote:
Hi Thomas,
On 3/11/25 11:49 AM, Thomas Huth wrote:
This test was using cloudinit and a "dnf install" command in the guest
to exercise the NIC with SMMU enabled. Since we don't have the cloudinit
stuff in the functional framework and we should not rely on
Correct mistakes in bitmasks, offsets, decoding of fields, and behavior that
do not match the latest AMD I/O Virtualization Technology (IOMMU)
Specification. These bugs do not trigger problems today in the limited mode
of operation supported by the AMD vIOMMU (passthrough), but upcoming
functional
The AMD I/O Virtualization Technology (IOMMU) Specification (see Table 8: V,
TV, and GV Fields in Device Table Entry), specifies that a DTE with V=0,
TV=1 does not contain a valid address translation information. If a request
requires a table walk, the walk is terminated when this condition is
enc
The definitions encoding the maximum Virtual, Physical, and Guest Virtual
Address sizes supported by the IOMMU are using incorrect offsets i.e. the
VASize and GVASize offsets are switched.
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jime
On 3/11/25 00:36, Philippe Mathieu-Daudé wrote:
On 11/3/25 05:08, Pierrick Bouvier wrote:
we'll use it in system/memory.c.
Having part of the commit description separated in its subject is a
bit annoying. But then I'm probably using 20-years too old tools in
my patch workflow.
Can you please
On Tue, Mar 11, 2025 at 08:13:16AM +, Daniel P. Berrangé wrote:
> On Mon, Mar 10, 2025 at 04:03:26PM -0400, Peter Xu wrote:
> > On Mon, Mar 10, 2025 at 07:48:16PM +, Daniel P. Berrangé wrote:
> > > Given this is in public API, the data needs to remain reported accurately
> > > for the whole
Sure
Thanks
Manish Mishra
On 11/03/25 8:52 pm, Peter Xu wrote:
!---|
CAUTION: External Email
|---!
On Tue, Mar 11, 2025 at 04:15:38AM +0530, Manish wrote:
Thank
Creates an object indicating that an AP configuration change event
has been received and stores it in a queue. These objects will later
be used to store event information for an AP configuration change
when the CHSC instruction is intercepted.
Signed-off-by: Rorie Reyes
---
hw/vfio/ap.c | 12 +++
On Tue, Mar 11, 2025 at 11:20:50AM -0400, Peter Xu wrote:
> On Tue, Mar 11, 2025 at 08:13:16AM +, Daniel P. Berrangé wrote:
> > On Mon, Mar 10, 2025 at 04:03:26PM -0400, Peter Xu wrote:
> > > On Mon, Mar 10, 2025 at 07:48:16PM +, Daniel P. Berrangé wrote:
> > > > Given this is in public API
The DeviceID bits are extracted using an incorrect offset in the call to
amdvi_iotlb_remove_page(). This field is read (correctly) earlier, so use
the value already retrieved for devid.
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
This patch adds enumeration constant VFIO_AP_CFG_CHG_IRQ_INDEX to specify
an IRQ index for signaling that a change has been made to the guest's AP
configuration. This is a placeholder for QEMU patches that use this value
since it is a linux-headers update which includes changes that aren't
merged i
From: Cédric Le Goater
Since we are about to remove all support for PPC 405, start by
removing the tests referring to the ref405ep machine.
Link: https://lore.kernel.org/qemu-devel/20250110141800.1587589-2-...@redhat.com
Signed-off-by: Cédric Le Goater
Reviewed-by: Nicholas Piggin
Message-ID:
From: Eric Auger
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate the storage of those
ID regs from named
Yet another update of the id register series, less changes this time
around.
Changed from v2:
- changed generation of the various register defines via the "DEF"
magic suggested by Richard
- some kvm-only code moved to kvm.c; some code potentially useful to
non-kvm code stayed out of there (the
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 57 ---
target/arm/cpu.c | 10 +++
target/arm/cpu.h | 2 --
target/arm/cpu64.c| 8 +++---
target/arm/helper.c | 6 +
Signed-off-by: Cornelia Huck
---
target/arm/cpu-sysregs.h | 4
target/arm/kvm.c | 22 ++
2 files changed, 26 insertions(+)
diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
index b95320b5b595..68a7de737185 100644
--- a/target/arm/cpu-sysregs.h
+++
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 40 -
target/arm/cpu.c | 29
target/arm/cpu.h | 2 --
target/arm/cpu64.c| 14
target/arm/help
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 44 +++
target/arm/cpu.c | 12 ---
target/arm/cpu.h | 2 --
target/arm/cpu64.c| 9
target/arm/helper.c
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 12 ++--
target/arm/cpu-features.h | 36 +-
target/arm/cpu.c | 24 +++
target/arm/cpu.h | 7 --
target/arm/cpu64.c| 28
target/arm/helper
Hi Thomas,
On 3/11/25 4:24 PM, Thomas Huth wrote:
> On 11/03/2025 15.00, Eric Auger wrote:
>> Hi Thomas,
>>
>>
>> On 3/11/25 11:49 AM, Thomas Huth wrote:
>>> This test was using cloudinit and a "dnf install" command in the guest
>>> to exercise the NIC with SMMU enabled. Since we don't have the
>
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 8 ++--
target/arm/cpu-features.h | 18
target/arm/cpu.h | 6 ---
target/arm/cpu64.c| 16 +++
target/arm/helper.c | 12 ++---
target/arm/kvm.c
From: Eric Auger
Introduce scripts that automate the generation of system register
definitions from a given linux source tree arch/arm64/tools/sysreg.
Invocation of
./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TREE
in scripts directory generates target/arm/cpu-sysregs.h.inc
containing d
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 2 +-
target/arm/cpu-features.h | 16
target/arm/cpu.c | 13 +
target/arm/cpu.h | 2 --
target/arm/cpu64.c| 4 ++--
target/arm/helpe
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 6 +++---
target/arm/cpu.h | 1 -
target/arm/cpu64.c| 7 ++-
target/arm/helper.c | 2 +-
target/arm/kvm.c | 3 +--
target/arm/tcg/cpu64.c| 4 ++--
6 f
Generated against Linux 6.14-rc1.
Signed-off-by: Cornelia Huck
---
target/arm/cpu-sysregs.h.inc | 161 ---
1 file changed, 148 insertions(+), 13 deletions(-)
diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
index 6c9f9981cc5d..a3829f40d3da
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 5 +-
target/arm/cpu-features.h | 10 ++--
target/arm/cpu.c | 8 +--
target/arm/cpu.h | 3 -
target/arm/cpu64.c| 8 +--
target/arm/helper.c | 8 +--
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 74 +++
target/arm/cpu.h | 4 ---
target/arm/cpu64.c| 8 ++---
target/arm/helper.c | 8 ++---
target/arm/hvf/hvf.c | 21 +++
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 16
target/arm/cpu.c | 15 +--
target/arm/cpu.h | 2 --
target/arm/cpu64.c| 4 ++--
target/arm/helper.c | 4 ++--
target/arm/h
The BMC HIOMAP PNOR access protocol has certain limits on PNOR addresses
and sizes. Add some sanity checks for these so we don't get strange
behaviour.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv_bmc.c | 28
1 file changed, 28 insertions(+)
diff --git a/hw/ppc/pnv
On Tue, 11 Mar 2025 at 10:33, Philippe Mathieu-Daudé wrote:
> On 10/3/25 18:28, Peter Maydell wrote:
> > This seems to be because the pl011 code and the chardev
> > code disagree about how "couldn't write anything" is
> > reported. pl011 here is looking for "0 means wrote nothing",
> > but the cha
On Thu, 27 Feb 2025 at 07:32, Jason Chien wrote:
>
> This commit renames the macros to accurately reflect the direction of
> DMA operations.
>
> EDU_DMA_TO_PCI now represents reading memory content into the EDU buffer,
> while EDU_DMA_FROM_PCI represents writing EDU buffer content to memory.
The
Am 13.02.2025 um 19:00 hat Stefan Hajnoczi geschrieben:
> SCSIDevice keeps track of in-flight requests for device reset and Task
> Management Functions (TMFs). The request list requires protection so
> that multi-threaded SCSI emulation can be implemented in commits that
> follow.
>
> Signed-off-b
David Milosevic writes:
> Dear QEMU Developers,
>
> I would like to propose the development of a video subsystem in QEMU, with
> the initial
> implementation focusing on UVC video device emulation and support for multiple
> backends, including V4L2, GStreamer, and libcamera.
>
> This work is alr
Am 13.02.2025 um 19:00 hat Stefan Hajnoczi geschrieben:
> Implement --device virtio-scsi-pci,iothread-vq-mapping= support so that
> virtqueues can be assigned to different IOThreads. This improves SMP guest
> scalability where I/O-intensive applications can become bottlenecked on a
> single IOThrea
The disassembled differences between actual and expected PPTT based on
the following cache topology representation:
- l1d and l1i shared at cluster level
- l2 shared at cluster level
- l3 shared at cluster level
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64
Display refreshment is invoked by a timer and it erroneously disables
the active scanout if it happens to be invoked after scanout has been
enabled. This offending scanout-disable race condition with a timer
can be easily hit when Qemu runs with a disabled vsync by using SDL or
GTK displays (with v
On 3/10/25 14:43, Philippe Mathieu-Daudé wrote:
On 10/3/25 08:37, Cédric Le Goater wrote:
On 3/9/25 00:09, Philippe Mathieu-Daudé wrote:
Convert the compile time check on the CONFIG_VFIO_IGD definition
by a runtime one by calling vfio_igd_builtin(), which check
whether VFIO_IGD is built in a qe
These functions can be invoked by the function that handles interception
of the CHSC SEI instruction for requests indicating the accessibility of
one or more adjunct processors has changed.
Signed-off-by: Rorie Reyes
---
hw/vfio/ap.c | 38
inc
From: John Snow
Add support for the special QAPI doc syntax to process @references as
``preformatted text``. At the moment, there are no actual
cross-references for individual members, so there is nothing to link
against. For now, process it identically to how we did in the old
qapidoc system.
S
From: Stefano Stabellini
On IOREQ_TYPE_INVALIDATE we need to invalidate the mapcache for regular
mappings. Since recently we started reusing the mapcache also to keep
track of grants mappings. However, there is no need to remove grant
mappings on IOREQ_TYPE_INVALIDATE requests, we shouldn't do th
On Mon, Mar 10, 2025 at 12:37 PM Chao Liu wrote:
>
> Hi, Alistair:
>
> I rebase both patches based on the riscv-to-apply.next branch and tested them.
> https://github.com/alistair23/qemu/tree/riscv-to-apply.next
>
> Only the first patch had two conflicts, which were resolved nicely,
> and the seco
Add an futimens operation to the fs driver and use if when a fid has
a valid file descriptor. This is required to support more cases where
the client wants to do an action on an unlinked file which it still
has an open file decriptor for.
Only 9P2000.L was considered.
Signed-off-by: Greg Kurz
--
On Sun, Mar 9, 2025 at 9:00 AM Richard Henderson
wrote:
>
> The third argument of the syscall contains the size of the
> cpu mask in bytes, not bits. Nor is the size rounded up to
> a multiple of sizeof(abi_ulong).
>
> Cc: qemu-sta...@nongnu.org
> Reported-by: Andreas Schwab
> Fixes: 9e1c7d982d7
On Fri, Mar 07, 2025 at 11:16:33PM +0100, Kevin Wolf wrote:
> Signed-off-by: Kevin Wolf
> ---
> util/aio-posix.c | 77 ++--
> 1 file changed, 41 insertions(+), 36 deletions(-)
Reviewed-by: Stefan Hajnoczi
signature.asc
Description: PGP signature
On 10/3/25 14:48, Thomas Huth wrote:
On 10/03/2025 14.45, Daniel P. Berrangé wrote:
On Mon, Mar 10, 2025 at 02:31:17PM +0100, Philippe Mathieu-Daudé wrote:
Allow generic CPUs to dump the architecture storage keys.
Being specific to s390x, it is only implemented there.
Signed-off-by: Philippe
On 10/3/25 19:24, Cédric Le Goater wrote:
On 3/10/25 18:38, Bernhard Beschow wrote:
Am 10. März 2025 17:31:57 UTC schrieb "Philippe Mathieu-Daudé"
:
On 10/3/25 16:56, Guenter Roeck wrote:
On 3/10/25 08:27, Philippe Mathieu-Daudé wrote:
On 10/3/25 15:09, BALATON Zoltan wrote:
On Mon, 10 Ma
Hi Zhao,
On 3/9/25 11:14 PM, Zhao Liu wrote:
> On Sun, Mar 02, 2025 at 02:00:15PM -0800, Dongli Zhang wrote:
>> Date: Sun, 2 Mar 2025 14:00:15 -0800
>> From: Dongli Zhang
>> Subject: [PATCH v2 07/10] target/i386/kvm: query kvm.enable_pmu parameter
>> X-Mailer: git-send-email 2.43.5
>>
>> There i
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
On Mon, 10 Mar 2025, Philippe Mathieu-Daudé wrote:
Import Linux's SDHCI_QUIRK_INVERTED_WRITE_PROTECT quirk definition.
Replace 'wp_inverted' boolean by a bit in quirk bitmask.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 16 ++--
hw/arm/aspeed.c | 2 +-
hw
From: Alex Bennée
This attempts to tidy up the VirtIO GPU documentation to make the list
of requirements clearer. There are still a lot of moving parts and the
distros have some catching up to do before this is all handled
automatically.
Signed-off-by: Alex Bennée
Cc: Sergio Lopez Pascual
Sign
On 3/10/25 21:43, Philippe Mathieu-Daudé wrote:
> On 10/3/25 08:37, Cédric Le Goater wrote:
>> On 3/9/25 00:09, Philippe Mathieu-Daudé wrote:
>>> Convert the compile time check on the CONFIG_VFIO_IGD definition
>>> by a runtime one by calling vfio_igd_builtin(), which check
>>> whether VFIO_IGD is
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/bindings.rs | 3 ---
rust/qemu-api/src/sysbus.rs | 29 +
2 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/rust/qemu-api/src/bindings.rs b/rust/qemu-api/src/bindings.rs
index 6e70a75a0e6..b791ca6d87f
On 3/10/25 09:14, Pierrick Bouvier wrote:
On 3/10/25 09:08, Richard Henderson wrote:
On 3/9/25 21:58, Pierrick Bouvier wrote:
For now, they are duplicate of the same macros in cpu-all.h that we
eliminate in next commit.
Keep code readable by not defining them with macros, but simply their
impl
Since I've just about rewritten the entirety of the QAPI documentation
system, it's probably fair that I be the contact point for if it goes
awry.
Signed-off-by: John Snow
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7ac04f35201..4b83a436d8f
The following changes since commit d9a4282c4b690e45d25c2b933f318bb41eeb271d:
Merge tag 'pull-tcg-20250308' of https://gitlab.com/rth7680/qemu into staging
(2025-03-09 11:45:00 +0800)
are available in the Git repository at:
https://github.com/jasowang/qemu.git tags/net-pull-request
for you
Add a special :ifcond: option that allows us to annotate the
definition-level conditionals.
The syntax of the argument is currently undefined, but it's possible we
can apply better formatting in the future. Currently, we just display
the ifcond string as preformatted text.
Signed-off-by: Harmonie
Allow virtio-scsi virtqueues to be assigned to different IOThreads. This
makes it possible to take advantage of host multi-queue block layer
scalability by assigning virtqueues that have affinity with vCPUs to
different IOThreads that have affinity with host CPUs. The same feature
was introduced fo
On 3/10/25 09:39, Richard Henderson wrote:
On 3/9/25 21:58, Pierrick Bouvier wrote:
Functions declared in bswap.h will be used instead.
At this point, we finished to extract memory API from cpu-all.h, and it
can be called from any common or target dependent code.
Signed-off-by: Pierrick Bouvie
On Mon, 10 Mar 2025, Philippe Mathieu-Daudé wrote:
The previous commit removed the single use of instance
setting the "endianness" property.
Since classes can register their io_ops with correct
endianness, no need to support different ones.
Remove the code related to SDHCIState::endianess field
Signed-off-by: Pierrick Bouvier
---
include/exec/ram_addr.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index 7c011fadd11..098fccb5835 100644
--- a/include/exec/ram_addr.h
+++ b/include/exec/ram_addr.h
@@ -342,7 +34
On 3/9/25 12:09 AM, Philippe Mathieu-Daudé wrote:
> Define TYPE_VFIO_PCI_IGD_LPC_BRIDGE once to help
> following where the QOM type is used in the code.
> We'll use it once more in the next commit.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Eric Auger
Eric
> ---
> hw/vfio/pci-qu
John Snow writes:
> This class is a generic, top-level directive for documenting some kind
> of QAPI thingamajig that we expect to go into the Index. This class
> doesn't do much by itself, and it isn't yet associated with any
> particular directive.
>
> Only handle_signature() is defined in the
On Sun, Mar 09, 2025 at 09:15:00PM -0400, Manish Mishra wrote:
> We allocate extra metadata SKBs in case of a zerocopy send. This metadata
> memory is accounted for in the OPTMEM limit. If there is any error while
> sending zerocopy packets or if zerocopy is skipped, these metadata SKBs are
> queue
On 2/5/25 3:38 AM, Cédric Le Goater wrote:
Are the kernel changes planned for 6.14 ?
FYI, QEMU 10.0 hard freeze is scheduled for 2025-03-18 which is
approximately when 6.14-rc7 will be released.
Thanks,
C.
Vasily - Since you applied my kernel patches already ([RFC PATCH v2]
s390/vfio-ap:
We want to capture potential Rust backtraces on panics in our test
logs, which isn't Rust's default behaviour. Set RUST_BACKTRACE=1 in
the add_test_setup environments, so that all our tests get run with
this environment variable set.
This makes the setting of that variable in the gitlab CI templa
Am 20.02.2025 um 05:05 hat Stefan Hajnoczi geschrieben:
> Getting the GSource for the AioContext stops fdmon-io_uring from working
> because it is not compatible with the glib event loop. Defer the GSource
> code until the glib event loop is actually used. For typical IOThreads
> this may never be
On Fri, Mar 07, 2025 at 10:42:03AM -0300, Fabiano Rosas wrote:
> The current migration compression documentation applies only to
> multifd. Now that we have a multifd section, move the compression
> documentation under it.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: Peter Xu
--
Peter Xu
On Tue Dec 10, 2024 at 10:05 AM AEST, Michael Kowal wrote:
> Renamed function to follow the convention of the other function names.
>
> Signed-off-by: Michael Kowal
Reviewed-by: Nicholas Piggin
> ---
> include/hw/ppc/xive.h | 16
> hw/intc/xive.c| 22 ++
Both x-igd-opregion option and legacy mode require identical steps to
set up OpRegion for IGD devices. Consolidate these steps into a single
vfio_pci_igd_setup_opregion function.
The function call in pci.c is wrapped with ifdef temporarily to prevent
build error for non-x86 archs, it will be remov
we'll use it in system/memory.c.
Signed-off-by: Pierrick Bouvier
---
include/exec/memory.h | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 60c0fb6ccd4..57661283684 100644
--- a/include/exec/memory.h
+++ b
On 3/10/25 15:59, Aditya Gupta wrote:
On 10/03/25 17:15, Cédric Le Goater wrote:
On 3/10/25 11:31, Aditya Gupta wrote:
<...snip...>
pc-bios/skiboot.lid | Bin 2527328 -> 2527424 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
This change should come first as a sub maintainer PR, to a
Support three main memory space types:
* Physical memory
* Logical memory (MMU)
* GDB Registers
Use custom memory type to mark memory spaces as secure
V=1 QTEST_QEMU_BINARY="./qemu-system-arm -M virt,secure=on -cpu cortex-a15"
tests/qtest/mcd-test
Signed-off-by: Mario Fleischmann
---
mcd/lib
On Mon, 10 Mar 2025 at 09:40, Paolo Bonzini wrote:
>
> On Mon, Mar 10, 2025 at 10:25 AM Daniel P. Berrangé
> wrote:
> > > This will only add the rust backtraces when the tests
> > > are run from the CI logs, not when you locally run
> > > "make check" or similar. There's probably a better place
This method annotates the start of a new module, crediting the source
location to the first line of the module file.
Signed-off-by: John Snow
---
docs/sphinx/qapidoc.py | 9 +
1 file changed, 9 insertions(+)
diff --git a/docs/sphinx/qapidoc.py b/docs/sphinx/qapidoc.py
index c243bb6faaa.
The following changes since commit e8a01102936286e012ed0f00bd7f3b7474d415c9:
Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into
staging (2025-03-05 21:58:23 +0800)
are available in the Git repository at:
https://repo.or.cz/qemu/armbru.git tags/pull-qapi-2025-03-06
These are only usable in system mode where we control the timer. For
user-mode make them NOPs.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Message-Id: <20250304222439.2035603-29-alex.ben...@linaro.org>
diff --git a/plugins/api-system.c b/plugins/api-system.c
index 38560de342..cc19
On Thu, 6 Mar 2025 02:33:37 +
Alireza Sanaee via wrote:
> OS like Linux is using PPTT processor node's identical implementation
> flag [1] to infer whether the whole system or a certain CPU cluster is
> homogeneous or not [2]. QEMU currently only support building
> homogeneous system, set the
This is needed for next commits (especially when implementing st/ld
primitives which will use this function).
As well, remove reference to TARGET_BIG_ENDIAN, as we are about to
remove this dependency.
Signed-off-by: Pierrick Bouvier
---
include/exec/tswap.h | 11 ---
include/qemu/bswap.h
SDL API changes GL context to a newly created GL context, which differs
from other GL providers that don't switch context. Change SDL backend to
restore the original GL context. This allows Qemu's virtio-gpu to support
new virglrenderer async-fencing feature for Virgl contexts, otherwise
virglrende
Virtqueues are not thread-safe. Until now this was not a major issue
since all virtqueue processing happened in the same thread. The ctrl
queue's Task Management Function (TMF) requests sometimes need the main
loop, so a BH was used to schedule the virtqueue completion back in the
thread that has v
Enhance the `use-after-unlink` test with a new check for the
case where the client wants to alter the size of an unlinked
file for which it still has an active fid.
Suggested-by: Christian Schoenebeck
Signed-off-by: Greg Kurz
---
tests/qtest/virtio-9p-test.c | 8
1 file changed, 8 inse
On 3/11/25 09:28, Cornelia Huck wrote:
From: Eric Auger
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate
On 3/11/25 09:28, Cornelia Huck wrote:
+/* read a sysreg value and store it in the idregs */
+static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, ARMIDRegisterIdx
index)
This still isn't used, and so must Werror.
r~
On 3/11/25 09:28, Cornelia Huck wrote:
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 57 ---
target/arm/cpu.c | 10 +++
target/arm/cpu.h | 2 --
target/arm/cpu64.c|
On 3/11/25 09:28, Cornelia Huck wrote:
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 44 +++
target/arm/cpu.c | 12 ---
target/arm/cpu.h | 2 --
target/arm/cpu64.c
On 3/11/25 09:28, Cornelia Huck wrote:
From: Eric Auger
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 40 -
target/arm/cpu.c | 29
target/arm/cpu.h | 2 --
target/arm/cpu64.c
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