Re: [PATCH v2] hw/sd/sdhci: Set reset value of interrupt registers

2025-03-06 Thread BALATON Zoltan
On Mon, 3 Mar 2025, BALATON Zoltan wrote: On Mon, 3 Mar 2025, Philippe Mathieu-Daudé wrote: Hi Zoltan, On 10/2/25 17:03, BALATON Zoltan wrote: The interrupt enable registers are not reset to 0 on Freescale eSDHC but some bits are enabled on reset. At least some U-Boot versions seem to expect t

Re: [RFC PATCH 0/5] hw/arm/virt: Add support for user-creatable nested SMMUv3

2025-03-06 Thread Eric Auger
Hi Shameer, On 3/6/25 7:27 PM, Shameerali Kolothum Thodi wrote: > >> -Original Message- >> From: Eric Auger >> Sent: Thursday, March 6, 2025 6:00 PM >> To: Shameerali Kolothum Thodi >> ; Duan, Zhenzhong >> ; Nicolin Chen ; >> Donald Dutile >> Cc: Peter Maydell ; Jason Gunthorpe >> ; Dani

[PULL 30/54] target/i386/hvf: Variable type fixup in decoder

2025-03-06 Thread Philippe Mathieu-Daudé
From: Phil Dennis-Jordan decode_bytes reads 1, 2, 4, or 8 bytes at a time. The destination variable should therefore be a uint64_t, not a target_ulong. Signed-off-by: Phil Dennis-Jordan Fixes: ff2de1668c9 ("i386: hvf: remove addr_t") Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20241209203

Re: [PATCH rfcv2 06/20] host_iommu_device: Define two new capabilities HOST_IOMMU_DEVICE_CAP_[NESTING|FS1GP]

2025-03-06 Thread Nicolin Chen
On Thu, Mar 06, 2025 at 04:59:39PM +0100, Eric Auger wrote: > >>> +++ b/include/system/host_iommu_device.h > >>> @@ -22,10 +22,16 @@ > >>> * > >>> * @hw_caps: host platform IOMMU capabilities (e.g. on IOMMUFD this > >> represents > >>> * the @out_capabilities value returned from IOM

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