On Thu, Mar 06, 2025 at 10:53:06AM +, Alex Bennée wrote:
> This option is supported by both gcc (since 4.7) and clang (since
> 7.0). Not only does this make the linkers job easier by reducing the
> amount of ELF it needs to parse it also reduces the total build size
> quite considerably. In my
From: "Maciej S. Szmigiero"
This SaveVMHandler helps device provide its own asynchronous transmission
of the remaining data at the end of a precopy phase via multifd channels,
in parallel with the transfer done by save_live_complete_precopy handlers.
These threads are launched only when multifd
From: "Maciej S. Szmigiero"
And rename existing load_device_config_state trace event to
load_device_config_state_end for consistency since it is triggered at the
end of loading of the VFIO device config state.
This way both the start and end points of particular device config
loading operation (
From: "Maciej S. Szmigiero"
These names conflict with ones used by future generic thread pool
equivalents.
Generic names should belong to the generic pool type, not specific (AIO)
type.
Acked-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Reviewed-by: Peter Xu
Signed-off-by: Maciej S. Szmigi
From: Alex Williamson
This is now redundant to PCIDevice.pm_cap.
Cc: Cédric Le Goater
Reviewed-by: Zhenzhong Duan
Reviewed-by: Eric Auger
Signed-off-by: Alex Williamson
Reviewed-by: Michael S. Tsirkin
Link:
https://lore.kernel.org/qemu-devel/20250225215237.3314011-4-alex.william...@redhat.
From: "Maciej S. Szmigiero"
Automatic memory management helps avoid memory safety issues.
Reviewed-by: Peter Xu
Signed-off-by: Maciej S. Szmigiero
Link:
https://lore.kernel.org/qemu-devel/a5843c5fa64d7e5239a4316092ec0ef0d10c2320.1741124640.git.maciej.szmigi...@oracle.com
Signed-off-by: Cédric
From: Eric Auger
As an outcome of KVM forum 2024 "vfio-platform: live and let die?"
talk, let's deprecate vfio-platform devices.
Signed-off-by: Eric Auger
Reviewed-by: Cédric Le Goater
Link:
https://lore.kernel.org/qemu-devel/20250305124225.952791-1-eric.au...@redhat.com
[ clg: Fixed spelling
From: "Maciej S. Szmigiero"
This way they can also be referenced in other translation
units than migration.c.
Reviewed-by: Cédric Le Goater
Signed-off-by: Maciej S. Szmigiero
Link:
https://lore.kernel.org/qemu-devel/26a940f6b22c1b685818251b7a3ddbbca601b1d6.1741124640.git.maciej.szmigi...@orac
From: "Maciej S. Szmigiero"
This way if there are fields there that needs explicit disposal (like, for
example, some attached buffers) they will be handled appropriately.
Add a related assert to multifd_set_payload_type() in order to make sure
that this function is only used to fill a previously
From: "Maciej S. Szmigiero"
Add vfio_multifd_transfer_supported() function that tells whether the
multifd device state transfer is supported.
Reviewed-by: Cédric Le Goater
Signed-off-by: Maciej S. Szmigiero
Link:
https://lore.kernel.org/qemu-devel/8ce50256f341b3d47342bb217cb5fbb2deb14639.1741
From: "Maciej S. Szmigiero"
multifd_send() function is currently not thread safe, make it thread safe
by holding a lock during its execution.
This way it will be possible to safely call it concurrently from multiple
threads.
Reviewed-by: Peter Xu
Signed-off-by: Maciej S. Szmigiero
Link:
http
From: Alex Williamson
We want the device in the D0 power state going into reset, but the
config write can enable the BARs in the address space, which are
then removed from the address space once we clear the memory enable
bit in the command register. Re-order to clear the command bit
first, so t
From: "Maciej S. Szmigiero"
This function name conflicts with one used by a future generic thread pool
function and it was only used by one test anyway.
Update the trace event name in thread_pool_submit_aio() accordingly.
Acked-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Reviewed-by: Pete
From: "Maciej S. Szmigiero"
Automatic memory management helps avoid memory safety issues.
Reviewed-by: Fabiano Rosas
Reviewed-by: Peter Xu
Signed-off-by: Maciej S. Szmigiero
Link:
https://lore.kernel.org/qemu-devel/2fd01d773a783d572dcf538a064a98cc09e75c12.1741124640.git.maciej.szmigi...@orac
From: "Maciej S. Szmigiero"
Add a thread which loads the VFIO device state buffers that were received
via multifd.
Each VFIO device that has multifd device state transfer enabled has one
such thread, which is created using migration core API
qemu_loadvm_start_load_thread().
Since it's important
From: "Maciej S. Szmigiero"
The multifd received data needs to be reassembled since device state
packets sent via different multifd channels can arrive out-of-order.
Therefore, each VFIO device state packet carries a header indicating its
position in the stream.
The raw device state data is save
From: "Maciej S. Szmigiero"
This property allows configuring whether to transfer the particular device
state via multifd channels when live migrating that device.
It defaults to AUTO, which means that VFIO device state transfer via
multifd channels is attempted in configurations that otherwise s
From: "Maciej S. Szmigiero"
Load device config received via multifd using the existing machinery
behind vfio_load_device_config_state().
Also, make sure to process the relevant main migration channel flags.
Signed-off-by: Maciej S. Szmigiero
Reviewed-by: Cédric Le Goater
Link:
https://lore.k
From: "Maciej S. Szmigiero"
Add multifd setup/cleanup functions and an associated VFIOMultifd data
structure that will contain most of the receive-side data together
with its init/cleanup methods.
Signed-off-by: Maciej S. Szmigiero
Reviewed-by: Cédric Le Goater
Link:
https://lore.kernel.org/q
From: "Maciej S. Szmigiero"
So it can be safety accessed from multiple threads.
This variable type needs to be changed to unsigned long since
32-bit host platforms lack the necessary addition atomics on 64-bit
variables.
Using 32-bit counters on 32-bit host platforms should not be a problem
in
From: "Maciej S. Szmigiero"
Wire VFIO multifd transfer specific setup and cleanup functions into
general VFIO load/save setup and cleanup methods.
Signed-off-by: Maciej S. Szmigiero
Reviewed-by: Cédric Le Goater
Link:
https://lore.kernel.org/qemu-devel/b1f864a65fafd4fdab1f89230df52e46ae41f2ac
This update introduces support for handling multi-output IRQs in the AST2700
interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps
1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a
specific IRQ.
Implemented "aspeed_intc_set_irq_handler_multi_out
On 3/6/25 15:23, Avihai Horon wrote:
On 06/03/2025 16:13, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
On 6.03.2025 14:37, Avihai Horon wrote:
On 06/03/2025 12:32, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
On 3
The following changes since commit e8a01102936286e012ed0f00bd7f3b7474d415c9:
Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into
staging (2025-03-05 21:58:23 +0800)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-vfi
Currently, the size of the "regs" array is 0x2000, which is too large. To save
code size and avoid mapping large unused gaps, will update it to only map the
useful set of registers. This update will support multiple sub-regions with
different sizes.
To address the redundant size issue, replace the
On 3/6/25 11:38, Jamin Lin wrote:
Currently, the size of the regs array is 0x2000, which is too large. So far,
it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000 are unused.
To save code size, introduce a new class attribute "reg_size" to set the
different register sizes for the
Jamin,
On 3/6/25 11:38, Jamin Lin wrote:
v1:
1. Refactor INTC model to support both INTC0 and INTC1.
2. Support AST2700 A1.
3. Create ast2700a0-evb machine.
v2:
To streamline the review process, split the following patch series into
three parts.
https://patchwork.kernel.org/p
On Thu, 6 Mar 2025, Daniel P. Berrangé wrote:
On Thu, Mar 06, 2025 at 02:45:52PM +0100, BALATON Zoltan wrote:
On Thu, 6 Mar 2025, Daniel P. Berrangé wrote:
On Thu, Mar 06, 2025 at 12:34:13PM +0100, Paolo Bonzini wrote:
Il gio 6 mar 2025, 10:27 Philippe Mathieu-Daudé ha
scritto:
This API is
The behavior of the enable and status registers is almost identical between
INTC(CPU Die) and INTCIO(IO Die). To reduce duplicated code, adds
"aspeed_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_intc_status_handler" functions to handle status
register write be
On Thu, 2025-03-06 at 15:06 +, Daniel P. Berrangé wrote:
> BTW, your email client is possibly mis-configured - your mail
> came through with "From: shalini "
> and attempting to reply to that gets an error saying that
> 'imap.linux.ibm.com' does not exist.
>
> On Thu, Mar 06, 2025 at 02:55:27P
On Wed, 2025-03-05 at 16:47 +0100, Stefano Garzarella wrote:
> Hi Roy,
>
> I was testing this series with the IGVM file generated by COCONUT SVSM,
> but QEMU was failing in this way:
>
> qemu-system-x86_64: KVM does not support guest_memfd
> qemu-system-x86_64: failed to initialize kvm: Op
On 30/1/25 14:43, Cédric Le Goater wrote:
Print a warning if IOMMU address space width is smaller than the
physical address width. In this case, PCI peer-to-peer transactions on
BARs are not supported and failures of device MMIO regions are to be
expected.
This can occur with the 39-bit IOMMU ad
Modified the temperature hwmon path to use a wildcard to handle different SDK
versions: "cat /sys/bus/i2c/devices/1-004d/hwmon/hwmon*/temp1_input".
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/f
Markus Armbruster writes:
> John Snow writes:
>
>> Hi! This series is based on armbru/pull-qapi-2025-02-26.
>>
>> This series is a "minimum viable" version of the new QAPI documentation
>> system. It does the bare minimum under the new framework, saving nice
>> features for later.
>
> Not saved
On Thu, Mar 6, 2025 at 2:13 AM Alistair Francis wrote:
>
> On Wed, Feb 19, 2025 at 2:58 AM Paolo Bonzini wrote:
> >
> > Do not create the RHCT MMU type entry for RV32 CPUs, since it
> > only has definitions for SV39/SV48/SV57. Likewise, check that
>
> I don't have access to the spec, so I'm goin
On Wed, Mar 05, 2025 at 05:56:46PM -0800, Richard Henderson wrote:
> On 3/5/25 07:39, Philippe Mathieu-Daudé wrote:
> > +void legacy_binary_info_init(const char *argv0)
> > +{
> > +g_auto(GStrv) tokens = g_strsplit(argv0, G_DIR_SEPARATOR_S, -1);
> > +unsigned count = 0;
> > +const char
Paolo Bonzini writes:
> Il gio 6 mar 2025, 11:53 Alex Bennée ha scritto:
>
> -option_cflags = (get_option('debug') ? ['-g'] : [])
> +option_cflags = []
> +if get_option('debug')
> + option_cflags += get_option('split_debug') ? ['-gsplit-dwarf'] : ['-g']
> +endif
>
> option_cflags does noth
Hi Roy,
On Thu, Mar 06, 2025 at 11:48:29AM +, Roy Hopkins wrote:
On Wed, 2025-03-05 at 16:47 +0100, Stefano Garzarella wrote:
[...]
Thanks for testing this. The problem seems to be down to the fact that I
had to introduce an initial parsing of the IGVM file during initialization
to extr
From: "Maciej S. Szmigiero"
DEFINE_PROP_ON_OFF_AUTO() property isn't runtime-mutable so using it
would mean that the source VM would need to decide upfront at startup
time whether it wants to do a multifd device state transfer at some
point.
Source VM can run for a long time before being migrate
From: "Maciej S. Szmigiero"
Add basic types and flags used by VFIO multifd device state transfer
support.
Since we'll be introducing a lot of multifd transfer specific code,
add a new file migration-multifd.c to home it, wired into main VFIO
migration code (migration.c) via migration-multifd.h h
From: "Maciej S. Szmigiero"
Read packet header first so in the future we will be able to
differentiate between a RAM multifd packet and a device state multifd
packet.
Since these two are of different size we can't read the packet body until
we know which packet type it is.
Reviewed-by: Fabiano
Paolo Bonzini writes:
> Il gio 6 mar 2025, 13:20 Alex Bennée ha scritto:
>
> Paolo Bonzini writes:
>
> > Il gio 6 mar 2025, 11:53 Alex Bennée ha scritto:
> >
> > -option_cflags = (get_option('debug') ? ['-g'] : [])
> > +option_cflags = []
> > +if get_option('debug')
> > + option_cf
Add an entry for docs/devel/testing/functional.rst to get notified
on patches that change this file.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f4fe1777afb..711283bf5f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
On Thu, Mar 6, 2025, 7:35 AM Markus Armbruster wrote:
> When I eyeballed the previous iteration, I made a few observations[1].
> Let's see what has changed.
>
> } New table of contents shows one level, old two. No objection; the
> } navigation thingie on the left is more useful anyway.
>
> No ch
On 3/6/25 11:38, Jamin Lin wrote:
Rename the variables "status_addr" to "status_reg" and "addr" to "reg" because
they are used as register index. This change makes the code more appropriate
and improves readability.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
BTW, your email client is possibly mis-configured - your mail
came through with "From: shalini "
and attempting to reply to that gets an error saying that
'imap.linux.ibm.com' does not exist.
On Thu, Mar 06, 2025 at 02:55:27PM +0100, shalini wrote:
> On 2025-03-05 17:06, Daniel P. Berrangé wrote:
On 06/03/2025 15.10, shalini wrote:
On 2025-03-05 19:33, Thomas Huth wrote:
On 24/02/2025 13.04, Shalini Chellathurai Saroja wrote:
Register Control-Program Identification data with the live
migration infrastructure.
Signed-off-by: Shalini Chellathurai Saroja
Reviewed-by: Nina Schoetterl-Glau
On 3/6/25 11:38, Jamin Lin wrote:
The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ
p
On 3/6/25 11:38, Jamin Lin wrote:
This update introduces support for handling multi-output IRQs in the AST2700
interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps
1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a
specific IRQ.
Implemented "a
On 3/6/25 11:38, Jamin Lin wrote:
The design of INTC controllers has significantly changed in AST2700 A1.
There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of pro
On 3/6/25 11:38, Jamin Lin wrote:
Updated Aspeed27x0SoCState to include an intc[2] array instead of a single
AspeedINTCState instance. Modified aspeed_soc_ast2700_get_irq and
aspeed_soc_ast2700_get_irq_index to correctly reference the corresponding
interrupt controller instance and OR gate index.
On 3/6/25 11:38, Jamin Lin wrote:
To improve readability, sort the memmap table by mapping address
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/aspeed_ast27x0.c | 54 -
1 file changed, 27 insertions(+), 27 delet
On Thu, Mar 06, 2025 at 02:45:52PM +0100, BALATON Zoltan wrote:
> On Thu, 6 Mar 2025, Daniel P. Berrangé wrote:
> > On Thu, Mar 06, 2025 at 12:34:13PM +0100, Paolo Bonzini wrote:
> > > Il gio 6 mar 2025, 10:27 Philippe Mathieu-Daudé ha
> > > scritto:
> > >
> > > > This API is to allow refactoring
On 3/6/25 11:38, Jamin Lin wrote:
Currently, the size of the "regs" array is 0x2000, which is too large. To save
code size and avoid mapping large unused gaps, will update it to only map the
useful set of registers. This update will support multiple sub-regions with
different sizes.
To address t
Am 04.03.2025 um 16:52 hat Alberto Faria geschrieben:
> Avoid emulating FUA when the driver supports it natively. This should
> provide better performance than a full flush after the write.
>
> Signed-off-by: Alberto Faria
Did you try out if you can see performance improvements in practice?
It's
To improve readability, sort the memmap table by mapping address
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 54 -
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 7439512b83
In ASPEED SDK v09.05, the naming convention for pre-built images has been
updated. The pre-built image for AST2700 A0 has been renamed to
ast2700-a0-default, while ast2700-default is now used for AST2700 A1.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/functional/test_aarch6
This option is supported by both gcc (since 4.7) and clang (since
7.0). Not only does this make the linkers job easier by reducing the
amount of ELF it needs to parse it also reduces the total build size
quite considerably. In my case a default build went from 5.8G to 3.9G.
The --disable-split-deb
On 6/3/25 11:51, Thomas Huth wrote:
Add an entry for docs/devel/testing/functional.rst to get notified
on patches that change this file.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Philippe Mathieu-Daudé
On 10/2/25 22:29, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (10):
target: Set disassemble_info::endian value for little-endian targets
target: Set disassemble_info::endian value for big-endian targets
target/arm: Set disassemble_info::endian value in disas_set_info()
targe
On 2025-03-05 19:05, Thomas Huth wrote:
On 24/02/2025 13.04, Shalini Chellathurai Saroja wrote:
Add Control-Program Identification (CPI) to the QEMU Object
Model (QOM). The CPI identifiers provide information about
the guest operating system. The CPI identifiers are:
system type, system name, sy
On 6/3/25 14:58, Philippe Mathieu-Daudé wrote:
On 10/2/25 22:29, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (10):
target: Set disassemble_info::endian value for little-endian targets
target: Set disassemble_info::endian value for big-endian targets
target/arm: Set disassemble
24.01.2025 12:05, Max Chou wrote:
In prop_vlen_set function, there is an incorrect comparison between
vlen(bit) and vlenb(byte).
This will cause unexpected error when user applies the `vlen=1024` cpu
option with a vendor predefined cpu type that the default vlen is
1024(vlenb=128).
Is this a qe
On 15/1/25 00:13, Philippe Mathieu-Daudé wrote:
OpenRISC timer is architecturally tied to the CPU.
It doesn't belong to the machine init() code to
instanciate it: move its creation when a vCPU is
realized (after being created).
Reported-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
On 6/3/25 08:28, Thomas Huth wrote:
On 05/03/2025 16.39, Philippe Mathieu-Daudé wrote:
Introduce legacy_binary_endianness() to return the endianness
of a legacy binary, and legacy_binary_is_big_endian() being
equivalent of compile time TARGET_BIG_ENDIAN definition.
Signed-off-by: Philippe Mathi
On 2025-03-05 19:33, Thomas Huth wrote:
On 24/02/2025 13.04, Shalini Chellathurai Saroja wrote:
Register Control-Program Identification data with the live
migration infrastructure.
Signed-off-by: Shalini Chellathurai Saroja
Reviewed-by: Nina Schoetterl-Glausch
---
hw/s390x/s390-virtio-ccw.c
On 6.03.2025 14:37, Avihai Horon wrote:
On 06/03/2025 12:32, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
On 3/6/25 11:15, Maciej S. Szmigiero wrote:
On 6.03.2025 07:47, Avihai Horon wrote:
On 05/03/2025 0:03, Maciej S. Szmigiero wrote:
External email:
From: Alex Williamson
The memory and IO BARs for devices are only accessible in the D0 power
state. In other power states the PCI spec defines that the device
responds to TLPs and messages with an Unsupported Request response.
To approximate this behavior, consider the BARs as unmapped when the
On 06/03/2025 12:32, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
On 3/6/25 11:15, Maciej S. Szmigiero wrote:
On 6.03.2025 07:47, Avihai Horon wrote:
On 05/03/2025 0:03, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC (CPU Die).
To support the INTCIO (IO Die) model, introduces
From: "Maciej S. Szmigiero"
qemu_loadvm_load_state_buffer() and its load_state_buffer
SaveVMHandler allow providing device state buffer to explicitly
specified device via its idstr and instance id.
Reviewed-by: Fabiano Rosas
Reviewed-by: Peter Xu
Signed-off-by: Maciej S. Szmigiero
Link:
http
From: "Maciej S. Szmigiero"
This QEMU_VM_COMMAND sub-command and its switchover_start SaveVMHandler is
used to mark the switchover point in main migration stream.
It can be used to inform the destination that all pre-switchover main
migration stream data has been sent/received so it can start to
From: "Maciej S. Szmigiero"
Migration code wants to manage device data sending threads in one place.
QEMU has an existing thread pool implementation, however it is limited
to queuing AIO operations only and essentially has a 1:1 mapping between
the current AioContext and the AIO ThreadPool in us
Use the common helper warn_report_once() instead of implementing its
own.
Cc: Eric Farman
Reviewed-by: Eric Farman
Link: https://lore.kernel.org/qemu-devel/20250214161936.1720039-1-...@redhat.com
Signed-off-by: Cédric Le Goater
---
hw/vfio/ccw.c | 12 ++--
1 file changed, 2 insertions(
From: Alex Williamson
The pm_cap on the PCIExpressDevice object can be distilled down
to the new instance on the PCIDevice object.
Cc: Michael S. Tsirkin
Cc: Marcel Apfelbaum
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Zhenzhong Duan
Reviewed-by: Eric Auger
Signed-off-by: Alex Williamson
From: Alex Williamson
Switch callers directly initializing the PCI PM capability with
pci_add_capability() to use pci_pm_init().
Cc: Dmitry Fleytman
Cc: Akihiko Odaki
Cc: Jason Wang
Cc: Stefan Weil
Cc: Sriram Yagnaraman
Cc: Keith Busch
Cc: Klaus Jensen
Cc: Jesper Devantier
Cc: Michael S.
From: "Maciej S. Szmigiero"
Add a basic support for receiving device state via multifd channels -
channels that are shared with RAM transfers.
Depending whether MULTIFD_FLAG_DEVICE_STATE flag is present or not in the
packet header either device state (MultiFDPacketDeviceState_t) or RAM
data (exi
From: "Maciej S. Szmigiero"
It's possible for {load,save}_cleanup SaveVMHandlers to get called without
the corresponding {load,save}_setup handler being called first.
One such example is if {load,save}_setup handler of a proceeding device
returns error.
In this case the migration core cleanup co
According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB
(0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.
Signed-off-by: Jam
Il gio 6 mar 2025, 10:27 Philippe Mathieu-Daudé ha
scritto:
> This API is to allow refactoring code for heterogeneous emulation,
> without changing user-facing behavior of current qemu-system binaries,
> which I now consider as 'legacy'.
>
> Once all current restrictions removed, the new qemu-sys
When I eyeballed the previous iteration, I made a few observations[1].
Let's see what has changed.
} New table of contents shows one level, old two. No objection; the
} navigation thingie on the left is more useful anyway.
No change. Okay.
} The new generator elides unreferenced types. Genera
Il gio 6 mar 2025, 13:20 Alex Bennée ha scritto:
> Paolo Bonzini writes:
>
> > Il gio 6 mar 2025, 11:53 Alex Bennée ha
> scritto:
> >
> > -option_cflags = (get_option('debug') ? ['-g'] : [])
> > +option_cflags = []
> > +if get_option('debug')
> > + option_cflags += get_option('split_debug'
On Thu, Mar 6, 2025 at 4:27 PM Michael Tokarev wrote:
>
> 24.01.2025 13:14, Max Chou wrote:
> > According to the Vector Reduction Operations section in the RISC-V "V"
> > Vector Extension spec,
> > "If vl=0, no operation is performed and the destination register is not
> > updated."
> >
> > The vd
On Thu, 6 Mar 2025, Daniel P. Berrangé wrote:
On Thu, Mar 06, 2025 at 12:34:13PM +0100, Paolo Bonzini wrote:
Il gio 6 mar 2025, 10:27 Philippe Mathieu-Daudé ha
scritto:
This API is to allow refactoring code for heterogeneous emulation,
without changing user-facing behavior of current qemu-sys
Prasad Pandit writes:
> Hello Fabiano,
>
> On Wed, 5 Mar 2025 at 19:26, Fabiano Rosas wrote:
>> Note that none of this is out of the ordinary, you'll find such
>> discussions in any thread on this community. It may feel arbitrary to
>> you because that's tacit knowledge we gathered along the yea
On Thu, 2025-03-06 at 15:55 +0100, Thomas Huth wrote:
> On 06/03/2025 13.23, shalini wrote:
> > On 2025-03-05 16:56, Thomas Huth wrote:
> > > On 24/02/2025 13.04, Shalini Chellathurai Saroja wrote:
> > > > Add Control-Program Identification (CPI) to the QEMU Object
> > > > Model (QOM). The CPI iden
We already have "qemu/compiler.h" for compiler-specific arrangements,
automatically included by "qemu/osdep.h" for each source file. No
need to explicitly include a header for a Clang particularity.
Suggested-by: Pierrick Bouvier
Reviewed-by: Pierrick Bouvier
Reviewed-by: Alex Bennée
Reviewed-b
From: Philippe Mathieu-Daudé
There is no generic acceleration, we have to use specific
implementations. Make the base class abstract.
Fixes: b14a0b7469fa ("accel: Use QOM classes for accel types")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cornelia Huck
Message-Id: <20200129212345.2054
On Thu, Mar 6, 2025 at 4:12 PM Deepak Gupta wrote:
>
> On Thu, Mar 06, 2025 at 03:20:55PM +1000, Alistair Francis wrote:
> >On Tue, Feb 18, 2025 at 12:56 PM Deepak Gupta wrote:
> >>
> >> Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for
> >> zicfiss") introduced CSR_SSP but i
On 11/2/25 17:26, Philippe Mathieu-Daudé wrote:
get_float_exception_flags() returns exception flags,
which are distinct from the FPCR bits used as error code.
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: <20250211130626.3940412-1-peter.mayd...@linaro.org>
---
target/alpha/fpu_helper.c
Investigate the git history to uncover when and why the VFIO
properties were introduced and update the models. This is mostly
targeting vfio-pci device, since vfio-platform, vfio-ap and vfio-ccw
devices are simpler.
Sort the properties based on the QEMU version in which they were
introduced.
Cc:
The following changes since commit e8a01102936286e012ed0f00bd7f3b7474d415c9:
Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into
staging (2025-03-05 21:58:23 +0800)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/accel-cpu
Cache CPUClass as early as possible, when the instance
is initialized.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250123234415.59850-5-phi...@linaro.org>
---
cpu-target.c | 3 ---
hw/core/cpu-common.c | 3 +++
2 files changed, 3 insertions(+), 3
cpu_common_initfn() is our target agnostic initializer,
while cpu_exec_initfn() is the target specific one.
The %as and %num_ases fields are not target specific,
so initialize them in the common helper.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <2025012323
cflags_next_tb is always re-initialized in the CPU Reset()
handler in cpu_common_reset_hold(), no need to initialize
it in cpu_common_initfn().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20240427155714.53669-13-phi...@linaro.org>
---
hw/core/cpu-common.c |
Move CPU TLB related methods to accel/tcg/ scope,
in "internal-common.h".
Suggested-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250123234415.59850-9-phi...@linaro.org>
---
accel/tcg/internal-common.h |
Both CPUClass::gdb_read_register() and CPUClass::gdb_write_register()
handlers are called from common gdbstub code, and won't be called with
register index over CPUClass::gdb_num_core_regs:
int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
CPUClass *cc = CPU_GET_CLASS(cpu)
All callers of do_load() / do_store() set MO_TE flag.
Set it once in the callees.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20241105130431.22564-15-phi...@linaro.org>
---
target/microblaze/translate.c | 36 +++
1 file chang
AccelCPUClass is for accelerator to initialize target specific
features of a vCPU. Not really related to hardware emulation,
rename "hw/core/accel-cpu.h" as "accel/accel-cpu-target.h"
(using the explicit -target suffix).
More importantly, target specific header often access the
target specific def
Currently only user emulation is supported.
Assert no target code is built for system emulation.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Brian Cain
Message-Id: <20250121142341.17001-2-phi...@linaro.org>
---
target/hexagon/cpu.h | 4
1 file changed, 4 insertions(+)
diff --git a/
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