On Tue, Feb 18, 2025 at 12:57 PM Deepak Gupta wrote:
>
> Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
> `ssamoswap` instruction. `ssamoswap` takes the code-point from existing
> reserved encoding (and not a zimop like other shadow stack instructions).
> If shadow stack
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three layers of caches and modifies
the cache description registers accordingly.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
target/arm/tcg/cpu64.c | 13 +
Specify which layer (core/cluster/socket) caches found at in the CPU
topology. Updating cache topology to device tree (spec v0.4).
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d an
On Thu, Mar 6, 2025 at 3:48 PM Alistair Francis wrote:
>
> On Mon, Mar 3, 2025 at 7:39 PM Florian Lugou
> wrote:
> >
> > scontext size is 16 bits on RV32 and 32 bits on RV64, as recommended by
> > version 1.0 2025-02-21 of the debug specification.
>
> Section 5.7.8 indicates the register is XLEN
Prepare to update `build_pptt` function to add cache description
functionalities, thus add binaries in this patch.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/test
Test new PPTT topolopy with cache representation.
Signed-off-by: Alireza Sanaee
Reviewed-by: Jonathan Cameron
---
tests/qtest/bios-tables-test.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 0a333ec435..6bdc25f4df 1
On Thu, Mar 6, 2025 at 4:13 PM Deepak Gupta wrote:
>
> On Thu, Mar 06, 2025 at 03:29:00PM +1000, Alistair Francis wrote:
> >On Tue, Feb 18, 2025 at 12:57 PM Deepak Gupta wrote:
> >>
> >> Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
> >> `ssamoswap` instruction. `ssamo
On Mon, Mar 3, 2025 at 7:38 PM Florian Lugou
wrote:
>
> Support setting textra32.sselect or textra64.sselect to 1 (scontext).
> The trigger will only match if the content of scontext matches the value
> in svalue, after it is masked as configured in sbytemask.
I don't think this matches the 0.13
DEFINE_PROP_ON_OFF_AUTO_BIT64() corresponds to DEFINE_PROP_ON_OFF_AUTO()
as DEFINE_PROP_BIT64() corresponds to DEFINE_PROP_BOOL(). The difference
is that DEFINE_PROP_ON_OFF_AUTO_BIT64() exposes OnOffAuto instead of
bool.
Signed-off-by: Akihiko Odaki
---
include/hw/qdev-properties.h | 18
06.03.2025 09:28, Michael Tokarev wrote:
... how important it is to pick it up for 8.2 and 7.2 series,
where the patch does not apply directly?
Scratch this. It is applicable for 9.2 only (from the currently
active stable series), b/c it fixes a commit after 8.2
Thanks,
/mjt
Replace TARGET_PAGE.* by runtime calls.
Signed-off-by: Pierrick Bouvier
---
hw/hyperv/vmbus.c | 50 +--
hw/hyperv/meson.build | 2 +-
2 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c
index 12a7dc43
Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
`ssamoswap` instruction. `ssamoswap` takes the code-point from existing
reserved encoding (and not a zimop like other shadow stack instructions).
If shadow stack is not enabled (via xenvcfg.SSE) and effective priv is
less tha
Signed-off-by: Pierrick Bouvier
---
include/hw/hyperv/hyperv.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/hw/hyperv/hyperv.h b/include/hw/hyperv/hyperv.h
index d717b4e13d4..c6f7039447f 100644
--- a/include/hw/hyperv/hyperv.h
+++ b/include/hw/hyperv/hyperv.h
@@
John Snow writes:
> On Wed, Mar 5, 2025 at 5:10 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > Instead of using the info object for the doc block as a whole (which
>> > always points to the very first line of the block), update the info
>> > pointer for each call to ensure_untagged_
On 05/03/2025 19:45, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
On 3/5/25 10:29, Cédric Le Goater wrote:
Hello,
On 3/4/25 23:03, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This is an updated v6 patch series of the v5 series located here:
On 05/03/2025 16.39, Philippe Mathieu-Daudé wrote:
Introduce legacy_binary_endianness() to return the endianness
of a legacy binary, and legacy_binary_is_big_endian() being
equivalent of compile time TARGET_BIG_ENDIAN definition.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/legacy_b
Hi Christian !
On Tue, 4 Mar 2025 16:15:57 +0100
Christian Schoenebeck wrote:
> Even though this function is serialized to be always called from main
> thread, v9fs_reclaim_fd() is dispatching the coroutine to a worker thread
> in between via its v9fs_co_*() calls, hence leading to the situation
John Snow writes:
> On Wed, Mar 5, 2025 at 5:16 AM Markus Armbruster wrote:
>
>> Replaying review of a previous posting for your convenience...
>>
>> John Snow writes:
>>
>> > This patch adds an explicit section "kind" to all QAPIDoc
>> > sections. Members/Features are now explicitly marked as
On 9/2/25 08:34, Paolo Bonzini wrote:
On 2/6/25 19:18, Philippe Mathieu-Daudé wrote:
"cpu.h" is target-specific. Definitions which can be used
by hw/ code when building QOM blocks can be in "cpu-qom.h",
which is target-agnostic.
Move the MISA bits (removing the pointless target_ulong cast)
and
On Thu, Mar 6, 2025 at 4:44 PM Michael Tokarev wrote:
>
> 06.03.2025 09:35, Michael Tokarev wrote:
>
> >> Migrate the tick_offset directly, adding it as a version-dependent field
> >> to VMState. Keep the old behavior when migrating from previous versions.
> >>
> >> Resolves: https://gitlab.com/qe
24.01.2025 13:14, Max Chou wrote:
According to the Vector Reduction Operations section in the RISC-V "V"
Vector Extension spec,
"If vl=0, no operation is performed and the destination register is not
updated."
The vd should be updated when vl is larger than 0.
Is this a qemu-stable material?
On Wed, Feb 19, 2025 at 2:59 AM Paolo Bonzini wrote:
>
> Almost all users of cpu->cfg.satp_mode care only about the "max" value
> satp_mode_max_from_map(cpu->cfg.satp_mode.map); convert the QOM
> properties back into it. For TCG, consult valid_vm[] instead of
> the bitmap of accepted modes.
>
> S
On 3/5/25 07:39, Philippe Mathieu-Daudé wrote:
There is no TARGET_ARM_64 definition. Luckily enough,
when TARGET_AARCH64 is defined, TARGET_ARM also is.
Fixes: 733766cd373 ("hw/arm: introduce xenpvh machine")
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/xen/arch_hvm.h | 2 +-
1 file
From: Yicong Yang
Currently we build the PPTT starting from the socket node and each
socket will be a separate tree. For a multi-socket system it'll
be hard for the OS to know the whole system is homogeneous or not
(actually we're in the current implementation) since no parent node
to telling the
From: Yicong Yang
Allow changes to PPTT test table, preparing for adding identical
implementation flags support and for adding a root node for all
the system.
Signed-off-by: Yicong Yang
Reviewed-by: Jonathan Cameron
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.
From: Yicong Yang
The lastest ACPI spec 6.5 support PPTT revision 3. Update it
by handy. This is compatible with previous revision.
Signed-off-by: Yicong Yang
Reviewed-by: Jonathan Cameron
Signed-off-by: Alireza Sanaee
---
hw/acpi/aml-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
From: Yicong Yang
Update the ACPI tables according to the acpi aml_build change, also
empty bios-tables-test-allowed-diff.h.
The disassembled differences between actual and expected PPTT shows
below. Only about the root node adding and identification flag set
as expected.
/*
* Intel ACPI C
On Wed, Feb 19, 2025 at 2:59 AM Paolo Bonzini wrote:
>
> "supported" can be computed on the fly based on the max_satp_mode.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_cfg.h | 4 +---
> target/riscv/cpu.c | 34
OS like Linux is using PPTT processor node's identical implementation
flag [1] to infer whether the whole system or a certain CPU cluster is
homogeneous or not [2]. QEMU currently only support building homogeneous
system, set the flag to indicate the fact. Build a root node in PPTT
for indicates th
On Wed, Feb 19, 2025 at 3:00 AM Paolo Bonzini wrote:
>
> They are used to provide the nice QOM properties for svNN,
> but the canonical source of the CPU configuration is now
> cpu->cfg.max_satp_mode. Store them in the ArchCPU struct.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Franc
From: Yicong Yang
Per ACPI 6.5 Table 5.158: Processor Structure Flags, the identical
implementation flag indicates whether all the children processors
of this node share the same identical implementation revision.
Currently Linux support parsing this field [1] and maybe used to
identify the heter
John Snow writes:
> On Wed, Mar 5, 2025 at 5:35 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > This is for the sake of the new rST generator (the "transmogrifier") so
>> > we can advance multiple lines on occasion while keeping the
>> > generated<-->source mappings accurate.
>> >
>>
On Wed, Mar 5, 2025 at 8:54 AM Michael S. Tsirkin wrote:
> On Tue, Mar 04, 2025 at 06:37:47PM +, Suravee Suthikulpanit wrote:
> > The QEMU-emulated AMD IOMMU PCI device is implemented based on the AMD
> I/O
> > Virtualization Technology (IOMMU) Specification [1]. The PCI id for this
> > devic
On 6/3/25 01:13, Edgar E. Iglesias wrote:
On Wed, Mar 5, 2025 at 5:22 PM Stefano Stabellini
mailto:sstabell...@kernel.org>> wrote:
+Edgar
On Wed, 5 Mar 2025, Philippe Mathieu-Daudé wrote:
> On 16/6/23 01:52, Stefano Stabellini wrote:
> > From: Vikram Garhwal mailto:vikram.g
On 26/02/2025 22.00, Matthew Rosato wrote:
This series introduces the concept of the relaxed translation requirement
for s390x guests in order to allow bypass of the guest IOMMU for more
efficient PCI passthrough.
With this series, QEMU can indicate to the guest that an IOMMU is not
strictly req
John Snow writes:
> On Wed, Mar 5, 2025, 6:31 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > Hi! This series is based on armbru/pull-qapi-2025-02-26.
>> >
>> > This series is a "minimum viable" version of the new QAPI documentation
>> > system. It does the bare minimum under the new
John Snow writes:
> On Wed, Mar 5, 2025, 4:13 AM Markus Armbruster wrote:
[...]
>> pylint warns:
>>
>> docs/sphinx/qapi_domain.py:279:4: W0237: Parameter 'contentnode' has
>> been renamed to 'content_node' in overriding 'QAPIObject.transform_content'
>> method (arguments-renamed)
>>
>> For
On Thu, Mar 6, 2025 at 6:26 AM Sahil Siddiq wrote:
>
> Hi,
>
> Sorry for the delay in my response. There was a lot to absorb in the
> previous mail and I thought I would spend some more time exploring
> this.
>
> On 2/11/25 1:27 PM, Eugenio Perez Martin wrote:
> > On Mon, Feb 10, 2025 at 5:25 PM S
On Mon, Mar 3, 2025 at 7:39 PM Florian Lugou
wrote:
>
> scontext size is 16 bits on RV32 and 32 bits on RV64, as recommended by
> version 1.0 2025-02-21 of the debug specification.
Section 5.7.8 indicates the register is XLEN bits wide, with data
being 32-bits wide for both RV32 and RV64.
Alista
Tomita,
On 3/3/25 18:52, Tomita Moeko wrote:
This patchset intends to decouple existing quirks from legacy mode.
Currently all quirks depends on legacy mode (except x-igd-opregion),
which includes following conditions:
* Machine type is i440fx
* IGD device is at guest BDF 00:02.0
* VBIOS in ROM
On Thu, Mar 06, 2025 at 04:22:52PM +1000, Alistair Francis wrote:
On Thu, Mar 6, 2025 at 4:13 PM Deepak Gupta wrote:
On Thu, Mar 06, 2025 at 03:29:00PM +1000, Alistair Francis wrote:
>On Tue, Feb 18, 2025 at 12:57 PM Deepak Gupta wrote:
>>
>> Commit f06bfe3dc38c ("target/riscv: implement zicf
On Thu, Mar 06, 2025 at 04:20:56PM +1000, Alistair Francis wrote:
On Thu, Mar 6, 2025 at 4:12 PM Deepak Gupta wrote:
On Thu, Mar 06, 2025 at 03:20:55PM +1000, Alistair Francis wrote:
>On Tue, Feb 18, 2025 at 12:56 PM Deepak Gupta wrote:
>>
>> Commit:8205bc1 ("target/riscv: introduce ssp and e
Hi Cedric,
> Subject: Re: [PATCH v4 17/23] hw/arm/aspeed_ast27x0.c Support AST2700 A1
> GIC Interrupt Mapping
>
> On 3/3/25 10:54, Jamin Lin wrote:
> > Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0.
> > These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197.
> >
On Fri, Feb 28, 2025 at 8:30 PM Paolo Bonzini wrote:
>
> From: Philippe Mathieu-Daudé
>
> Use GLib conversion macros to pass misa_mxl_max as
> riscv_cpu_class_init() class data.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> Link: https://lore.kernel.org/r/20250212
On Wed, Feb 19, 2025 at 3:01 AM Paolo Bonzini wrote:
>
> There is nothing that overwrites env->misa_mxl, so it is a constant. Do
The idea is that misa_mxl can change, although that's not supported now.
> not let a corrupted migration stream change the value; changing misa_mxl
Does this actuall
On 3/6/2025 3:00 AM, dongli.zh...@oracle.com wrote:
> Hi Dapeng,
>
> On 3/4/25 11:35 PM, Mi, Dapeng wrote:
>> On 3/3/2025 6:00 AM, Dongli Zhang wrote:
>>> The kvm_put_msrs() sets the MSRs using KVM_SET_MSRS. The x86 KVM processes
>>> these MSRs one by one in a loop, only saving the config and tri
On Wed, Mar 5, 2025 at 8:27 PM Santiago Monserrat Campanello
wrote:
>
> semihosting link to risc-v changed
>
> Signed-off-by: Santiago Monserrat Campanello
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> the original one l
On Fri, Feb 28, 2025 at 8:31 PM Paolo Bonzini wrote:
>
> To support merging a subclass's RISCVCPUDef into the superclass, a list
> of all the CPU features is needed. Put them into a header file that
> can be included multiple times, expanding the macros BOOL_FIELD and
> TYPE_FIELD to different op
Hi,
Sorry for the delay in my response. There was a lot to absorb in the
previous mail and I thought I would spend some more time exploring
this.
On 2/11/25 1:27 PM, Eugenio Perez Martin wrote:
On Mon, Feb 10, 2025 at 5:25 PM Sahil Siddiq wrote:
On 2/10/25 7:53 PM, Eugenio Perez Martin wrote:
On Thu, Mar 06, 2025 at 03:20:55PM +1000, Alistair Francis wrote:
On Tue, Feb 18, 2025 at 12:56 PM Deepak Gupta wrote:
Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for
zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access
to CSR_SSP in M-mode. Gated to CS
Do not consume a value if interpreting one failed so that we can
reinterpret the value with a different type.
Signed-off-by: Akihiko Odaki
---
qapi/qobject-input-visitor.c | 103 +--
1 file changed, 69 insertions(+), 34 deletions(-)
diff --git a/qapi/qobj
This series was spun off from:
"[PATCH 0/3] virtio-net: Convert feature properties to OnOffAuto"
(https://patchew.org/QEMU/20240714-auto-v3-0-e27401aab...@daynix.com/)
Some features are not always available with vhost. Legacy features are
not available with vp_vdpa in particular. virtio devices us
bool has representations of "on" and "off" different from
OnOffAuto/OnOffSplit:
- The command line syntax accepts on/yes/true/y and off/no/false/n for
bool but only on and off for OnOffAuto.
- JSON uses true/false for bool but "on" and "off" for
OnOffAuto/OnOffSplit.
This inconsistency causes
On Thu, Mar 06, 2025 at 03:29:00PM +1000, Alistair Francis wrote:
On Tue, Feb 18, 2025 at 12:57 PM Deepak Gupta wrote:
Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
`ssamoswap` instruction. `ssamoswap` takes the code-point from existing
reserved encoding (and not a
Some features are not always available with vhost. Legacy features are
not available with vp_vdpa in particular. virtio devices used to disable
them when not available even if the corresponding properties were
explicitly set to "on".
QEMU already has OnOffAuto type, which includes the "auto" value
The disassembled differences between actual and expected PPTT based on
the following cache topology representation:
- l1d and l1i shared at cluster level
- l2 shared at cluster level
- l3 shared at cluster level
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64
21.01.2025 20:06, Daniel Henrique Barboza wrote:
Hi,
In this new version, in patch 2, we're using the address 'size' val from
riscv_cpu_tlb_fill() instead of infering it from the CPU XLEN.
No other changes made. Patches based on master.
Changes from v2:
- patch 2:
- use 'size' instead of i
15.01.2025 00:21, Rodrigo Dias Correa wrote:
Instead of migrating the raw tick_offset, goldfish_rtc migrates a
recalculated value based on QEMU_CLOCK_VIRTUAL. As QEMU_CLOCK_VIRTUAL
stands still across a save-and-restore cycle, the guest RTC becomes out
of sync with the host RTC when the VM is res
On Wed, Feb 19, 2025 at 3:00 AM Paolo Bonzini wrote:
>
> The maximum available SATP mode implies all the shorter virtual address sizes.
> Store it in RISCVCPUConfig and avoid recomputing it via
> satp_mode_max_from_map.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
On Sat, Feb 22, 2025 at 2:21 AM Paolo Savini wrote:
>
> This commit expands the probe_pages helper function in
> target/riscv/vector_helper.c to handle also the cases in which we need access
> to
> the flags raised while probing the memory and the host address.
> This is done in order to provide
On Wed, Mar 5, 2025 at 5:10 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Instead of using the info object for the doc block as a whole (which
> > always points to the very first line of the block), update the info
> > pointer for each call to ensure_untagged_section when the existing
>
On Wed, Mar 5, 2025 at 9:24 PM Chao Liu wrote:
>
> Hi,
>
> This patchset fixes some bugs in RVV instructions,
>
> can you pull it in the near future please?
>
> Looking forward to your reply!
@Daniel Henrique Barboza you commented on v2, can you have a look at this?
Alistair
>
> --
> Regards,
>
On 3/5/25 08:12, Philippe Mathieu-Daudé wrote:
Introduce theTypeInfo::registerable() callback to allow
runtime decision on whether register a QOM type or not.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qom/object.h | 1 +
qom/object.c | 4
qom/trace-events | 1 +
3 f
On Wed, Mar 05, 2025 at 08:43:53AM +0100, Thomas Huth wrote:
> We run the gitlab-CI with the untrusted tests enabled, and
> the test_replay_mips64el_malta_5KEc_cpio subtest is rather slow,
> so this already hit the standard 90 seconds timeout in the CI.
> Increase the timeout for more headroom.
>
Hi Cedric,
> Subject: Re: [PATCH v4 14/23] hw/intc/aspeed: Add Support for Multi-Output
> IRQ Handling
>
> On 3/3/25 10:54, Jamin Lin wrote:
> > This update introduces support for handling multi-output IRQs in the
> > AST2700 interrupt controller (INTC), specifically for GICINT192_201.
> > GICIN
On Wed, Mar 5, 2025 at 9:20 AM Philippe Mathieu-Daudé wrote:
>
> Prefer runtime helpers to get target page size / mask / bits
> rather than compile time definitions. This will help to build
> these files once for all RISC-V binaries.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistai
On Wed, Mar 5, 2025 at 9:20 AM Philippe Mathieu-Daudé wrote:
>
> Prefer runtime helpers to get target page size / mask / bits
> rather than compile time definitions. This will help to build
> these files once for all RISC-V binaries.
>
> Signed-off-by: Philippe Mathieu-Daudé
Thanks!
Do you mind
On Wed, Mar 5, 2025 at 5:16 AM Markus Armbruster wrote:
> Replaying review of a previous posting for your convenience...
>
> John Snow writes:
>
> > This patch adds an explicit section "kind" to all QAPIDoc
> > sections. Members/Features are now explicitly marked as such, with the
> > name now b
Hi Harsh,
Thanks for your reviews.
On 04/03/25 14:31, Harsh Prateek Bora wrote:
On 2/17/25 12:47, Aditya Gupta wrote:
Implement the handler for "ibm,configure-kernel-dump" rtas call in QEMU.
Currently the handler just does basic checks and handles
register/unregister/invalidate requests fr
On Tue, Feb 25, 2025 at 10:55 AM Sebastian Huber
wrote:
>
> Real-time kernels such as RTEMS or Zephyr may use a static device tree
> built into the kernel image. Do not require to use the -dtb option if
> -kernel is used for the microchip-icicle-kit machine. Issue a warning
> if no device tree i
On 05/03/25 12:10, Harsh Prateek Bora wrote:
On 2/17/25 12:47, Aditya Gupta wrote:
<...snip...>
+ /* Reset error_flags & bytes_dumped for now */
+ fdm->rgn[i].error_flags = 0;
+ fdm->rgn[i].bytes_dumped = 0;
+
+ if (be32_to_cpu(fdm->rgn[i].request_flag) !=
FADUMP
On Fri, Feb 28, 2025 at 8:31 PM Paolo Bonzini wrote:
>
> From: Philippe Mathieu-Daudé
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
> Link: https://lore.kernel.org/r/20250212213249.45574-7-phi...@linaro.org
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Fran
On Tue, Mar 04, 2025 at 11:39:10AM +0300, ger...@altlinux.org wrote:
> From: Denis Rastyogin
>
> This error was discovered by fuzzing qemu-img.
>
> In the QED block driver, the need_check_timer timer is freed in
> bdrv_qed_detach_aio_context, but the pointer to the timer is not
> set to NULL. Th
The following changes since commit 661c2e1ab29cd9c4d268ae3f44712e8d421c0e56:
scripts/checkpatch: Fix a typo (2025-03-04 09:30:26 +0800)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git tags/block-pull-request
for you to fetch changes up to 2ad638a3d160923ef3dbf87
From: Denis Rastyogin
This error was discovered by fuzzing qemu-img.
In the QED block driver, the need_check_timer timer is freed in
bdrv_qed_detach_aio_context, but the pointer to the timer is not
set to NULL. This can lead to a use-after-free scenario
in bdrv_qed_drain_begin().
The need_check
On 05/03/25 12:53, Harsh Prateek Bora wrote:
On 2/17/25 12:47, Aditya Gupta wrote:
<...snip...>
+ case FADUMP_CPU_STATE_DATA: {
+ struct rtas_fadump_reg_save_area_header reg_save_hdr;
+ struct rtas_fadump_reg_entry **reg_entries;
+ struct rtas_fadump_r
On Tue, Feb 25, 2025 at 10:55 AM Sebastian Huber
wrote:
>
> Further customize the -bios and -kernel options behaviour for the
> microchip-icicle-kit machine. If "-bios none -kernel filename" is
> specified, then do not load a firmware and instead only load and start
> the kernel image.
>
> Signed
On 04/03/25 14:51, Harsh Prateek Bora wrote:
On 2/17/25 12:47, Aditya Gupta wrote:
According to PAPR:
R1–7.3.30–3. When the platform receives an ibm,os-term RTAS
call, or
on a system reset without an ibm,nmi-interlock RTAS call, if the
platform has a dump structure register
On Tue, Feb 25, 2025 at 10:55 AM Sebastian Huber
wrote:
>
> This property enables the setting of the CLINT timebase frequency
> through the command line, for example:
>
> -machine microchip-icicle-kit,clint-timebase-frequency=1000
>
> Signed-off-by: Sebastian Huber
> Reviewed-by: Philippe M
On Fri, Feb 28, 2025 at 8:31 PM Paolo Bonzini wrote:
>
> Prepare for adding more fields to RISCVCPUDef and reading them in
> riscv_cpu_init: instead of storing the misa_mxl_max field in
> RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct
> and go through it.
>
> Signed-off-by: P
On Fri, Feb 28, 2025 at 8:33 PM Paolo Bonzini wrote:
>
> Since all TYPE_RISCV_CPU subclasses support a class_data of type
> RISCVCPUDef, process it even before calling the .class_init function
> for the subclasses.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
On 3/5/25 08:38, Cornelia Huck wrote:
+++ b/target/arm/cpu-sysregs.h
@@ -0,0 +1,131 @@
+#ifndef ARM_CPU_SYSREGS_H
+#define ARM_CPU_SYSREGS_H
+
+/*
+ * Following is similar to the coprocessor regs encodings, but with an argument
+ * ordering that matches the ARM ARM. We also reuse the various CP_R
On 3/5/25 07:39, Philippe Mathieu-Daudé wrote:
+void legacy_binary_info_init(const char *argv0)
+{
+g_auto(GStrv) tokens = g_strsplit(argv0, G_DIR_SEPARATOR_S, -1);
+unsigned count = 0;
+const char *binary_name;
+
+while (tokens[count]) {
+count++;
+}
+assert(count
On Wed, Feb 19, 2025 at 2:58 AM Paolo Bonzini wrote:
>
> Check that the argument to set_satp_mode_max_supported is valid for
> the MXL value of the CPU. It would be a bug in the CPU definition
> if it weren't.
>
> In fact, there is such a bug in riscv_bare_cpu_init(): not just
> SV32 is not a val
On Tue, Feb 25, 2025 at 10:55 AM Sebastian Huber
wrote:
>
> Booting the microchip-icicle-kit machine using the latest PolarFire SoC
> Hart Software Services (HSS) no longer works since Qemu lacks support
> for several registers (clocks, DRAM controller). Also reading from the
> SDCard does not wor
On Wed, Feb 19, 2025 at 3:00 AM Paolo Bonzini wrote:
>
> The maximum available SATP mode implies all the shorter virtual address sizes.
> Store it in RISCVCPUConfig and avoid recomputing it via
> satp_mode_max_from_map.
>
> Signed-off-by: Paolo Bonzini
This fails to build on the latest riscv-to
On Tue, Feb 25, 2025 at 11:49 AM ~yuming wrote:
>
> From: Yu-Ming Chang
>
> Since C always implies Zca, Zca is always enabled when 16-bit
> insructions are supported. we can only check ext_zca to allow
> 16-bit aligned PC addresses.
>
> Signed-off-by: Yu-Ming Chang
Thanks!
Applied to riscv-to-
On Wed, Feb 19, 2025 at 2:58 AM Paolo Bonzini wrote:
>
> Do not create the RHCT MMU type entry for RV32 CPUs, since it
> only has definitions for SV39/SV48/SV57. Likewise, check that
I don't have access to the spec, so I'm going to take your word on this
> satp_mode_max_from_map() will actually
On 3/5/25 07:39, Philippe Mathieu-Daudé wrote:
Prefer runtime helpers to get target page size.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/vfio/common.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index 7a4010ef4ee..d4c9e5
On 3/5/25 07:39, Philippe Mathieu-Daudé wrote:
Ensure common code never use this target specific definition.
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/poison.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/poison.h b/include/exec/poison.h
index 0c4ad04eb97..0a
On 3/5/25 08:38, Cornelia Huck wrote:
Signed-off-by: Cornelia Huck
---
target/arm/cpu-sysregs.h | 3 +++
target/arm/cpu64.c | 25 +
target/arm/kvm.c | 12
3 files changed, 40 insertions(+)
diff --git a/target/arm/cpu-sysregs.h b/target/ar
On Wed, Mar 5, 2025 at 5:35 AM Markus Armbruster wrote:
> John Snow writes:
>
> > This is for the sake of the new rST generator (the "transmogrifier") so
> > we can advance multiple lines on occasion while keeping the
> > generated<-->source mappings accurate.
> >
> > next_line now simply takes
On Tue, Feb 25, 2025 at 11:49 AM ~yuming wrote:
>
> From: Yu-Ming Chang
>
> Since C always implies Zca, Zca is always enabled when 16-bit
> insructions are supported. we can only check ext_zca to allow
> 16-bit aligned PC addresses.
Urgh! Sorry about this
Zca is only in priv spec version 1.12 o
On Tue, Feb 18, 2025 at 12:56 PM Deepak Gupta wrote:
>
> Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for
> zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access
> to CSR_SSP in M-mode. Gated to CSR_SSP is not gated via `xSSE`. But
> rather rules clearly spec
On 3/4/25 23:03, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
DEFINE_PROP_ON_OFF_AUTO() property isn't runtime-mutable so using it
would mean that the source VM would need to decide upfront at startup
time whether it wants to do a multifd device state transfer at some
point.
Source V
Fabiano,
Could you please ack (or not) this patch please ?
Thanks,
C.
On 3/4/25 23:03, Maciej S. Szmigiero wrote:
From: Peter Xu
The newly introduced device state buffer can be used for either storing
VFIO's read() raw data, but already also possible to store generic device
states. After
On 05/03/2025 11:29, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
Hello,
On 3/4/25 23:03, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This is an updated v6 patch series of the v5 series located here:
https://lore.kernel.org/qemu-devel/cover.1
From: Arpit Kumar
CXL spec 3.2 section 8.2.10.5.3 describes Get Log Capabilities.
It provides log capabilities supported by specified log.
Signed-off-by: Arpit Kumar
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 20
include/hw/cxl/cxl_mailbox.h | 5
From: Davidlohr Bueso
As of 3.1 spec, background commands can be canceled with a new
abort command. Implement the support, which is advertised in
the CEL. No ad-hoc context undoing is necessary as all the
command logic of the running bg command is done upon completion.
Arbitrarily, the on-going b
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