Re: [RFC PATCH] gitlab: add a new build_unit job to track build size

Hi Alex, On 2/28/25 09:54, Alex Bennée wrote: We want to reduce the total number of build units in the system to get on our way to a single binary. It will help to have some numbers so lets add a job to gitlab to track our progress. That's a good idea! Signed-off-by: Alex Bennée Cc: Pierri

Re: [PATCH] bcm2838: Add GIC-400 timer interupt connections

On Sat, 1 Mar 2025 at 01:47, Sourojeet Adhikari wrote: > > On 2025-02-27 10:17, Peter Maydell wrote: > > On Thu, 27 Feb 2025 at 09:15, Sourojeet Adhikari > wrote: > > The systmr INTERRUPT_TIMER0..3 sysbus IRQ outputs are already > being wired up in the function bcm_soc_peripherals_common_realize(

Re: [PATCH] hw/net/fsl_etsec: Set eTSEC device description and category

On Tue, 18 Feb 2025, BALATON Zoltan wrote: Add description and set category for eTSEC device so it shows up better in -device help. Ping? Signed-off-by: BALATON Zoltan --- hw/net/fsl_etsec/etsec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etse

[PATCH] target/arm: Make dummy debug registers RAZ, not NOP

In debug_helper.c we provide a few dummy versions of debug registers: * DBGVCR (AArch32 only): enable bits for vector-catch debug events * MDCCINT_EL1: interrupt enable bits for the DCC debug communications channel * DBGVCR32_EL2: the AArch64 accessor for the state in DBGVCR We impleme

Re: [PATCH] hw/ppc/e500: Partial implementation of local access window registers

On Wed, 15 Jan 2025, BALATON Zoltan wrote: This allows guests to set the CCSR base address. Also store and return values of the local access window registers but their functionality isn't implemented. Bernhard, If you have no alternative patch you plan to submit for next release should we mer

[PATCH 31/39] target/hexagon: Add implicit sysreg writes

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.c | 16 1 file changed, 16 insertions(+) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index d4b22acb72..ff881d1060 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/trans

Re: Kubernetes gitlab-runner jobs cannot be scheduled

On 3/1/25 07:19, Stefan Hajnoczi wrote: Hi, On February 26th GitLab CI started failing many jobs because they could not be scheduled. I've been unable to merge pull requests because the CI is not working. Here is an example failed job: https://gitlab.com/qemu-project/qemu/-/jobs/9281757413 Hi

Re: [PATCH v2 01/10] bsd-user: drop not longer used target_reset_cpu()

On Fri, Feb 7, 2025 at 9:21 AM Igor Mammedov wrote: > target_reset_cpu() static inlines have no user, > remove them. > > Signed-off-by: Igor Mammedov > --- > CC: Warner Losh > CC: Kyle Evans > --- > bsd-user/aarch64/target_arch_cpu.h | 5 - > bsd-user/arm/target_arch_cpu.h | 4 >

[PATCH 24/39] target/hexagon: Add exec-start-addr prop

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 + target/hexagon/cpu.c | 7 ++- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index baa48ec051..4667a1f748 100644 --- a/target/hexagon/cpu.h +++ b/target/hex

[PATCH 22/39] target/hexagon: Implement setprio, resched

From: Brian Cain The hardware-assisted scheduler helps manage tasks on the run queue and interrupt steering. This instruction is defined in the Qualcomm Hexagon V71 Programmer's Reference Manual - https://docs.qualcomm.com/bundle/publicresource/80-N2040-51_REV_AB_Hexagon_V71_ProgrammerS_Referenc

Re: [PATCH v5 1/2] target/loongarch: fix 'make check-functional' failed

On 2025/2/28 下午5:06, Song Gao wrote: some tlb instructions get the tlb_ps from tlb->misc but the value may has been initialized to 0,just check the tlb_ps skip the function and write a log. Signed-off-by: Song Gao --- target/loongarch/tcg/tlb_helper.c | 8 1 file changed, 8 i

[PATCH 11/39] target/hexagon: Add representation to count cycles

From: Brian Cain The PCYCLE register can be enabled to indicate accumulated clock cycles. Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 3 ++- target/hexagon/cpu.c | 3 +++ target/hexagon/machine.c | 25 - 3 files changed, 29 insertions(+), 2 deletions(

Re: [PATCH] util/keyval: fix msan findings

Paolo Bonzini writes: > On 2/28/25 22:20, Patrick Venture wrote: >> From: Peter Foley >> e.g. >> qemu: Uninitialized value was created by an allocation of 'key_in_cur.i' in >> the stack frame >> qemu: #0 0xc49f489c in keyval_parse_one >> third_party/qemu/util/keyval.c:190:5 >> Signed-off-b

[PATCH v6 6/6] target/i386: Add support for EPYC-Turin model

Add the support for AMD EPYC zen 5 processors (EPYC-Turin). Add the following new feature bits on top of the feature bits from the previous generation EPYC models. movdiri : Move Doubleword as Direct Store Instruction movdir64b : Move 64 Bytes as Direct Store Instruction avx

[PATCH 36/38] target/hexagon: Add clear_wait_mode() definition

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 1 + target/hexagon/cpu_helper.c | 10 ++ 2 files changed, 11 insertions(+) diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index e0c0c037a6..6f0c6697ad 100644 --- a/target/hexagon/cpu_

[PATCH 16/39] target/hexagon: Implement hex_tlb_lookup_by_asid()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/hex_mmu.c | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c index d2297c036d..07ad8e9616 100644 --- a/target/hexagon/hex_mmu.c +++ b/tar

[PATCH 11/38] target/hexagon: Add guest/sys reg writes to DisasContext

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 36 1 file changed, 36 insertions(+) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index f611c854dc..0eaa3db03e 100644 --- a/target/hexagon/translate.h +++ b/

[PATCH 15/38] target/hexagon: Add handlers for guest/sysreg r/w

From: Brian Cain This commit provides handlers to generate TCG for guest and system register reads and writes. They will be leveraged by a future commit. Signed-off-by: Brian Cain --- target/hexagon/genptr.c | 159 1 file changed, 159 insertions(+) di

[PATCH 21/38] target/hexagon: Add system reg insns

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/macros.h | 2 + target/hexagon/hex_common.py | 15 +- target/hexagon/imported/encode_pp.def | 213 +++-- target/hexagon/imported/system.idef | 262 +++--- 4 files change

[PATCH 09/38] target/hexagon: Add guest, system reg number state

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 8 target/hexagon/cpu.c | 17 + 2 files changed, 25 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 20ea0adcca..b7789a3c90 100644 --- a/target/hexagon/cpu.h +++ b/target

[PATCH 28/39] target/hexagon: Implement modify_ssr, resched, pending_interrupt

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/helper.h| 3 +++ target/hexagon/op_helper.c | 20 2 files changed, 23 insertions(+) diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 730eaf8b9a..3df663baeb 100644 --- a/target/hexagon/he

[PATCH 00/38] hexagon system emu, part 1/3

hexagon architecture system emulation: part 1/3 These patches are also staged in my tree (branch "hex-next" at https://github.com/quic/qemu/). After these three patch series, we're able to run the test suite for minivm [1]. minivm is a hypervisor, an implementation of the Hexagon Virtual Machine

[PATCH 33/39] target/hexagon: initialize sys/guest reg TCGvs

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.c | 20 1 file changed, 20 insertions(+) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index ff881d1060..248ed60f29 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/t

[PATCH 21/39] target/hexagon: Implement hexagon_resume_threads()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h| 1 + target/hexagon/cpu_helper.h | 1 + target/hexagon/cpu_helper.c | 37 + target/hexagon/op_helper.c | 3 ++- 4 files changed, 41 insertions(+), 1 deletion(-) diff --git a/tar

[PATCH 27/38] target/hexagon: Add sreg_{read,write} helpers

From: Brian Cain Co-authored-by: Sid Manning Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 8 +++ target/hexagon/cpu.c| 1 + target/hexagon/cpu_helper.c | 37 target/hexagon/op_helper.c | 114 ++-- 4 files changed, 156 in

[PATCH 03/38] target/hexagon: Add System/Guest register definitions

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/gen_analyze_funcs.py | 21 +++- target/hexagon/hex_common.py| 163 2 files changed, 181 insertions(+), 3 deletions(-) diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analy

[PATCH 18/38] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index db50defeb6..7fb11a0819 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexa

[PATCH v6 0/6] target/i386: Update EPYC CPU models for Cache property, RAS, SVM feature and add EPYC-Turin CPU model

Following changes are implemented in this series. 1. Fixed the cache(L2,L3) property details in all the EPYC models. 2. Add RAS feature bits (SUCCOR, McaOverflowRecov) on all EPYC models 3. Add missing SVM feature bits required for nested guests on all EPYC models 4. Add the missing feature bit

[PATCH 2/4] hw/nvram/eeprom_at24c: Remove ERR macro that calls fprintf to stderr

In the realize method error_setg can be used like other places there already do. The other usage can be replaced with error_report which is the preferred way instead of directly printing to stderr. Signed-off-by: BALATON Zoltan --- hw/nvram/eeprom_at24c.c | 12 +--- 1 file changed, 5 ins

[PATCH 4/4] hw/nvram/eeprom_at24c: Reorganise init to avoid overwriting values

The init_rom can write values to the beginning of the memory but these are overwritten by values from a backing file that covers the whole memory. Do the init_rom handling only if it would not be overwritten. Signed-off-by: BALATON Zoltan --- hw/nvram/eeprom_at24c.c | 6 ++ 1 file changed, 2

[PATCH 3/4] hw/nvram/eeprom_at24c: Remove memset after g_malloc0

Calling memset to zero memory is not needed after g_malloc0 which already clears memory. These used to be in separate functions but after some patches the memset ended up after g_malloc0 and thus can be dropped. Fixes: 4f2c6448c3 (hw/nvram/eeprom_at24c: Make reset behavior more like hardware) Sig

[PATCH 1/4] hw/nvram/eeprom_at24c: Use OBJECT_DECLARE_SIMPLE_TYPE

No need to open code it so use the simple object type declaration. Signed-off-by: BALATON Zoltan --- hw/nvram/eeprom_at24c.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c index a40cc5dd15..2ae03935d4 100644 --- a/hw/nvram

[PATCH 0/4] Misc eeprom_at24c clean ups

These are some small misc clean ups in hw/nvram/eeprom_at24c. Regards, BALATON Zoltan BALATON Zoltan (4): hw/nvram/eeprom_at24c: Use OBJECT_DECLARE_SIMPLE_TYPE hw/nvram/eeprom_at24c: Remove ERR macro that calls fprintf to stderr hw/nvram/eeprom_at24c: Remove memset after g_malloc0 hw/nvra

[PATCH 2/8] hw/hexagon: Add machine configs for sysemu

From: Brian Cain Co-authored-by: Mike Lambert Co-authored-by: Sid Manning Signed-off-by: Brian Cain --- MAINTAINERS| 2 + qapi/machine.json | 2 +- include/hw/hexagon/hexagon.h | 151 + hw/hexagon/machine_cfg_v

[PATCH 1/8] hw/intc: Add l2vic interrupt controller

From: Sid Manning Co-authored-by: Matheus Tavares Bernardino Co-authored-by: Damien Hedde Signed-off-by: Brian Cain --- MAINTAINERS| 2 + docs/devel/hexagon-l2vic.rst | 59 + docs/devel/index-internals.rst | 1 + include/hw/intc/l2vic.h| 37 +++ hw/intc

[PATCH 5/8] hw/hexagon: Modify "Standalone" symbols

From: Brian Cain These symbols are used by Hexagon Standalone OS to indicate whether the program should halt and wait for interrupts at startup. For QEMU, we want these programs to just continue crt0 startup through to the user program's main(). Signed-off-by: Brian Cain --- hw/hexagon/hexago

[PATCH 7/8] hw/hexagon: Define hexagon "virt" machine

From: Brian Cain Signed-off-by: Brian Cain --- configs/devices/hexagon-softmmu/default.mak | 1 + configs/targets/hexagon-softmmu.mak | 1 + include/hw/hexagon/virt.h | 41 ++ hw/hexagon/virt.c | 395 target/hexagon/c

[PATCH 3/8] hw/hexagon: Add v68, sa8775-cdsp0 defs

From: Brian Cain Signed-off-by: Brian Cain --- hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc | 64 ++ hw/hexagon/machine_cfg_v68n_1024.h.inc| 65 +++ 2 files changed, 129 insertions(+) create mode 100644 hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc create

[PATCH 0/8] hexagon system emu, part 3/3

hexagon architecture system emulation: part 3/3 This series contains some initial machine definitions, an interrupt controller device and a test case. Hexagon "Standalone OS" is used by the Hexagon SDK to create simple baremetal bootable programs that can be run on QEMU or the instruction set sim

[PATCH 8/8] tests/functional: Add a hexagon minivm test

From: Brian Cain Signed-off-by: Brian Cain --- MAINTAINERS | 1 + tests/functional/meson.build| 8 + tests/functional/test_hexagon_minivm.py | 42 + 3 files changed, 51 insertions(+) create mode 100755 tests/functional/test_

[PATCH 6/8] target/hexagon: add build config for softmmu

Signed-off-by: Brian Cain --- MAINTAINERS | 1 + configs/devices/hexagon-softmmu/default.mak | 7 +++ configs/targets/hexagon-softmmu.mak | 6 ++ target/Kconfig | 1 + target/hexagon/Kconfig | 2 ++

[PATCH v2] hw/riscv/riscv-iommu: Fix process directory table walk

The PPN field in a non-leaf PDT entry is positioned differently from that in a leaf PDT entry. The original implementation incorrectly used the leaf entry's PPN mask to extract the PPN from a non-leaf entry, leading to an erroneous page table walk. This commit introduces new macros to properly def

Re: [PATCH] hw/riscv/riscv-iommu: Fix process directory table walk

Hi Danial, I have rebased onto commit d1d54e60bcbfb9ef7804ec5376b84bb0a1e7148f and submitted patch v2. Daniel Henrique Barboza 於 2025年2月28日 週五 下午7:18寫道： > Hi Jason, > > > Patch LGTM but it won't apply on top of alistair/riscv-to-apply.next. Can > you please rebase? > > > Thanks, > > Daniel > >

[PATCH 10/39] target/hexagon: Implement arch_{s, g}et_{thread, system}_reg()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index e8d89d8526..1cdf4f8dd0 100644 --- a/target/hexagon/cpu_helper.h +++ b/tar

[PATCH 22/38] target/hexagon: Add sysemu TCG overrides

From: Brian Cain Define TCG overrides for setprio(), crswap(,sgp{0,1,1:0}). Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 32 target/hexagon/gen_tcg_sys.h | 41 target/hexagon/helper.h | 1 + target/hexagon/

Re: [PATCH v2] microvm: do not use the lastest cpu version

On Thu, Feb 20, 2025 at 12:36 PM Zhao Liu wrote: > > On Thu, Feb 20, 2025 at 12:23:26PM +0530, Ani Sinha wrote: > > Date: Thu, 20 Feb 2025 12:23:26 +0530 > > From: Ani Sinha > > Subject: [PATCH v2] microvm: do not use the lastest cpu version > > X-Mailer: git-send-email 2.45.2 > > > > commit 0788

[PATCH 4/8] hw/hexagon: Add support for cfgbase

From: Sid Manning Signed-off-by: Sid Manning --- target/hexagon/cpu.h | 1 + hw/hexagon/hexagon_dsp.c | 10 ++ target/hexagon/cpu.c | 6 ++ 3 files changed, 17 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 73c3bb34b0..0608d3265c 100644 --- a

[PATCH 19/38] target/hexagon: Define register fields for system regs

From: Brian Cain Define the register fields for ssr, schedcfg, stid, bestwait, ccr, modectl, imask, ipendad. Define the fields for TLB entries. Signed-off-by: Brian Cain --- target/hexagon/reg_fields_def.h.inc | 96 + 1 file changed, 96 insertions(+) diff --git a/

Re: [PATCH v2 4/7] tests/functional: reduce tuxrun maxmem to work on 32-bit hosts

On 2/28/25 02:27, Daniel P. Berrangé wrote: maxmem=4G is too large to address on 32-bit hosts, so reduce it to 2G since the tuxrun tests don't actually need such an elevated memory limit. Signed-off-by: Daniel P. Berrangé --- tests/functional/test_ppc64_tuxrun.py | 2 +- 1 file changed, 1 ins