From: Akihiko Odaki
pci_new() aborts when creating a VF with addr >= PCI_DEVFN_MAX.
Signed-off-by: Akihiko Odaki
Message-Id: <20250116-reuse-v20-7-7cb370606...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
docs/pcie_sriov.txt | 8 +---
include
From: Thomas Huth
QEMU currently crashes when you try to inspect the properties of the
microvm machine:
$ echo '{ "execute": "qmp_capabilities" }
{ "execute": "qom-list-properties","arguments":
{ "typename": "microvm-machine"}}' | \
./qemu-system-x86_64 -qmp stdio
{"QMP"
From: Akihiko Odaki
A PF may automatically create VFs and the PF may be function 0.
Signed-off-by: Akihiko Odaki
Reviewed-by: Shivaprasad G Bhat
Tested-by: Shivaprasad G Bhat
Message-Id: <20250116-reuse-v20-2-7cb370606...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S.
From: Akihiko Odaki
Disable SR-IOV VF devices by reusing code to power down PCI devices
instead of removing them when the guest requests to disable VFs. This
allows to realize devices and report VF realization errors at PF
realization time.
Signed-off-by: Akihiko Odaki
Message-Id: <20250116-reu
From: Akihiko Odaki
num_vfs is not migrated so use PCI_SRIOV_CTRL_VFE and PCI_SRIOV_NUM_VF
instead.
Signed-off-by: Akihiko Odaki
Message-Id: <20250116-reuse-v20-10-7cb370606...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
include/hw/pci/pcie_sriov.h | 1
From: Akihiko Odaki
A device gets automatically unrealized when being unparented.
Signed-off-by: Akihiko Odaki
Message-Id: <20250116-reuse-v20-6-7cb370606...@daynix.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci/pcie_sri
From: Li Zhijian
Introduce the `CXL_T3_MSIX_VECTOR` enumeration to specify MSIX vector
assignments specific to the Type 3 (T3) CXL device.
The primary goal of this change is to encapsulate the MSIX vector uses
that are unique to the T3 device within an enumeration, improving code
readability and
From: Yao Xingtao
Since the kernel does not check the interleave capability, a
3-way, 6-way, 12-way or 16-way region can be create normally.
Applications can access the memory of 16-way region normally because
qemu can convert hpa to dpa correctly for the power of 2 interleave
ways, after kernel
From: Matias Ezequiel Vara Larsen
Use virtio_get_config_size() rather than sizeof(struct
virtio_snd_config) for the config_size in the vhost-user-snd frontend.
The frontend shall rely on device features for the size of the device
configuration space. The presence of `controls` in the config space
From: Stefano Garzarella
While sending a patch for backends/cryptodev-vhost.c I noticed that
Michael wasn`t in CC so I took a look at the files listed under `vhost`
and tried to fix it increasing the coverage by adding new files.
Signed-off-by: Stefano Garzarella
Message-Id: <20250211144259.117
Em Fri, 21 Feb 2025 10:21:27 +
Jonathan Cameron escreveu:
> On Fri, 21 Feb 2025 07:38:23 +0100
> Mauro Carvalho Chehab wrote:
>
> > Em Mon, 3 Feb 2025 16:22:36 +0100
> > Igor Mammedov escreveu:
> >
> > > On Mon, 3 Feb 2025 11:09:34 +
> > > Jonathan Cameron wrote:
> > >
> > > >
From: Akihiko Odaki
VFs are automatically created by PF, and creating zpci for them will
result in unexpected usage of fids. Currently QEMU does not support
multifunction for s390x so we don't need zpci for VFs anyway.
Signed-off-by: Akihiko Odaki
Message-Id: <20250116-reuse-v20-3-7cb370606...@
From: Alexander Graf
When we return a response packet from NSM, we need to indicate its
length according to the content of the response. Prior to this patch, we
returned the length of the source buffer, which may confuse guest code
that relies on the response size.
Fix it by returning the respon
We're missing scounteren and senvcfg CSRs, both already present in the
KVM UAPI.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/kvm/kvm-cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index f14fcc58bb..017ca82226 10
From: Daniel P. Berrangé
When a machine is first booted, all virtio balloon stats are initialized
to their default value -1 (18446744073709551615 when represented as
unsigned).
They remain that way while the firmware is loading, and early phase of
guest OS boot, until the virtio-balloon driver i
From: Nicholas Piggin
Of the MSI-X PBA pending bits, the PCI Local Bus Specification says:
Software should never write, and should only read
Pending Bits. If software writes to Pending Bits, the
result is undefined.
Log a GUEST_ERROR message if the PBA is written to by software.
Cc: Marc
From: Jonah Palmer
Creates and supports an IOVA-only tree to support a SVQ IOVA->HVA and
GPA->IOVA tree for host-only and guest-backed memory, respectively, in
the next patch.
The IOVA allocator still allocates an IOVA range but now adds this range
to the IOVA-only tree as well as to the full IO
From: Sairaj Kodilkar
Interrupt passthrough is determine by the bits 191,190,187-184.
These bits are part of the 3rd quad word (i.e. index 2) in DTE. Hence
replace dte[3] by dte[2].
Fixes: b44159fe0 ("x86_iommu/amd: Add interrupt remap support when VAPIC is not
enabled")
Signed-off-by: Sairaj K
From: Li Zhijian
Simply pass the errp to its callee which will set errp if needed, to
enhance error reporting for CXL Type 3 device initialization by setting
the errp when realization functions fail.
Previously, failing to set `errp` could result in errors being overlooked,
causing the system to
From: Eric Auger
To ease the debug of reset sequence, let's add a trace point
in vfio_reset_handler()
Signed-off-by: Eric Auger
Reviewed-by: Cédric Le Goater
Acked-by: Michael S. Tsirkin
Reviewed-by: Zhenzhong Duan
Message-Id: <20250218182737.76722-5-eric.au...@redhat.com>
Reviewed-by: Peter
Hi,
In this version the following changes were made, based on feedback from
Drew in v1:
- patch 2: reworked. Instead of using a different existing 'env' field
to get/put the 'sie' CSR, we're adding a new helper that contains all
reset vals for the KVM CSRs we support
- patch 3: reworked. Add
From: Laurent Vivier
The netdev reports NETDEV_VHOST_USER_CONNECTED event when
the chardev is connected, and NETDEV_VHOST_USER_DISCONNECTED
when it is disconnected.
The NETDEV_VHOST_USER_CONNECTED event includes the chardev id.
This allows a system manager like libvirt to detect when the server
On 2/20/25 16:19, Philippe Mathieu-Daudé wrote:
Hmm what about keeping a MAC_PVG_COMMON instead:
-- >8 --
--- a/hw/display/Kconfig
+++ b/hw/display/Kconfig
@@ -141,15 +141,17 @@ config XLNX_DISPLAYPORT
config DM163
bool
-config MAC_PVG
+config MAC_PVG_COMMON
bool
- default y
+
Am 21. Februar 2025 07:34:44 UTC schrieb Ilya Chichkov :
>Add PCF8563 a real-time clock with calendar and I2C interface.
Nice! I'd like to use it myself.
>This commit adds support for interfacing with it and implements
>functionality of setting timer, alarm, reading and writing time.
>
>Datash
On Fri, 21 Feb 2025 at 14:41, Philippe Mathieu-Daudé wrote:
>
> On 17/2/25 13:50, Peter Maydell wrote:
>
> > (1) floatx80 behaviours
> >
> > Two QEMU targets implement floatx80: x86 and m68k. (PPC also has one
> > use in the xsrqpxp round-to-80-bit-precision operation, and the
> > Linux-user NWFPE
From: Khem Raj
glibc 2.41+ has added [1] definitions for sched_setattr and
sched_getattr functions and struct sched_attr. Therefore, it needs
to be checked for here as well before defining sched_attr, to avoid
a compilation failure.
Define sched_attr conditionally only when SCHED_ATTR_SIZE_VER0
As shown in the PL011 device, the orphan rules required a manual
implementation of ClassInitImpl for anything not in the qemu_api crate;
this gets in the way of moving system emulation-specific code (including
DeviceClass, which as a blanket ClassInitImpl implementation)
into its own crate.
Make C
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/bindings.rs | 6
rust/qemu-api/src/qdev.rs | 68 ---
rust/qemu-api/src/vmstate.rs | 2 +-
3 files changed, 49 insertions(+), 27 deletions(-)
diff --git a/rust/qemu-api/src/bindings.rs b/rust/qemu-api/s
On 2/20/25 10:54, Peter Maydell wrote:
On Thu, 20 Feb 2025 at 18:39, Richard Henderson
wrote:
On 2/20/25 09:12, Peter Maydell wrote:
That suggests that we are correctly implementing the x87
required behaviour in QEMU, and so that the TODO comment
I add in this patch isn't right. But then I'm
From: Mikael Szreder
The gdbstub implementation for the Sparc architecture would
incorrectly calculate the the floating point register offset.
This resulted in, for example, registers f32 and f34 to point to
the same value.
The issue was caused by the confusion between even register numbers
and
On 2/20/25 06:11, Jamin Lin wrote:
Hi Cedric,
Subject: Re: [PATCH v3 00/28] Support AST2700 A1
Hello Jamin,
On 2/13/25 04:35, Jamin Lin wrote:
v1:
1. Refactor INTC model to support both INTC0 and INTC1.
2. Support AST2700 A1.
3. Create ast2700a0-evb machine.
v2:
To streamline
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Hello Zhenzhong,
On 2/21/25 07:12, Duan, Zhenzhong wrote:
-Original Message-
From: Alex Williamson
Subject: [PATCH 4/5] pcie, virtio: Remove redundant pm_cap
The pm_cap on the PCIExpressDevice object can be distilled down
to the new instance on the PCIDevice object.
Cc: Michael S.
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