On Fri, Jan 24, 2025 at 05:03:27PM +0100, Stefano Brivio wrote:
> But I don't understand why we're leaving this as it is.
So that people notice if there's some backend problem and
announcements are not going out. should help debug migration
issues. which we had, so we added this :)
Hi Zhenzhong,
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> Signed-off-by: Nicolin Chen
> Signed-off-by: Zhenzhong Duan
in the title, there is only a single helper here. a small commit msg may
help the reader
> ---
> include/system/iommufd.h | 3 +++
> backends/iommufd.c | 30
In system register access pseudocode the common pattern for
AArch32 registers with access traps to EL3 is:
at EL1 and EL2:
if HaveEL(EL3) && !ELUsingAArch32(EL3) && (SCR_EL3.TERR == 1) then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && (SCR.TERR =
Thank you very much!
On Thu, Feb 20, 2025 at 8:18 AM Peter Maydell
wrote:
> On Wed, 19 Feb 2025 at 18:46, Hao Wu wrote:
> >
> > Changes since v4:
> >
> > 1. Bump vmstate versions on NPCM CLK and GCR modules.
> > 2. Remove "hw/boards.h" include in npcm8xx.h and add it in npcm8xx*.c
> > 3. Use cp
On Thu, 20 Feb 2025 10:28:20 -0500
"Michael S. Tsirkin" wrote:
> On Fri, Jan 24, 2025 at 05:03:27PM +0100, Stefano Brivio wrote:
> > But I don't understand why we're leaving this as it is.
>
> So that people notice if there's some backend problem and
> announcements are not going out. should h
On Thu, Feb 13, 2025 at 13:00:31 -0500, Stefan Hajnoczi wrote:
> Implement --device virtio-scsi-pci,iothread-vq-mapping= support so that
> virtqueues can be assigned to different IOThreads. This improves SMP guest
> scalability where I/O-intensive applications can become bottlenecked on a
> single
If GNU Binutils is configured with --enable-error-rwx-segments=yes, one
gets the following for optionrom:
```
.../bin/ld: error: pvh.img has a LOAD segment with RWX permissions
.../bin/ld: final link faile
```
Pass -Wl,--no-error-rwx-segments to suppress that.
Signed-off-by: Sam James
---
pc-bi
On Mon, 17 Feb 2025 at 19:14, Richard Henderson
wrote:
>
> On 2/17/25 04:50, Peter Maydell wrote:
> > Currently we compile-time set an 'm68k_denormal' flag in the FloatFmt
> > for floatx80 for m68k. This controls our handling of what the Intel
> > documentation calls a "pseudo-denormal": a value
On Thu, 20 Feb 2025 11:45:35 +0100
Eric Auger wrote:
> Hi Alex,
>
> On 2/20/25 11:31 AM, Eric Auger wrote:
> >
> > Hi Alex,
> >
> > On 2/19/25 10:19 PM, Alex Williamson wrote:
> >> On Wed, 19 Feb 2025 11:58:44 -0700
> >> Alex Williamson wrote:
> >>
> >>> On Wed, 19 Feb 2025 18:58:58 +0100
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> Currently we have realize() callback which is called before attachment.
> But there are still some elements e.g., hwpt_id is not ready before
> attachment. So we need a realize_late() callback to further initialize
> them.
from the description it is n
Hi Zhenzhong,
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> New added properties include IOMMUFD handle, devid and hwpt_id.
a property generally has an other meaning in qemu (PROP*).
I would rather say you enhance HostIOMMUDeviceIOMMUFD object with 3 new
members, specific to the iommufd BE + 2 new
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> There are three iommufd related elements iommufd handle, devid and
There are three iommufd specific members in HostIOMMUDevice
IOMMUFD that need to be initialized after attach on realize_late() ...
> hwpt_id. hwpt_id is ready only after VFIO device
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> Implement [at|de]tach_hwpt handlers in VFIO subsystem. vIOMMU
> utilizes them to attach to or detach from hwpt on host side.
>
> Signed-off-by: Yi Liu
> Signed-off-by: Zhenzhong Duan
> ---
> hw/vfio/iommufd.c | 22 ++
> 1 file c
On Thu, Feb 20, 2025 at 05:59:10PM +0100, Stefano Brivio wrote:
> On Thu, 20 Feb 2025 10:28:20 -0500
> "Michael S. Tsirkin" wrote:
>
> > On Fri, Jan 24, 2025 at 05:03:27PM +0100, Stefano Brivio wrote:
> > > But I don't understand why we're leaving this as it is.
> >
> > So that people notice i
On 2/20/25 09:12, Peter Maydell wrote:
That suggests that we are correctly implementing the x87
required behaviour in QEMU, and so that the TODO comment
I add in this patch isn't right. But then I'm a bit confused
about what the code is actually doing. Why do we need to look
at fmt->m68k_denormal
Hi Zhenzhong,
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> Signed-off-by: Zhenzhong Duan
> ---
> include/system/host_iommu_device.h | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/include/system/host_iommu_device.h
> b/include/system/host_iommu_device.h
> index df782598f2..18f8
On 2/20/25 7:41 PM, Eric Auger wrote:
> Hi Zhenzhong,
>
>
> On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
>> Signed-off-by: Zhenzhong Duan
>> ---
>> include/system/host_iommu_device.h | 8
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/include/system/host_iommu_device.h
>> b/inc
I'm trying to debug some functional tests that fail for me
with 'make check-functional' on a debug build. Consistently
(well, same set of tests in two runs) when I run
'make -j8 check-functional' these fail:
7/44 qemu:func-thorough+func-arm-thorough+thorough / func-arm-arm_sx1
+cc qemu-riscv, Alistar.
On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote:
> Booting the microchip-icicle-kit machine using the latest PolarFire SoC
> Hart Software Services (HSS) no longer works since Qemu lacks support
> for several registers (clocks, DRAM controller). Also readin
On Thu, 20 Feb 2025 at 18:39, Richard Henderson
wrote:
>
> On 2/20/25 09:12, Peter Maydell wrote:
> > That suggests that we are correctly implementing the x87
> > required behaviour in QEMU, and so that the TODO comment
> > I add in this patch isn't right. But then I'm a bit confused
> > about wha
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> Implement query of HOST_IOMMU_DEVICE_CAP_ERRATA for IOMMUFD
> backed host IOMMU device.
>
> Query on this capability is not supported for legacy backend
> because there is no plan to support nesting with leacy backend
legacy
> backed host device.
>
>
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> Implement query of HOST_IOMMU_DEVICE_CAP_[NESTING|FS1GP] for IOMMUFD
> backed host IOMMU device.
>
> Query on these two capabilities is not supported for legacy backend
> because there is no plan to support nesting with leacy backend backed
> host dev
Hi Zhenzhong
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> Hi,
>
> Per Jason Wang's suggestion, iommufd nesting series[1] is split into
> "Enable stage-1 translation for emulated device" series and
> "Enable stage-1 translation for passthrough device" series.
>
> This series is 2nd part focusing o
On 20.02.25 17:13, Jean-Philippe Brucker wrote:
For Arm CCA we'd like the guest_memfd discard notifier to call the IOMMU
notifiers and create e.g. VFIO mappings. The default VFIO discard
notifier isn't sufficient for CCA because the DMA addresses need a
translation (even without vIOMMU).
At the
Am 13. Februar 2025 00:13:24 UTC schrieb BALATON Zoltan :
>On Wed, 12 Feb 2025, Bernhard Beschow wrote:
>> Am 7. Februar 2025 01:12:38 UTC schrieb BALATON Zoltan :
>>> On Thu, 6 Feb 2025, Bernhard Beschow wrote:
Am 2. Februar 2025 01:25:22 UTC schrieb BALATON Zoltan
:
I had
On Thu, 20 Feb 2025 13:21:33 -0500
"Michael S. Tsirkin" wrote:
> On Thu, Feb 20, 2025 at 05:59:10PM +0100, Stefano Brivio wrote:
> > On Thu, 20 Feb 2025 10:28:20 -0500
> > "Michael S. Tsirkin" wrote:
> >
> > > On Fri, Jan 24, 2025 at 05:03:27PM +0100, Stefano Brivio wrote:
> > > > But I don
On Wed, Feb 19, 2025 at 8:22 AM Markus Armbruster wrote:
> John Snow writes:
>
> > "The text handler you add looks just like the existing latex handler.
> Does
> > LaTeX output lack "little headings", too?"
> >
> > Yes, almost certainly. Can you let me know which output formats we
> actually
> >
On Thu, Feb 20, 2025 at 03:48:17PM +0100, Juraj Marcin wrote:
> Maybe it could be also useful to add assertions to places where locked
> BQL is assumed and the assumption is not clear enough. Then, when
> something changes, it will fail with a clear reason instead of debugging
> race conditions tha
On Thu, Feb 20, 2025 at 09:00:04PM +0100, Stefano Brivio wrote:
> On Thu, 20 Feb 2025 13:21:33 -0500
> "Michael S. Tsirkin" wrote:
>
> > On Thu, Feb 20, 2025 at 05:59:10PM +0100, Stefano Brivio wrote:
> > > On Thu, 20 Feb 2025 10:28:20 -0500
> > > "Michael S. Tsirkin" wrote:
> > >
> > > > On
On Mon, Jan 20, 2025 at 05:41:32PM +, CLEMENT MATHIEU--DRIF wrote:
> From: Clement Mathieu--Drif
>
> This patch set belongs to a list of series that add SVM support for VT-d.
>
> Here we focus on implementing ATS support in the IOMMU and adding a
> PCI-level API to be used by virtual devices
On 17/2/25 00:07, Richard Henderson wrote:
Use the fully general extract opcodes instead.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 10 -
tcg/aarch64/tcg-target-has.h | 10 -
tcg/arm/tcg-target-has.h | 4 -
tcg/i386/tcg-target-has.h| 1
This is more like a cosmetics fix since the f_cd_fetch and f_ste_fetch are
basically the same field since they are in the exact same union with exact
same type.
Signed-off-by: Nicolin Chen
---
hw/arm/smmuv3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3.c b/h
On 17/2/25 00:07, Richard Henderson wrote:
Use the fully general extract opcodes instead.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 10 -
tcg/aarch64/tcg-target-has.h | 10 -
tcg/arm/tcg-target-has.h | 4 -
tcg/i386/tcg-target-has.h| 1
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> While we model a 16-elements RX FIFO since the PL011 model was
> introduced in commit cdbdb648b7c ("ARM Versatile Platform Baseboard
> emulation"), we only read 1 char at a time!
>
> Have the IOCanReadHandler handler return how many element
Hi Phil,
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> We shouldn't receive characters when the full UART or its
> receiver is disabled. However we don't want to break the
> possibly incomplete "my first bare metal assembly program"s,
> so we choose to simply display a warning when thi
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> While we model a 8-elements RX FIFO since the PL011 model was
> introduced in commit 97398d900ca ("bcm2835_aux: add emulation
> of BCM2835 AUX block") we only read 1 char at a time!
I'm not sure I get why in this patch and the subsequent on
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> In the IOCanReadHandler sh_serial_can_receive(), if the Serial
> Control Register 'Receive Enable' bit is set (bit 4), then we
> returns a size of (1 << 4) which happens to be equal to 16,
return
> so effectively SH_RX_FIFO_LENGTH.
>
> The
On 20/2/25 09:21, Luc Michel wrote:
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
While we model a 8-elements RX FIFO since the PL011 model was
introduced in commit 97398d900ca ("bcm2835_aux: add emulation
of BCM2835 AUX block") we only read 1 char at a time!
I'm not sure I get why i
On Wed, 19 Feb 2025 at 15:00, Alex Bennée wrote:
>
> Hi,
>
> As I was looking at the native context patches I realised our existing
> GPU testing is a little sparse. I took the opportunity to split the
> test from the main virt test and then extend it to exercise the 3
> current display modes (vir
Hi,
> Yes, we should have an easy way for machine to allow, in addition to -M
> graphics=BOOLEAN, the structured property -M
> graphics.{width,height,depth,enabled}. Then '-g' can desugar to -M
> graphics.width=WW,graphics.height=HH,graphics.depth=BB.
>
> > It is also used to set TYPE_NUBUS_MAC
Wrap access to errno, for use in the block layer and character device
bindings.
This first version of errno.rs focuses on io::Result. Kevin
suggested allowing conversion from io::Error to negative errno.
For now, I'd rather avoid that to encourage separation between code
that can propagate errors
This allows access to errno values.
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
rust/Cargo.lock | 7
rust/qemu-api/Cargo.toml | 1 +
scripts/archive-source.sh | 2 +-
scripts/make-release
On 9/2/25 11:36, Bernhard Beschow wrote:
TYPE_CHIPIDEA models an IP block which is also used in TYPE_ZYNQ_MACHINE which
itself is not an IMX device. CONFIG_ZYNQ selects CONFIG_USB_EHCI_SYSBUS while
TYPE_CHIPIDEA is a separate compilation unit, so only works by accident if
CONFIG_IMX is given. Fix
Hi Conor,
On 20/2/25 19:30, Conor Dooley wrote:
+cc qemu-riscv, Alistar.
On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote:
Booting the microchip-icicle-kit machine using the latest PolarFire SoC
Hart Software Services (HSS) no longer works since Qemu lacks support
for several re
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