SMMUTransCfg->ttb is never used in QEMU, TT base address
can be accessed by SMMUTransCfg->tt[i]->ttb.
Signed-off-by: JianChunfu
---
include/hw/arm/smmu-common.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index d1a4a6455..e5ad55b
Uniform the removal judgement of g_hash_table_foreach_remove(), previous
name seems to perform the actual action while it just returns a Boolean.
Signed-off-by: JianChunfu
---
v2: - move smmuv3_invalidate_ste() to smmu_hash_remove_by_sid_range()
- add function smmu_configs_inv_sid_range()
v1:
Normally, there is no need to perform firmware reconfiguration once the
virtal machine has started. Hence, currently ovmf firmware parsing happens only
once. However, if the firmware changes betweeen boots then reconfiguration needs
to happen again. Firmware can change if for example the guest brin
Em Wed, 05 Feb 2025 09:16:53 +0100
Markus Armbruster escreveu:
> Mauro Carvalho Chehab writes:
>
> > Using the QMP GHESv2 API requires preparing a raw data array
> > containing a CPER record.
> >
> > Add a helper script with subcommands to prepare such data.
> >
> > Currently, only ARM Processo
On 2/20/25 3:55 AM, Igor Mammedov wrote:
On Fri, 14 Feb 2025 14:16:35 +1000
Gavin Shan wrote:
The error -1 is returned if the previously reported CPER error
hasn't been claimed. The virtual machine is terminated due to
abort(). It's conflicting to the ideal behaviour that the affected
vCPU ret
The memory and IO BARs for devices are only accessible in the D0
power state. In other power states the PCI spec defines that the
device should respond to TLPs and messages with an Unsupported
Request response. The closest we can come to emulating this
behavior is to consider the BARs as unmapped
On Fri, Feb 21, 2025 at 4:46 AM Michael S. Tsirkin wrote:
>
> On Thu, Feb 20, 2025 at 09:00:04PM +0100, Stefano Brivio wrote:
> > On Thu, 20 Feb 2025 13:21:33 -0500
> > "Michael S. Tsirkin" wrote:
> >
> > > On Thu, Feb 20, 2025 at 05:59:10PM +0100, Stefano Brivio wrote:
> > > > On Thu, 20 Feb 202
Queued in loongarch-next with title and changelog changed as follows:
target/loongarch/gdbstub: Fix gdbstub incorrectly handling some registers
Write operation with R32 (orig_a0) and R34 (CSR_BADV) is discarded on
Regards
Bibo Mao
On 2025/2/18 上午11:20, Bibo Mao wrote:
Write operation with R3
On 2/20/2025 09:57, Michael S. Tsirkin wrote:
On Tue, Feb 11, 2025 at 10:19:23AM -0600, Konstantin Shkolnyy wrote:
Add .set_vnet_le() function that always returns success, assuming that
vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and
outputs the message:
"backend doe
Hi Cedric,
> Cc: Troy Lee
> Subject: Re: [PATCH v3 04/28] hw/arm/aspeed: Rename IRQ table and machine
> name for AST2700 A0
>
> On 2/13/25 04:35, Jamin Lin wrote:
> > Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename
> > its IRQ table and machine name.
> >
> > Signed-off-by:
On 2/21/2025 3:39 AM, David Hildenbrand wrote:
> On 20.02.25 17:13, Jean-Philippe Brucker wrote:
>> For Arm CCA we'd like the guest_memfd discard notifier to call the IOMMU
>> notifiers and create e.g. VFIO mappings. The default VFIO discard
>> notifier isn't sufficient for CCA because the DMA a
Add SI705x temperature sensor with I2C interface and allow setting
temperature, VDD status and measurement resolution through properties.
This commit adds support for interfacing with it and implements
functionality for sensor's commands.
Datasheet: https://www.integrated-circuit.com/pdf/502/391/4
On the incoming migration side, QEMU uses a coroutine to load all the VM
states. Inside, it may reference MigrationState on global states like
migration capabilities, parameters, error state, shared mutexes and more.
However there's nothing yet to make sure MigrationState won't get
destroyed (e.g
... and also to require it (--enable-pvg). While at it, unify the dependency()
call for pvg and metal, which simplifies the logic a bit.
Note that all other Apple frameworks are either required or always-present,
therefore do not add them to the summary in the same way as PVG.
Signed-off-by: Pao
PVG is not cross-architecture; the PVG guest drivers with x86-64 macOS do not
give
useful results with the aarch64 macOS host PVG framework, and vice versa.
To express this repurpose CONFIG_MAC_PVG, making it true only if the target has
the same architecture as the host. Furthermore, remove apple
Do not enable Apple ParavirtualizedGraphics on cross-architecture targets,
where it is not supported by the drivers, and add an option to configure it
out just like most others external dependencies.
Only compile-tested on non-Mac for now, but CI is in progress.
Paolo
Paolo Bonzini (2):
pvg: d
On Wed, 19 Feb 2025 at 15:00, Alex Bennée wrote:
>
> Hi,
>
> As I was looking at the native context patches I realised our existing
> GPU testing is a little sparse. I took the opportunity to split the
> test from the main virt test and then extend it to exercise the 3
> current display modes (vir
Prasad Pandit writes:
> Hello,
>
> On Wed, 19 Feb 2025 at 22:53, Fabiano Rosas wrote:
>> I don't see anything stopping postcopy_start() from being called in the
>> source in relation to multifd recv threads being setup in the
>> destination. So far it seems possible that the source is opening th
On Thu, 20 Feb 2025 at 11:29, Peter Maydell wrote:
>
> On Wed, 19 Feb 2025 at 15:00, Alex Bennée wrote:
> >
> > Hi,
> >
> > As I was looking at the native context patches I realised our existing
> > GPU testing is a little sparse. I took the opportunity to split the
> > test from the main virt te
Hi Alex, Ard, Gerd,
Thanks for roping me in,
On Thu, 13 Feb 2025 at 12:13, Ard Biesheuvel wrote:
>
> On Thu, 13 Feb 2025 at 11:11, Alexander Graf wrote:
> >
> >
> > On 13.02.25 10:41, Ard Biesheuvel wrote:
> > > On Tue, 11 Feb 2025 at 10:23, Gerd Hoffmann wrote:
> > >> This patch adds a virtua
On Sun, 9 Feb 2025 at 10:36, Bernhard Beschow wrote:
>
> TYPE_CHIPIDEA models an IP block which is also used in TYPE_ZYNQ_MACHINE which
> itself is not an IMX device. CONFIG_ZYNQ selects CONFIG_USB_EHCI_SYSBUS while
> TYPE_CHIPIDEA is a separate compilation unit, so only works by accident if
> CON
On Wed, 19 Feb 2025 at 16:55, Stephen Longfield wrote:
>
> The problem is internal to t32_expandimm_imm, the imm intermediate
> immediate value.
>
> It's extracted via: int imm = extract32(x, 0, 8);, so the value will be
> between 0-255
>
> It is then multiplied by one of 1, 0x00010001, 0x01000100
Peter Xu writes:
> On the incoming migration side, QEMU uses a coroutine to load all the VM
> states. Inside, it may reference MigrationState on global states like
> migration capabilities, parameters, error state, shared mutexes and more.
>
> However there's nothing yet to make sure MigrationSt
On Fri, Dec 13, 2024 at 05:26:37PM +, Hendrik Wuethrich wrote:
> From: Hendrik Wüthrich
>
> The aim of this patch series is to emulate Intel RDT features in order
> to make testing of the linux Resctrl subsystem possible with Qemu.
>
> A branch with the patches applied can be found at:
> htt
Am 20.02.2025 um 07:35 hat Zhao Liu geschrieben:
> > +/// Use QEMU's event loops to run a Rust [`Future`] to completion and
> > return its result.
> > +///
> > +/// This function must be called in coroutine context. If the future isn't
> > ready yet, it yields.
> > +pub fn qemu_co_run_future(futu
On Thu, Jan 16, 2025 at 10:59:10AM +, Daniel P. Berrangé wrote:
> On Thu, Jan 16, 2025 at 09:19:20AM +, Daniel P. Berrangé wrote:
> > On Thu, Jan 16, 2025 at 09:48:50AM +0100, Philippe Mathieu-Daudé wrote:
> > > On 16/1/25 07:46, Thomas Huth wrote:
> > > > We now have a general note about v
On Thu, 20 Feb 2025 10:57:22 +0530
Vinayak Holikatti wrote:
> CXL spec 3.2 section 8.2.10.9.5.3 describes media operations commands.
> CXL devices supports media operations discovery command.
>
> Signed-off-by: Vinayak Holikatti
Hi Vinayak,
Rather than go around again, I've applied this to my
On Tue, Jan 21, 2025 at 10:01:21PM +0800, Zhao Liu wrote:
> At present, the hpet_cfg is written unconditionally since 40ac17cd56eb
> ("pass info about hpets to seabios.]"), because it concerns ACPI HPET is
> created unconditionally.
>
> But that fact has changed since 51124bbfd2ea ("i386: acpi: Do
On Wed, 19 Feb 2025 at 18:46, Hao Wu wrote:
>
> This allows different FIUs to have different flash sizes, useful
> in NPCM8XX which has multiple different sized FIU modules.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Hao Wu
> Reviewed-by: Philippe Mathieu-Daude
> @@ -543,6 +554,7 @@ stati
On 20/02/2025 15.59, Michael S. Tsirkin wrote:
On Thu, Jan 16, 2025 at 10:59:10AM +, Daniel P. Berrangé wrote:
On Thu, Jan 16, 2025 at 09:19:20AM +, Daniel P. Berrangé wrote:
On Thu, Jan 16, 2025 at 09:48:50AM +0100, Philippe Mathieu-Daudé wrote:
On 16/1/25 07:46, Thomas Huth wrote:
W
On Tue, 18 Feb 2025 10:58:00 +0530
Sweta Kumari wrote:
Title is a bit long so I cut it after commands.
> 1)get alert configuration(Opcode 4201h)
> 2)set alert configuration(Opcode 4202h)
>
> The patch is generated against the Johnathan's tree
> https://gitlab.com/jic23/qemu.git and branch cxl-2
On 17/2/25 14:06, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (5):
accel/accel-cpu-target.h: Include missing 'cpu.h' header
accel/tcg: Include missing bswap headers in user-exec.c
accel/tcg: Take mmap lock in the whole cpu_memory_rw_debug() function
accel/tcg: Avoid using lo
On Thu, Feb 20, 2025 at 11:06:12AM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On the incoming migration side, QEMU uses a coroutine to load all the VM
> > states. Inside, it may reference MigrationState on global states like
> > migration capabilities, parameters, error state, shared m
On Fri, Jan 31, 2025 at 10:55:26AM +0100, Eric Auger wrote:
>
> I tested [PATCH] virtio: Remove virtio devices on device_shutdown()
> https://lore.kernel.org/all/20240808075141.3433253-1-kirill.shute...@linux.intel.com/
>
> and it fixes my issue
>
> Eric
To make sure, we are dropping this in f
On Thu, Feb 20, 2025 at 3:50 PM Michael S. Tsirkin wrote:
>
> On Fri, Dec 13, 2024 at 05:26:37PM +, Hendrik Wuethrich wrote:
> > From: Hendrik Wüthrich
> >
> > The aim of this patch series is to emulate Intel RDT features in order
> > to make testing of the linux Resctrl subsystem possible wi
On Fri, Feb 07, 2025 at 02:53:43PM +0900, Akihiko Odaki wrote:
> object_property_help() uses the conventional command line syntax instead
> of the JSON syntax. In particular,
> - Key-value pairs are written in the command line syntax.
> - bool description passed to the function says on/off instead
On Fri, 13 Dec 2024 17:26:38 +
Hendrik Wuethrich wrote:
> From: Hendrik Wüthrich
>
> Change config to show RDT, add minimal code to the rdt.c module to make
> sure things still compile.
>
> Signed-off-by: Hendrik Wüthrich
Hi,
A few drive by comments.
> ---
> hw/i386/Kconfig | 4
On Sat, Feb 08, 2025 at 04:51:10PM +0900, Akihiko Odaki wrote:
> Some features are not always available with vhost. Legacy features are
> not available with vp_vdpa in particular. virtio devices used to disable
> them when not available even if the corresponding properties were
> explicitly set to
On Thu, 20 Feb 2025 10:57:24 +0530
Vinayak Holikatti wrote:
> CXL spec 3.2 section 8.2.10.9.5.3 describes media operations commands.
> CXL devices supports media operations Sanitize and Write zero command.
>
> Signed-off-by: Vinayak Holikatti
Another one where I made some minor tweaks whilst a
Peter Maydell writes:
> On Wed, 19 Feb 2025 at 15:00, Alex Bennée wrote:
>>
>> Hi,
>>
>> As I was looking at the native context patches I realised our existing
>> GPU testing is a little sparse. I took the opportunity to split the
>> test from the main virt test and then extend it to exercise th
On Thu, 20 Feb 2025 08:07:23 -0700
Alex Williamson wrote:
> On Thu, 20 Feb 2025 11:45:35 +0100
> Eric Auger wrote:
>
> > Hi Alex,
> >
> > On 2/20/25 11:31 AM, Eric Auger wrote:
> > >
> > > Hi Alex,
> > >
> > > On 2/19/25 10:19 PM, Alex Williamson wrote:
> > >> On Wed, 19 Feb 2025 11:58
Gerd Hoffmann writes:
> Define qapi schema for the uefi variable store state.
>
> Use it and the generated visitor helper functions to store persistent
> (EFI_VARIABLE_NON_VOLATILE) variables in JSON format on disk.
>
> Signed-off-by: Gerd Hoffmann
[...]
> diff --git a/qapi/meson.build b/qapi/
+ Suravee
On 2/17/25 02:26, Philippe Mathieu-Daudé wrote:
On 31/7/24 19:00, Peter Maydell wrote:
In amdvi_update_iotlb() we will only put a new entry in the hash
table if to_cache.perm is not IOMMU_NONE. However we allocate the
memory for the new AMDVIIOTLBEntry and for the hash table key
rega
On Thu, Feb 20, 2025 at 05:40:38PM +0800, Li Zhijian wrote:
> On 19/02/2025 22:11, Peter Xu wrote:
> > then
> > in the test it tries to detect rdma link and fetch the ip only
> It should work without root permission if we just*detect* and*fetch ip*.
>
> Do you also mean we c
Peter Xu writes:
> On Thu, Feb 20, 2025 at 11:06:12AM -0300, Fabiano Rosas wrote:
>> Peter Xu writes:
>>
>> > On the incoming migration side, QEMU uses a coroutine to load all the VM
>> > states. Inside, it may reference MigrationState on global states like
>> > migration capabilities, paramet
On Tue, Feb 11, 2025 at 10:19:23AM -0600, Konstantin Shkolnyy wrote:
> Add .set_vnet_le() function that always returns success, assuming that
> vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and
> outputs the message:
> "backend does not support LE vnet headers; falling ba
Hi Michael,
On 2/20/25 4:25 PM, Michael S. Tsirkin wrote:
> On Fri, Jan 31, 2025 at 10:55:26AM +0100, Eric Auger wrote:
>> I tested [PATCH] virtio: Remove virtio devices on device_shutdown()
>> https://lore.kernel.org/all/20240808075141.3433253-1-kirill.shute...@linux.intel.com/
>>
>> and it fixe
On 2025-02-20 11:06, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On the incoming migration side, QEMU uses a coroutine to load all the VM
> > states. Inside, it may reference MigrationState on global states like
> > migration capabilities, parameters, error state, shared mutexes and more.
> >
On Tue, 18 Feb 2025 14:27:28 +0530
Arpit Kumar wrote:
> CXL CCI log commands implmented as per CXL Specification 3.2 8.2.10.5
> 1) get_log_capabilities (Opcode 0402h)
> 2) clear_log (Opcode 0403h)
> 3) populate_log (Opcode 0404h)
>
> This v2 patch addresses the feedback from the v1 patch and inc
On Mon, 17 Feb 2025 19:20:39 +0800
Yuquan Wang wrote:
> Add serial number parameter in the cxl persistent examples.
>
> Signed-off-by: Yuquan Wang
Looks good. I've queued it up on my gitlab staging tree, but
Michael if you want to pick this one directly that's fine as well.
I should be pushin
Explictly reset env->mstatus and env->sie. Add a comment about env->mip
being read/written into KVM 'sip' CSR.
We're also not read/writing 'scounteren' which is available in the KVM
UAPI. Add it in kvm_reset() and get/put_regs_csr().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/kvm/k
Using env->sie is clearer than using env->mie.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/kvm/kvm-cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 484b6afe7c..fea03f3657 100644
--- a/target/ri
Hi,
These patches were done in the context of gitlab #2573 [1]. The gitlab
entry per se will probably be closed as a guest software bug, but while
working on it I noticed that we're writing a TCG-initialized
env->mstatus in KVM.
This is happening because riscv_cpu_reset_hold() is doing all TCG
re
riscv_cpu_reset_hold() does a lot of TCG-related initializations that
aren't relevant for KVM, but nevertheless are impacting the reset state
of KVM vcpus.
When running a KVM guest, kvm_riscv_reset_vcpu() is called at the end of
reset_hold(). At that point env->mstatus is initialized to a non-zero
In Arm CCA, the guest-physical address space is split in half. The top
half represents memory shared between guest and host, and the bottom
half is private to the guest. From QEMU's point of view, the two halves
are merged into a single region, and pages within this region are
either shared or priv
These two patches will be included in the series that adds support for
Arm CCA guests to QEMU, which isn't ready to be merged [1], but I'm sending
them as RFC first to seek advice about the best way to implement this.
There is a breaking change to CCA guests, where DMA addresses now have
the "shar
For Arm CCA we'd like the guest_memfd discard notifier to call the IOMMU
notifiers and create e.g. VFIO mappings. The default VFIO discard
notifier isn't sufficient for CCA because the DMA addresses need a
translation (even without vIOMMU).
At the moment:
* guest_memfd_state_change() calls the pop
On Wed, 19 Feb 2025 at 18:46, Hao Wu wrote:
>
> Changes since v4:
>
> 1. Bump vmstate versions on NPCM CLK and GCR modules.
> 2. Remove "hw/boards.h" include in npcm8xx.h and add it in npcm8xx*.c
> 3. Use cpu_to_le32 instead of tswap32 in npcm8xx.c
>
I've applied this to target-arm.next with the
From: Hao Wu
A lot of NPCM7XX and NPCM8XX GCR modules share the same code,
this commit moves the NPCM7XX GCR to NPCM GCR for these
properties.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Message-id: 20250219184609.1839281-6-wuhao...@google.com
Signed-off-by: Peter Maydell
---
include/hw
There are no longer any uses of CP_ACCESS_TRAP in access functions,
because we have converted them all to use either CP_ACCESS_TRAP_EL1
or CP_ACCESS_TRAP_UNCATEGORIZED, as appropriate. Remove the handling
of bare CP_ACCESS_TRAP from the access_check_cp_reg() helper, so that
it now asserts if an acc
The pseudocode for the accessors for the LOR sysregs says they
are UNDEFINED if SCR_EL3.NS is 0. We were reporting the wrong
syndrome value here; use CP_ACCESS_TRAP_UNCATEGORIZED.
Cc: qemu-sta...@nongnu.org
Fixes: 2d7137c10faf ("target/arm: Implement the ARMv8.1-LOR extension")
Signed-off-by: Pete
R_NYXTL says that these AT insns should be UNDEFINED if they
would operate on an EL lower than EL3 and SCR_EL3.{NSE,NS} is
set to the Reserved {1, 0}. We were incorrectly reporting
them with the wrong syndrome; use CP_ACCESS_TRAP_UNCATEGORIZED
so they are reported as UNDEFINED.
Cc: qemu-sta...@non
From: Philippe Mathieu-Daudé
Implicit default values are often hard to figure out, better
be explicit. Now that all boards explicitly set the number of
GIC external IRQs, remove the default values (displaying an
error message if it is out of range).
Signed-off-by: Philippe Mathieu-Daudé
Reviewe
From: Hao Wu
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Message-id: 20250219184609.1839281-8-wuhao...@google.com
Signed-off-by: Peter Maydell
---
include/hw/misc/npcm_gcr.h | 6 +-
hw/misc/npcm_gcr.c | 133 -
2 files changed, 134 insertions(
From: Hao Wu
These 2 values are different between NPCM7XX and NPCM8XX
GCRs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Message-id: 20250219184609.1839281-7-wuhao...@google.com
Signed-off-by: Peter Maydell
---
include/hw/m
o
staging (2025-02-19 08:36:45 +0800)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20250220
for you to fetch changes up to 1c3169179b8242866316108386800379c4e22974:
docs/system/arm: Add Description for NPCM8XX SoC (2025-0
The access pseudocode for the CNTPS_TVAL_EL1, CNTPS_CTL_EL1 and
CNTPS_CVAL_EL1 secure timer registers says that they are UNDEFINED
from EL2 or NS EL1. We incorrectly return CP_ACCESS_TRAP from the
access function in these cases, which means that we report the wrong
syndrome value to the target EL.
From: Hao Wu
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Message-id: 20250219184609.1839281-17-wuhao...@google.com
Signed-off-by: Peter Maydell
---
include/hw/arm/npcm8xx.h | 21
hw/arm/npcm8xx_boards.c | 253 +++
hw/arm/meson.build | 2
From: Hao Wu
These 2 values are different between NPCM7XX and NPCM8XX
CLKs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Message-id: 20250219184609.1839281-13-wuhao...@google.com
Signed-off-by: Peter Maydell
---
include/hw/
From: Hao Wu
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
Message-id: 20250219184609.1839281-16-wuhao...@google.com
Signed-off-by: Peter Maydell
---
configs/devices/aarch64-softmmu/default.mak | 1 +
include/hw/arm/npcm8xx.h| 106 +++
hw/arm/npcm8xx.c
On XScale CPUs, there is no EL2 or AArch64, so no syndrome register.
These traps are just UNDEFs in the traditional AArch32 sense, so
CP_ACCESS_TRAP_UNCATEGORIZED is more accurate than CP_ACCESS_TRAP.
This has no visible behavioural change, because the guest doesn't
have a way to see the syndrome v
From: Stephen Longfield
In t32_expandimm_imm(), we take an 8 bit value XY and construct a
32-bit value which might be of the form XY, 00XY00XY, XY00XY00, or
XYXYXYXY. We do this with multiplications, and we use an 'int' type.
For the cases where we're setting the high byte of the 32-bit value
to
The code for WFI/WFE trapping has several errors:
* it wasn't using arm_sctlr(), so it would look at SCTLR_EL1
even if the CPU was in the EL2&0 translation regime
* it was raising UNDEF, not Monitor Trap, for traps to
AArch32 EL3 because of SCR.{TWE,TWI}
* it was not honouring SCR.{TWE,TWI
From: Hao Wu
This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one
it supports loading the UBoot from the SPI device and not more.
We updated the npcm7xx bootrom to be compiled from this version.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Message-id: 20250219184609.1839281-2-
In the gicv3_{irq,fiq,irqfiq}_access() functions, there is a check
which downgrades a CP_ACCESS_TRAP_EL3 to CP_ACCESS_TRAP if EL3 is not
AArch64. This has been there since the GIC was first implemented,
but it isn't right: if we are trapping because of SCR.IRQ or SCR.FIQ
then we definitely want to
From: Hao Wu
This allows different FIUs to have different flash sizes, useful
in NPCM8XX which has multiple different sized FIU modules.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Reviewed-by: Philippe Mathieu-Daude
Message-id: 20250219184609.1839281-4-wuhao...@google.com
[PMM: flash_si
From: Philippe Mathieu-Daudé
The 32 IRQ lines skipped are the GIC internal ones.
Use the GIC_INTERNAL definition for clarity.
No logical change.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20250212154333.28644-2-phi...@linaro.org
Signed-off-by: Peter Maydel
CP_ACCESS_TRAP_UNCATEGORIZED is technically an accurate description
of what this return value from a cpreg accessfn does, but it's liable
to confusion because it doesn't match how the Arm ARM pseudocode
indicates this case. What it does is an EXCP_UDEF with a zero
("uncategorized") syndrome value,
From: Hao Wu
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu
Reviewe
There are not many traps in AArch32 which should trap to Monitor
mode, but these trap bits should trap not just lower ELs to Monitor
mode but also the non-Monitor modes running at EL3 (i.e. Secure
System, Secure Undef, etc).
We get this wrong because the relevant access functions implement the
AA
From: Philippe Mathieu-Daudé
Looking at the Zynq 7000 SoC Technical Reference Manual (UG585 v1.14)
on Appendix A: Register Details, the mpcore Interrupt Controller Type
Register (ICDICTR) has the IT_Lines_Number field read-only with value
0x2, described as:
IT_Lines_Number
b00010 =
From: Bernhard Beschow
TYPE_CHIPIDEA models an IP block which is also used in TYPE_ZYNQ_MACHINE which
itself is not an IMX device. CONFIG_ZYNQ selects CONFIG_USB_EHCI_SYSBUS while
TYPE_CHIPIDEA is a separate compilation unit, so only works by accident if
CONFIG_IMX is given. Fix that by extractin
We currently use CP_ACCESS_TRAP in a number of access functions where
we know we're currently at EL0; in this case the "usual target EL"
is EL1, so CP_ACCESS_TRAP and CP_ACCESS_TRAP_EL1 behave the same.
Use CP_ACCESS_TRAP_EL1 to more closely match the pseudocode for
this sort of check.
Note that i
From: Philippe Mathieu-Daudé
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"). Add the GIC_EXT_IRQS definition (with a comment)
to make that explicit.
Except explicitly setting a property value
From: Philippe Mathieu-Daudé
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"). Add the GIC_EXT_IRQS definition (with a comment)
to make that explicit.
Except explicitly setting a property value
In the gicv3_{irq,fiq,irqfiq}_access() functions, in the
arm_current_el(env) == 3 case we do the following test:
if (!is_a64(env) && !arm_is_el3_or_mon(env)) {
r = CP_ACCESS_TRAP_EL3;
}
In this check, the "!is_a64(env)" is redundant, because if
we are at EL3 and in AArch64 then arm
In the CPAccessResult enum, the CP_ACCESS_TRAP* values indicate the
equivalent of the pseudocode AArch64.SystemAccessTrap(..., 0x18),
causing a trap to a specified exception level with a syndrome value
giving information about the failing instructions. In the
pseudocode, such traps are always take
From: Hao Wu
A lot of NPCM7XX and NPCM8XX CLK modules share the same code,
this commit moves the NPCM7XX CLK to NPCM CLK for these
properties.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Message-id: 20250219184609.1839281-12-wuhao...@google.com
Signed-off-by: Peter Maydell
---
include/h
From: Hao Wu
NPCM8XX adds a few new registers and have a different set of reset
values to the CLK modules. This patch supports them.
This patch doesn't support the new clock values generated by these
registers. Currently no modules use these new clock values so they
are not necessary at this poi
From: Hao Wu
The bootrom is a minimal bootrom used to load an NPCM8XX image.
The source code is located in the same repo as the NPCM7XX one:
github.com/google/vbootrom/tree/master/npcm8xx.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Message-id: 20250219184609.1839281-3-wuhao...@google.com
From: Philippe Mathieu-Daudé
We already have a definition to distinct GIC internal
IRQs versus external ones, use it. No logical changes.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20250212154333.28644-5-phi...@linaro.org
Signed
From: Hao Wu
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
This document describes the NPCM8XX SoC and an evaluation board
(NPCM 845 EVB).
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
Message-id: 2025021
From: Hao Wu
The NPCM8xx GCR device can be accessed with 64-bit memory operations.
This patch supports that.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Reviewed-by: Philippe Mathieu-Daude
Message-id: 20250219184609.1839281-10-wuhao...@google.com
Signed-off-by: Peter Maydell
---
hw/mis
From: Hao Wu
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module
needs to fit both. This commit changes the name of the GCR module.
Future commits will add the support for NPCM8XX GCRs.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Message-id: 20250219184609.1839281-5-wuhao.
From: Hao Wu
NPCM7XX and NPCM8XX have a different set of CLK registers. This
commit changes the name of the clk files to be used by both
NPCM7XX and NPCM8XX CLK modules.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Message-id: 20250219184609.1839281-11-wuhao...@google.com
Signed-off-by: Pe
From: Hao Wu
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR
module. Since we don't simulate a detailed memory controller, we
need to store this information directly similar to the NPCM7XX's
INCTR3 register.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Message-id: 20250
The pseudocode for AT S1E2R and AT S1E2W says that they should be
UNDEFINED if executed at EL3 when EL2 is not enabled. We were
incorrectly using CP_ACCESS_TRAP and reporting the wrong exception
syndrome as a result. Use CP_ACCESS_TRAP_UNCATEGORIZED.
Cc: qemu-sta...@nongnu.org
Fixes: 2a47df953202e
On 20/2/25 14:33, Paolo Bonzini wrote:
PVG is not cross-architecture; the PVG guest drivers with x86-64 macOS do not
give
useful results with the aarch64 macOS host PVG framework, and vice versa.
To express this repurpose CONFIG_MAC_PVG, making it true only if the target has
the same architectur
From: Philippe Mathieu-Daudé
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit 528622421eb
"hw/cpu/a15mpcore: Correct default value for num-irq").
The Versati
From: Philippe Mathieu-Daudé
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit 528622421eb
"hw/cpu/a15mpcore: Correct default value for num-irq").
The Caldexa
101 - 200 of 244 matches
Mail list logo
