Re: [PULL v2 11/14] os: add an ability to lock memory on_fault

On Wed, Feb 12, 2025 at 12:38:23PM -0500, Peter Xu wrote: > From: Daniil Tatianin > > This will be used in the following commits to make it possible to only > lock memory on fault instead of right away. > > Signed-off-by: Daniil Tatianin > Reviewed-by: Vladimir Sementsov-Ogievskiy > Link: > h

Re: [PATCH 1/5] hw/arm: Mark Allwinner Technology devices as little-endian

On 2/12/25 03:39, Philippe Mathieu-Daudé wrote: These devices are only used by the ARM targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LI

Re: [PATCH 2/5] hw/mips: Mark Boston machine devices as little-endian

On 2/12/25 03:39, Philippe Mathieu-Daudé wrote: The Boston machine is only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by: Philipp

Re: [PATCH 3/5] hw/mips: Mark Loonson3 Virt machine devices as little-endian

On 2/12/25 03:39, Philippe Mathieu-Daudé wrote: The Loonson3 Virt machine is only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by:

Re: [PULL v2 11/14] os: add an ability to lock memory on_fault

On Wed, Feb 12, 2025 at 05:48:46PM +, Daniel P. Berrangé wrote: > On Wed, Feb 12, 2025 at 12:38:23PM -0500, Peter Xu wrote: > > From: Daniil Tatianin > > > > This will be used in the following commits to make it possible to only > > lock memory on fault instead of right away. > > > > Signed-

Re: [PATCH v2 1/8] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition

On 2/12/25 07:43, Philippe Mathieu-Daudé wrote: The 32 IRQ lines skipped are the GIC internal ones. Use the GIC_INTERNAL definition for clarity. No logical change. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/exynos4210.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) Revie

Re: [PATCH v2 2/8] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs

On 2/12/25 07:43, Philippe Mathieu-Daudé wrote: When not specified, Cortex-A9MP configures its GIC with 64 external IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly settin

Re: [PATCH 09/11] rust/block: Add read support for block drivers

Am 12.02.2025 um 16:05 hat Paolo Bonzini geschrieben: > On 2/11/25 22:43, Kevin Wolf wrote: > > +/// A request to a block driver > > +pub enum Request { > > +Read { offset: u64, len: u64 }, > > +} > > + > > Maybe add flags already? > > +#[allow(dead_code)] > > +pub enum MappingTarget { > > +

Re: [PATCH 08/11] rust/block: Add driver module

Am 12.02.2025 um 17:43 hat Paolo Bonzini geschrieben: > On 2/11/25 22:43, Kevin Wolf wrote: > > +/// Reads data from the child node into a linear typed buffer. > > +pub async fn read(&self, offset: u64, buf: &mut > > T) -> io::Result<()> { > > +unsafe { > > +self.read_r

Re: [PATCH v5 3/5] migration: enable multifd and postcopy together

Hi, On Wed, 12 Feb 2025 at 20:08, Peter Xu wrote: > I think it's not because TLS channels don't send magic, but TLS channels > are not prone to ordering issues. > In general, I'm not convinced we need to check names of iochannels. * If the channel does not set '_READ_MSG_SEEK' flag, which magic

Re: [PULL 00/68] target-arm queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

[PULL v2 06/14] memory: pass MemTxAttrs to memory_access_is_direct()

From: David Hildenbrand We want to pass another flag that will be stored in MemTxAttrs. So pass MemTxAttrs directly. Reviewed-by: Peter Xu Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Hildenbrand Link: https://lore.kernel.org/r/20250210084648.33798-6-da...@redhat.com [peterx: Fix

Re: [PULL 0/2] NBD patches through 2025-02-11

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

[PULL v2 00/14] Mem next patches

The following changes since commit ffaf7f0376f8040ce9068d71ae9ae8722505c42e: Merge tag 'pull-10.0-testing-and-gdstub-updates-100225-1' of https://gitlab.com/stsquad/qemu into staging (2025-02-10 13:26:17 -0500) are available in the Git repository at: https://gitlab.com/peterx/qemu.git tags/

[PULL v2 11/14] os: add an ability to lock memory on_fault

From: Daniil Tatianin This will be used in the following commits to make it possible to only lock memory on fault instead of right away. Signed-off-by: Daniil Tatianin Reviewed-by: Vladimir Sementsov-Ogievskiy Link: https://lore.kernel.org/r/20250212143920.1269754-2-d-tatia...@yandex-team.ru

Re: [PULL 0/6] loongarch-to-apply queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

Re: [PATCH 08/11] rust/block: Add driver module

On 2/11/25 22:43, Kevin Wolf wrote: +/// Reads data from the child node into a linear typed buffer. +pub async fn read(&self, offset: u64, buf: &mut T) -> io::Result<()> { +unsafe { +self.read_raw(offset, buf.buffer_len(), buf.buffer_mut_ptr()) +.await

Re: [PATCH v4 32/33] vfio/migration: Add x-migration-multifd-transfer VFIO property

On 1/30/25 11:08, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" This property allows configuring at runtime whether to transfer the particular device state via multifd channels when live migrating that device. It defaults to AUTO, which means that VFIO device state transfer via multif

Re: [PATCH v4 31/33] vfio/migration: Multifd device state transfer support - send side

On 1/30/25 11:08, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" Implement the multifd device state transfer via additional per-device thread inside save_live_complete_precopy_thread handler. Switch between doing the data transfer in the new handler and doing it in the old save_state h

Re: [PATCH] vdpa: Allow vDPA to work on big-endian machine

On 12/2/25 18:24, Konstantin Shkolnyy wrote: On 2/12/2025 08:52, Philippe Mathieu-Daudé wrote: On 11/2/25 17:19, Konstantin Shkolnyy wrote: Add .set_vnet_le() function that always returns success, assuming that vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and outpu

Re: [PATCH] hw/ppc/e500: Partial implementation of local access window registers

Am 7. Februar 2025 01:12:38 UTC schrieb BALATON Zoltan : >On Thu, 6 Feb 2025, Bernhard Beschow wrote: >> Am 2. Februar 2025 01:25:22 UTC schrieb BALATON Zoltan : >>> On Sat, 1 Feb 2025, Bernhard Beschow wrote: Am 1. Februar 2025 14:55:15 UTC schrieb Bernhard Beschow : > Am 30. Jan

Re: [PATCH v3 19/19] qom: Require TypeInfo::class_data points to const data

On 2/12/25 13:32, Philippe Mathieu-Daudé wrote: All TypeInfo::class_data point to const data. Enforce that in the structure, so future class_data stays in .rodata. Signed-off-by: Philippe Mathieu-Daudé --- include/qom/object.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [PATCH v6 01/11] hw/qdev-properties-system: Introduce EndianMode QAPI enum

On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote: On 12/2/25 17:23, BALATON Zoltan wrote: On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote: On 12/2/25 14:53, Philippe Mathieu-Daudé wrote: On 12/2/25 13:56, BALATON Zoltan wrote: On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote: On 12/2/25

Re: [PULL 04/32] hw/timer/xilinx_timer: Make device endianness configurable

On 10/02/2025 21.41, Philippe Mathieu-Daudé wrote: Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness for each machine usin

[PATCH 1/9] target/microblaze: Split out mb_unaligned_access_internal

Use an explicit 64-bit type for the address to store in EAR. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h| 3 +++ target/microblaze/helper.c | 25 - 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/target/microblaze/cpu.h b/target/micro

Re: [PATCH] hw/ppc/e500: Partial implementation of local access window registers

On Wed, 12 Feb 2025, Bernhard Beschow wrote: Am 7. Februar 2025 01:12:38 UTC schrieb BALATON Zoltan : On Thu, 6 Feb 2025, Bernhard Beschow wrote: Am 2. Februar 2025 01:25:22 UTC schrieb BALATON Zoltan : I had to apply

Re: [PATCH 4/5] hw/arm/smmuv3: Move reset to exit phase

On 2/10/25 15:22, Peter Maydell wrote: On Mon, 10 Feb 2025 at 14:14, Peter Xu wrote: On Fri, Feb 07, 2025 at 06:18:50PM +, Peter Maydell wrote: On Fri, 7 Feb 2025 at 17:48, Peter Xu wrote: On Fri, Feb 07, 2025 at 04:58:39PM +, Peter Maydell wrote: (I wonder if we ought to suggest

Re: [PULL 05/12] vfio/iommufd: Fix SIGSEV in iommufd_cdev_attach()

11.02.2025 17:33, Cédric Le Goater wrote: From: Zhenzhong Duan When iommufd_cdev_ram_block_discard_disable() fails for whatever reason, errp should be set or else SIGSEV is triggered in vfio_realize() when error_prepend() is called. By this chance, use the same error message for both legacy an

Re: [PATCH v3 09/23] hw/uefi: add var-service-core.c

On 12.02.25 16:18, Gerd Hoffmann wrote: Hi, Yes. Knowing both physical and virtual address works only for memory you allocated yourself before ExitBootServices. So you can't pass on pointers from the OS, you have to copy the data to a buffer where you know the physical address instead.

[PATCH v3 11/19] qom: Constify InterfaceInfo[] interfaces

Mechanical change using gsed. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/virtio/virtio-pci.h | 2 +- include/qom/object.h| 4 ++-- authz/list.c| 2 +- authz/l

[PATCH v3 08/19] qom: Have class_base_init() take a const data argument

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/qom/object.h | 2 +- hw/core/machine.c| 2 +- hw/core/qdev.c | 2 +- hw/pci/pci.c | 2 +- qom/object.c | 2 +- rust/qemu-api/src/qom.rs | 2 +- 6 files changed, 6 insert

Re: [PULL v2 11/14] os: add an ability to lock memory on_fault

On Wed, Feb 12, 2025 at 06:03:30PM +, Daniel P. Berrangé wrote: > On Wed, Feb 12, 2025 at 12:56:46PM -0500, Peter Xu wrote: > > On Wed, Feb 12, 2025 at 05:48:46PM +, Daniel P. Berrangé wrote: > > > On Wed, Feb 12, 2025 at 12:38:23PM -0500, Peter Xu wrote: > > > > From: Daniil Tatianin > >

[PATCH v3 12/19] hw/virtio/virtio-pci: Always allocate QOM type base_name

Introduce 'single_generic_device' boolean for clarity. Allocate base_name on entry. Replace the g_free() call by g_autofree qualifier. Use g_strconcat() instead of g_strdup_printf(). Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 11 ++- 1 file changed, 6 insertions(+

[PATCH v3 01/19] hw: Declare various const data as 'const'

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/isa/vt82c686.c | 2 +- hw/rtc/m48t59-isa.c | 2 +- hw/rtc/m48t59.c | 2 +- hw/sensor/tmp421.c| 2 +- hw/usb/hcd-ehci-pci.c | 2 +- hw/usb/hcd-uhci.c | 2 +- 6 files changed, 6 insertions(+), 6 deletio

[PATCH v3 03/19] target/i386: Constify X86CPUModel uses

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/i386/cpu.h | 2 +- target/i386/cpu.c | 8 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c67b42d34fc..f9ce6970ee1 100644 --- a/target/i386/cpu.h ++

[PATCH v3 17/19] hw/virtio/virtio-pci: Reduce generic_type_info scope

Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 25 + 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 6f0e1772669..99724deb3d9 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virti

[PATCH v3 16/19] hw/virtio/virtio-pci: Constify generic_type_info

Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 16 ++-- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index a33d1b2cbcf..6f0e1772669 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@

[PATCH v3 10/19] qom: Constify TypeInfo::class_data

All callers now correctly expect a const class data. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/qom/object.h| 2 +- hw/arm/armsse.c | 2 +- hw/block/m25p80.c

[PATCH v3 18/19] hw: Constify various TypeInfo and associated structures

Constify various TypeInfo structures. When they are generated from an array, also constify the array. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/net/e1000.c | 12 ++-- hw/rtc/m48t59-isa.c| 22 +++--- hw/rtc/m48t59.c

[PATCH v3 06/19] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 97713681cbe..fbe5548cf5a 100644 --- a/target/riscv/cpu.h +++

[PATCH v3 02/19] hw: Make class data 'const'

When the %data argument is not modified, we can declare it const. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/sd/sdhci-internal.h | 2 +- hw/sd/sdhci.c| 2 +- hw/sensor/emc141x.c | 2 +- hw/sensor/isl_pmbus_vr.c | 2 +- 4 files changed, 4 inser

[PATCH v3 15/19] hw/virtio/virtio-pci: Constify base_type_info

Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 9512590c936..a33d1b2cbcf 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -24

[PATCH v3 14/19] hw/virtio/virtio-pci: Do not access base_type_info.name directly

base_type_info.name is initialized to t->base_name, check that directly. Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index ad1d164421d..9512590c936

[PATCH v3 05/19] target/xtensa: Finalize config in xtensa_register_core()

Make XtensaConfigList::config not const. Only modify XtensaConfig within xtensa_register_core(), when the class is registered, not when it is initialized. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Acked-by: Max Filippov --- target/xtensa/cpu.h| 2 +- target/xtens

[PATCH v3 19/19] qom: Require TypeInfo::class_data points to const data

All TypeInfo::class_data point to const data. Enforce that in the structure, so future class_data stays in .rodata. Signed-off-by: Philippe Mathieu-Daudé --- include/qom/object.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/qom/object.h b/include/qom/object.h index

[PATCH v3 04/19] target/sparc: Constify SPARCCPUClass::cpu_def

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/sparc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index dda811503b5..462bcb6c0e6 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -574,

[PATCH v3 07/19] target/riscv: Convert misa_mxl_max using GLib macros

Use GLib conversion macros to pass misa_mxl_max as riscv_cpu_class_init() class data. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cp

[PATCH v2] vdpa: Fix endian bugs in shadow virtqueue

VDPA didn't work on a big-endian machine due to missing/incorrect CPU<->LE data format conversions. Signed-off-by: Konstantin Shkolnyy --- Changes in v2: Change desc_next[] from LE format to "CPU". hw/virtio/vhost-shadow-virtqueue.c | 18 ++ 1 file changed, 10 insertions(+), 8 d

Re: [PATCH v5 1/4] os: add an ability to lock memory on_fault

On Wed, Feb 12, 2025 at 07:17:45PM +0300, Daniil Tatianin wrote: > > > -static inline int os_mlock(void) > > > +static inline int os_mlock(bool on_fault) > > > { > > > +(void)on_fault; > > Is this really needed ? Our compiler flags don't enable warnings > > about unused variables. > > Hmm, I

Re: [PATCH 06/11] rust/block: Add I/O buffer traits

Il mer 12 feb 2025, 18:23 Kevin Wolf ha scritto: > Am 12.02.2025 um 17:48 hat Paolo Bonzini geschrieben: > > On 2/11/25 22:43, Kevin Wolf wrote: > > > +/// Implementing `SizedIoBuffer` provides an implementation for > [`IoBuffer`] without having to > > > +/// implement any functions manually. > >

Re: [PULL 00/32] Misc HW patches for 2025-02-10

On 12/02/2025 05.45, Eldon Stegall wrote: On Wed, Feb 12, 2025 at 02:39:16AM +0100, Thomas Huth wrote: On 12/02/2025 01.41, Thomas Huth wrote: On 11/02/2025 20.03, Philippe Mathieu-Daudé wrote: On 11/2/25 19:53, Philippe Mathieu-Daudé wrote: On 11/2/25 19:48, Philippe Mathieu-Daudé wrote: [.

[PATCH 0/9] target/microblaze: Always use TARGET_LONG_BITS == 32

Use out-of-line helpers to implement extended address memory ops. With this, we can reduce TARGET_LONG_BITS to the more natural 32 for this 32-bit cpu. r~ Richard Henderson (9): target/microblaze: Split out mb_unaligned_access_internal target/microblaze: Split out mb_transaction_failed_inte

[PATCH 7/9] target/microblaze: Use TARGET_LONG_BITS == 32 for system mode

Now that the extended address instructions are handled separately from virtual addresses, we can narrow the emulation to 32-bit. Signed-off-by: Richard Henderson --- configs/targets/microblaze-softmmu.mak | 4 +--- configs/targets/microblazeel-softmmu.mak | 4 +--- 2 files changed, 2 insertion

[PATCH 4/9] target/microblaze: Use uint64_t for CPUMBState.ear

Use an explicit 64-bit type for EAR. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 45f7f49809..01571d4f86 1006

Re: [PATCH v3 18/19] hw: Constify various TypeInfo and associated structures

On 2/12/25 13:32, Philippe Mathieu-Daudé wrote: Constify various TypeInfo structures. When they are generated from an array, also constify the array. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/net/e1000.c | 12 ++-- hw/rtc/m48t59-isa.c

[PATCH 8/9] target/microblaze: Drop DisasContext.r0

Return a constant 0 from reg_for_read, and a new temporary from reg_for_write. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 24 ++-- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/transl

Re: [PATCH] qapi: merge common parts of NbdServerOptions and nbd-server-start data

On Wed, Feb 12, 2025 at 05:33:51PM +0300, Vladimir Sementsov-Ogievskiy wrote: > Instead of comment > "Keep this type consistent with the nbd-server-start arguments", we > can simply merge these things. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > --- > > No problem for me to rebase on top o

Re: [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.

t; Alistair > > > > > > > Sorry for the inconvenience. Strangely cherry-pick, patch and git am -3 > > all seem to work fine but git am seems to be failing. > > > > I looked into the conflict and it looks like am expects > > ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), > > but g

Re: [PATCH 1/3] hw/cxl/cxl-mailbox-utils.c: Added support for Get Log Capabilities (Opcode 0402h)

> >> > >> +static const struct CXLLogCapabilities cxl_get_log_cap[MAX_LOG_TYPE] = { > >> +[CEL] = {.param_flags.pflags = CXL_LOG_CAP_CLEAR | > >> CXL_LOG_CAP_POPULATE, > >> + .uuid = cel_uuid}, > >> +}; > >> + > >> +static void cxl_init_get_log(CXLCCI *cci) > >> +{ > >> +for (i

Re: [PATCH v5 3/5] migration: enable multifd and postcopy together

On Wed, Feb 12, 2025 at 11:06:00PM +0530, Prasad Pandit wrote: > * I was going to send a revised series with these changes, but will > wait on that for now. You were going to send some changes that you don't yet fully understand how it works? How would you do the flush in the new revision if your

Re: [PATCH 5/5] target/i386: Mark WHPX APIC region as little-endian

On 2/12/25 03:39, Philippe Mathieu-Daudé wrote: This device is only used by the x86 targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTL

Re: [PATCH 4/5] hw/pci-host: Mark versatile regions as little-endian

On 2/12/25 03:39, Philippe Mathieu-Daudé wrote: This device is only used by the ARM targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTL

Re: [PATCH] linux-user: Move TARGET_SA_RESTORER out of generic/signal.h

Hi Andreas, On 2025-02-10 13:59:34+0100, Andreas Schwab wrote: > SA_RESTORER and the associated sa_restorer field of struct sigaction are > an obsolete feature, not expected to be used by future architectures. > They are also absent on RISC-V, LoongArch, Hexagon and OpenRISC, but > defined due to

Re: [PATCH v2 8/8] hw/cpu/arm_mpcore: Remove default values for GIC external IRQs

On 2/12/25 07:43, Philippe Mathieu-Daudé wrote: Implicit default values are often hard to figure out, better be explicit. Now that all boards explicitly set the number of GIC external IRQs, remove the default values (displaying an error message if it is out of range). Signed-off-by: Philippe Mat

[PATCH v3 00/19] qom: Constify class_data

Since v2: - Rework virtio_pci_types_register() - Force TypeInfo::class_data to be in .rodata Since v1: - Make XtensaConfigList::config not const (Max) - Update / test rust (Paolo) - Constify InterfaceInfo[] Following Richard's suggestion [*], make QOM class data *const*. [*] https://lore.kernel

[PATCH 5/9] target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea

Use an explicit 64-bit type for extended addresses. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 549013d25e..a1

[PATCH 2/9] target/microblaze: Split out mb_transaction_failed_internal

Use an explicit 64-bit type for the address to store in EAR. Signed-off-by: Richard Henderson --- target/microblaze/op_helper.c | 70 +-- 1 file changed, 42 insertions(+), 28 deletions(-) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c

[PATCH 3/9] target/microblaze: Implement extended address load/store out of line

Use helpers and address_space_ld/st instead of inline loads and stores. This allows us to perform operations on physical addresses wider than virtual addresses. Signed-off-by: Richard Henderson --- target/microblaze/helper.h| 16 -- target/microblaze/op_helper.c | 99 +++

[PATCH 9/9] target/microblaze: Simplify compute_ldst_addr_type{a,b}

Require TCGv_i32 and TCGv be identical, so drop the extensions. Return constants when possible instead of a mov into a temporary. Return register inputs unchanged when possible. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 26 +- 1 file changed,

[PATCH 6/9] target/microblaze: Fix printf format in mmu_translate

Use TARGET_FMT_lx to match the target_ulong type of vaddr. Signed-off-by: Richard Henderson --- target/microblaze/mmu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 2423ac6172..6152fdafd5 100644 --- a/target/microbl

Re: [PATCH v3 12/19] hw/virtio/virtio-pci: Always allocate QOM type base_name

On 2/12/25 13:32, Philippe Mathieu-Daudé wrote: Introduce 'single_generic_device' boolean for clarity. Allocate base_name on entry. Replace the g_free() call by g_autofree qualifier. Use g_strconcat() instead of g_strdup_printf(). Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci

[PATCH v3 13/19] hw/virtio/virtio-pci: Assert before registering QOM types

Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 15383570c91..ad1d164421d 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -2496,6 +24

Re: [PATCH v3 0/7] physmem: teach cpu_memory_rw_debug() to write to more memory regions

Sorry for the delayed engagement, I failed to apply the patch set from the mailing list and had to remember that David had published this change set on GitHub. Tested-by: Stefan Zabka This addresses my initial use case of being able to write to a single MMIO device. I have not set up a scena

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