Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness on the single machine using the
device.
Signed-off-by: Philippe Mathieu-D
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness on the single machine using the
device.
Signed-off-by: Philippe Mathieu-D
Make microblaze tests a bit more generic.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20250206131052.30207-14-phi...@linaro.org>
---
tests/functional/test_microblaze_s3adsp1800.py | 7 +--
tests/functional/test_microblazeel_s3adsp1800.py | 7 +--
2 file
On 12.02.25 11:24, Gerd Hoffmann wrote:
Hi,
+/* read header */
+dma_memory_read(&address_space_memory, dma,
+uv->buffer, sizeof(*mhdr),
+MEMTXATTRS_UNSPECIFIED);
Depending on DMA sounds appealing at first, but can fall apart in corner
cases.
Signed-off-by: Philippe Mathieu-Daudé
---
meson.build | 7 +++
1 file changed, 7 insertions(+)
diff --git a/meson.build b/meson.build
index 18cf9e2913b..10f4c9fd30d 100644
--- a/meson.build
+++ b/meson.build
@@ -4826,6 +4826,13 @@ summary_info += {'libdw': libdw}
if host_os == '
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness for each machine using the device.
Signed-off-by: Philippe Mathieu-Daudé
The archive used in test_microblaze_s3adsp1800.py (testing a
big-endian target) contains a big-endian kernel. Rename using
the _BE suffix.
Similarly, the archive in test_microblazeel_s3adsp1800 (testing
a little-endian target) contains a little-endian kernel. Rename
using _LE suffix.
These change
Introduce the EndianMode type and the DEFINE_PROP_ENDIAN() macros.
Endianness can be BIG, LITTLE or unspecified (default).
Signed-off-by: Philippe Mathieu-Daudé
---
qapi/common.json| 16
include/hw/qdev-properties-system.h | 7 +++
hw/core/qdev-propertie
Avoid fetching assets from www.qemu-advent-calendar.org
website, prefer fetching microblaze assets from GitLab servers.
Suggested-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_microblazeel_s3adsp1800.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
d
Commit f0ec14c78c4 ("tests/avocado: Fix console data loss") fixed
QEMUMachine's problem with console, we don't need to use the sleep()
kludges.
Suggested-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <20250206131052.30
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness on the single machine using the
device.
Signed-off-by: Philippe Mathieu-D
Have the MicroblazeMachine class being common to both
MicroblazeBigEndianMachine and MicroblazeLittleEndianMachine
classes. Move the xmaton and ballerina tests to the parent class.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20250206131052.30207-16-phi...@linaro.o
Am 12.02.2025 um 11:01 hat Paolo Bonzini geschrieben:
> On 2/11/25 22:43, Kevin Wolf wrote:
> > The existing qemu_api library can't be linked into tools because it
> > contains a few bindings for things that only exist in the system
> > emulator.
> >
> > This adds a new "system" feature to the qem
On Wed, Feb 12, 2025 at 05:39:17PM +0300, Daniil Tatianin wrote:
> This will be used in the following commits to make it possible to only
> lock memory on fault instead of right away.
>
> Signed-off-by: Daniil Tatianin
> ---
> include/system/os-posix.h | 2 +-
> include/system/os-win32.h | 3 +
On 2/11/25 22:43, Kevin Wolf wrote:
+/// A request to a block driver
+pub enum Request {
+Read { offset: u64, len: u64 },
+}
+
Maybe add flags already?
+#[allow(dead_code)]
+pub enum MappingTarget {
+/// The described blocks are unallocated. Reading from them yields zeros.
+Unmappe
On Wed, Feb 12, 2025 at 05:39:17PM +0300, Daniil Tatianin wrote:
> This will be used in the following commits to make it possible to only
> lock memory on fault instead of right away.
>
> Signed-off-by: Daniil Tatianin
> ---
> include/system/os-posix.h | 2 +-
> include/system/os-win32.h | 3 +
Am 12.02.2025 um 14:47 hat Paolo Bonzini geschrieben:
> On Wed, Feb 12, 2025 at 2:13 PM Kevin Wolf wrote:
> > Yes, we definitely need some proper bindings there. I'm already tired of
> > writing things like this:
> >
> > return -(bindings::EINVAL as std::os::raw::c_int)
> >
> > Or even:
> >
>
On 12.02.25 16:21, Peter Xu wrote:
On Mon, Feb 10, 2025 at 09:46:46AM +0100, David Hildenbrand wrote:
We want to pass another flag that will be stored in MemTxAttrs. So pass
MemTxAttrs directly.
Reviewed-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Hildenbrand
---
The 32 IRQ lines skipped are the GIC internal ones.
Use the GIC_INTERNAL definition for clarity.
No logical change.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/exynos4210.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
in
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"). Add the GIC_EXT_IRQS definition (with a comment)
to make that explicit.
Except explicitly setting a property value to its same implicit
value, the
We already have a definition to distinct GIC internal
IRQs versus external ones, use it. No logical changes.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/arm/xilinx_zynq.c | 34 --
1 file changed, 16 insertions(+), 18 deletions(-)
diff
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit 528622421eb
"hw/cpu/a15mpcore: Correct default value for num-irq").
The Caldexa Highbank board however expects
Some boards based on Cortex-A9MP / Cortex-A15MP do not explicit
the number of external GIC IRQs, using some (implicit) default value,
not always trivial to figure out. Change that by removing the default
value, requiring MPCore objects to be created with the "num-irq" set.
Since v1:
- Remove gener
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit 528622421eb
"hw/cpu/a15mpcore: Correct default value for num-irq").
The Versatile Express board however expect
Implicit default values are often hard to figure out, better
be explicit. Now that all boards explicitly set the number of
GIC external IRQs, remove the default values (displaying an
error message if it is out of range).
Signed-off-by: Philippe Mathieu-Daudé
---
hw/cpu/a15mpcore.c | 18 +
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"). Add the GIC_EXT_IRQS definition (with a comment)
to make that explicit.
Except explicitly setting a property value to its same implicit
value, the
Looking at the Zynq 7000 SoC Technical Reference Manual (UG585 v1.14)
on Appendix A: Register Details, the mpcore Interrupt Controller Type
Register (ICDICTR) has the IT_Lines_Number field read-only with value
0x2, described as:
IT_Lines_Number
b00010 = the distributor provides 96 int
On 12/2/25 16:23, Peter Xu wrote:
On Wed, Feb 12, 2025 at 05:39:17PM +0300, Daniil Tatianin wrote:
This will be used in the following commits to make it possible to only
lock memory on fault instead of right away.
Signed-off-by: Daniil Tatianin
---
include/system/os-posix.h | 2 +-
include
On 2/12/2025 09:06, Eugenio Perez Martin wrote:
-i = cpu_to_le16(svq->desc_next[i]);
+i = le16_to_cpu(svq->desc_next[i]);
Both svq->desc_next and "i" are in QEMU. We can skip the conversion
and assign directly.
Are you saying that desc_next[] should be in "CPU" and not LE form
On Wed, Feb 12, 2025 at 03:30:21PM +, Daniel P. Berrangé wrote:
> > diff --git a/include/system/os-win32.h b/include/system/os-win32.h
> > index b82a5d3ad9..cd61d69e10 100644
> > --- a/include/system/os-win32.h
> > +++ b/include/system/os-win32.h
> > @@ -123,8 +123,9 @@ static inline bool is_da
The MMIO region size required to support virtualized environments with
large PCI BAR regions can exceed the hardcoded limit configured in QEMU.
For example, a VM with multiple NVIDIA Grace-Hopper GPUs passed through
requires more MMIO memory than the amount provided by VIRT_HIGH_PCIE_MMIO
(currentl
On Tue, Feb 11, 2025 at 5:20 PM Konstantin Shkolnyy wrote:
>
> VDPA didn't work on a big-endian machine due to missing/incorrect
> CPU<->LE data format conversions.
>
Thank you very much for this!
> Signed-off-by: Konstantin Shkolnyy
> ---
> hw/virtio/vhost-shadow-virtqueue.c | 16 +---
On 1/30/25 11:08, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Since it's important to finish loading device state transferred via the
main migration channel (via save_live_iterate SaveVMHandler) before
starting loading the data asynchronously transferred via multifd the thread
doing
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250210133134.90879-7-phi...@linaro.org>
---
hw/isa/vt82c686.c | 2 +-
hw/rtc/m48t59-isa.c | 2 +-
hw/rtc/m48t59.c | 2 +-
hw/sensor/tmp421.c| 2 +-
hw/usb/hcd-ehci-pci.c | 2 +-
hw/usb/hcd-uhci.c
The following changes since commit f9edf32ea2e18a56de5d92f57e9d10565c822367:
Merge tag 'pull-request-2025-02-11' of https://gitlab.com/thuth/qemu into
staging (2025-02-11 13:27:32 -0500)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/hw-misc-202
When the %data argument is not modified, we can declare it const.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250210133134.90879-8-phi...@linaro.org>
---
hw/sd/sdhci-internal.h | 2 +-
hw/sd/sdhci.c| 2 +-
hw/sensor/emc141x.c | 2 +-
hw
On Wed, Feb 12, 2025 at 4:37 PM Konstantin Shkolnyy wrote:
>
> On 2/12/2025 09:06, Eugenio Perez Martin wrote:
> >> -i = cpu_to_le16(svq->desc_next[i]);
> >> +i = le16_to_cpu(svq->desc_next[i]);
> >
> > Both svq->desc_next and "i" are in QEMU. We can skip the conversion
> > and ass
On Fri, Dec 06, 2024 at 11:45:24AM +, Daniel P. Berrangé wrote:
> If the 'stap' binary is missing in $PATH, a huge trace is thrown
>
> $ qemu-trace-stap list /usr/bin/qemu-system-x86_64
> Traceback (most recent call last):
> File "/usr/bin/qemu-trace-stap", line 169, in
> main()
> F
On 2/12/25 16:48, Cédric Le Goater wrote:
On 1/30/25 11:08, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Since it's important to finish loading device state transferred via the
main migration channel (via save_live_iterate SaveVMHandler) before
starting loading the data asynchronousl
On 2/12/25 6:30 PM, Daniel P. Berrangé wrote:
On Wed, Feb 12, 2025 at 05:39:17PM +0300, Daniil Tatianin wrote:
This will be used in the following commits to make it possible to only
lock memory on fault instead of right away.
Signed-off-by: Daniil Tatianin
---
include/system/os-posix.h | 2
On 1/30/25 11:08, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Load device config received via multifd using the existing machinery
behind vfio_load_device_config_state().
Also, make sure to process the relevant main migration channel flags.
Signed-off-by: Maciej S. Szmigiero
---
On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote:
On 12/2/25 14:53, Philippe Mathieu-Daudé wrote:
On 12/2/25 13:56, BALATON Zoltan wrote:
On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote:
On 12/2/25 12:37, Thomas Huth wrote:
On 12/02/2025 12.24, Philippe Mathieu-Daudé wrote:
Introduce the
The design of INTC controllers has significantly changed in AST2700 A1.
There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged e
Added support for multiple output pins in the INTC controller to
accommodate the AST2700 A1.
Introduced "num_outpins" to represent the number of output pins. Updated the
IRQ handling logic to initialize and connect output pins separately from input
pins. Modified the "aspeed_soc_ast2700_realize" f
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.c | 8
hw/arm/aspeed_ast27x0.c | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/
This method simplifies the process of fetching and extracting assets from the
Aspeed GitHub repository.
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tes
Added a new method `start_ast2700_test` to the `AST2x00MachineSDK` class and
this method centralizes the logic for starting the AST2700 test, making it
reusable for different test cases.
Modified the hwmon path to use a wildcard to handle different SDK versions:
"cat /sys/bus/i2c/devices/1-004d/hw
Currently, these trace events only refer to INTC. To simplify the INTC model,
both INTC(CPU Die) and INTCIO(IO Die) will share the same helper functions.
However, it is difficult to recognize whether these trace events are comes from
INTC or INTCIO. To make these trace events more readable, adds o
Refactors the INTC to distinguish between input and output pin indices,
improving interrupt handling clarity and accuracy.
Updated the functions to handle both input and output pin indices.
Added detailed logging for input and output pin indices in trace events.
These changes ensure that the INTC
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin
Reviewed-by: Andrew Jeffery
---
hw/misc/aspeed_hace.c | 20
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
Add AST2700 INTC design guidance and its block diagram.
Signed-off-by: Jamin Lin
---
docs/specs/aspeed-intc.rst | 136 +
docs/specs/index.rst | 1 +
2 files changed, 137 insertions(+)
create mode 100644 docs/specs/aspeed-intc.rst
diff --git a/docs/sp
To improve readability, sort the IRQ table by IRQ number.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 50 -
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 6e3375f5d3..4862b
The HACE controller between AST2600 and AST2700 are almost identical.
The HACE controller registers base address starts at 0x1207_ and
its alarm interrupt is connected to GICINT4.
Signed-off-by: Jamin Lin
Reviewed-by: Andrew Jeffery
---
hw/arm/aspeed_ast27x0.c | 15 +++
1 file c
Currently, it does not support the CRYPT command. Instead, it only sends an
interrupt to notify the firmware that the crypt command has completed.
It is a temporary workaround to resolve the boot issue in the Crypto Manager
Self Test.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 12 +
Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0.
These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197.
Updates the interrupt mapping to include support for AST2700 A1 by extending
the existing mappings to the new GIC range.
Signed-off-by: Jamin Lin
---
hw/arm/as
According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB
(0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.
Introduced a new c
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC (CPU Die).
To support the INTCIO (IO Die) model, introduces
The behavior of the enable and status registers is almost identical between
INTC(CPU Die) and INTCIO(IO Die). To reduce duplicated code, adds
"aspeed_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_intc_status_handler" functions to handle status
register write be
This update introduces support for handling multi-output IRQs in the AST2700
interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps
1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a
specific IRQ.
Implemented "aspeed_intc_set_irq_handler_multi_out
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index e3f7df2e86..18b85081c7 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/m
v1:
1. Refactor INTC model to support both INTC0 and INTC1.
2. Support AST2700 A1.
3. Create ast2700a0-evb machine.
v2:
To streamline the review process, split the following patch series into
three parts.
https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jam
The behavior of the INTC set IRQ is almost identical between INTC and INTCIO.
To reduce duplicated code, introduce the "aspeed_intc_set_irq_handler" function
to handle both INTC and INTCIO IRQ behavior.
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c | 62 -
To support AST2700 A1, some registers of the INTC(CPU Die) support one input
pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC
controller code for better clarity and consistency in naming conventions.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 2 +-
h
According to the design of the AST2600, it has a Silicon Revision ID Register,
specifically SCU004 and SCU014, to set the Revision ID for the AST2600.
For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303.
In the "aspeed_ast2600_scu_reset" function, the hardcoded value
"AS
Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV to
identify the A1 silicon revisions.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_scu.c | 2 ++
include/hw/misc/aspeed_scu.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/a
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index aa817afa4e..788dd29a6d 100755
--- a/tests/functional/test_aarch64
On 2/12/25 20:12, Michael Tokarev wrote:
11.02.2025 17:33, Cédric Le Goater wrote:
From: Zhenzhong Duan
When iommufd_cdev_ram_block_discard_disable() fails for whatever reason,
errp should be set or else SIGSEV is triggered in vfio_realize() when
error_prepend() is called.
By this chance, use
13.02.2025 09:32, Cédric Le Goater wrote:
..
This seems to be a qemu-stable material (for 9.2).
Please let me know if it is not.
For 9.0 and above. It applies cleanly.
Yup, - I thought it wont be clear.
9.0 & 9.1 are end-of-line at this point, only 9.2 is relevant now.
Also 7.2 and 8.2 are s
On Wed, Feb 12, 2025 at 7:11 PM Philippe Mathieu-Daudé
wrote:
>
> On 12/2/25 17:49, Konstantin Shkolnyy wrote:
> > VDPA didn't work on a big-endian machine due to missing/incorrect
> > CPU<->LE data format conversions.
> >
> > Signed-off-by: Konstantin Shkolnyy
> > ---
> > Changes in v2: Change d
On Wed, Feb 12, 2025 at 5:49 PM Konstantin Shkolnyy wrote:
>
> VDPA didn't work on a big-endian machine due to missing/incorrect
> CPU<->LE data format conversions.
>
Fixes: 10857ec0ad ("vhost: Add VhostShadowVirtqueue")
> Signed-off-by: Konstantin Shkolnyy
Acked-by: Eugenio Pérez
Thanks!
>
On 12/02/2025 23.34, BALATON Zoltan wrote:
On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote:
On 12/2/25 17:23, BALATON Zoltan wrote:
On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote:
On 12/2/25 14:53, Philippe Mathieu-Daudé wrote:
On 12/2/25 13:56, BALATON Zoltan wrote:
On Wed, 12 Feb 2025
On Tue, Feb 11, 2025 at 09:26:55AM +, Jonathan Cameron wrote:
> On Tue, 11 Feb 2025 10:24:13 +0800
> Yuquan Wang wrote:
>
> > The previous default value of sn is UI64_NULL which would cause the
> > cookie of nd_interleave_set be '0' and the "invalid interleave-set
> > -cookie" failure in labe
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index 788dd29a6d..ad2774be15 100755
--- a/tests/functional/test_aarch
Introduce a new ast2700 INTCIO class to support AST2700 INTCIO.
Added new register definitions for INTCIO, including enable and status
registers for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTCIO, supporting six input pins and six
output pins, aligning with the newly def
The memory map for AST2700 A1 remains compatible with AST2700 A0. However, the
IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging
from 192 to 201. Add a new IRQ map table for AST2700 A1.
Add "aspeed_soc_ast2700a1_class_init" to initialize the AST2700 A1 SoC.
Introduce "asp
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index ad2774be15..2afc50265a 100755
--- a/tests/functional/test_aarch64_aspeed.py
+++
The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ
pin to 10 output IRQ pins. The pin nu
As raised by Richard Henderson, these warnings are displayed in user
only as well. Disable them for CONFIG_USER_ONLY.
Signed-off-by: Clément Léger
---
target/riscv/tcg/tcg-cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index
On 2025/02/10 1:56, Dmitry Osipenko wrote:
From: Alex Bennée
This attempts to tidy up the VirtIO GPU documentation to make the list
of requirements clearer. There are still a lot of moving parts and the
distros have some catching up to do before this is all handled
automatically.
Signed-off-by
On 2025/02/10 6:03, Dmitry Osipenko wrote:
On 2/6/25 08:41, Akihiko Odaki wrote:
On 2025/02/06 2:40, Dmitry Osipenko wrote:
On 2/3/25 08:31, Akihiko Odaki wrote:
...
Requirements don't vary much. For example virglrenderer minigbm support
is mandatory for crosvm, while for QEMU it's not.
Is t
On 2/11/25 22:43, Kevin Wolf wrote:
+/// Implementing `SizedIoBuffer` provides an implementation for [`IoBuffer`]
without having to
+/// implement any functions manually.
+///
+/// # Safety
+///
+/// Types implementing `SizedIoBuffer` guarantee that the whole object can be
accessed as an I/O
+/
On 2/12/25 16:29, Kevin Wolf wrote:
Am 12.02.2025 um 11:01 hat Paolo Bonzini geschrieben:
On 2/11/25 22:43, Kevin Wolf wrote:
The existing qemu_api library can't be linked into tools because it
contains a few bindings for things that only exist in the system
emulator.
This adds a new "system"
Am 12.02.2025 um 17:48 hat Paolo Bonzini geschrieben:
> On 2/11/25 22:43, Kevin Wolf wrote:
> > +/// Implementing `SizedIoBuffer` provides an implementation for
> > [`IoBuffer`] without having to
> > +/// implement any functions manually.
> > +///
> > +/// # Safety
> > +///
> > +/// Types implemen
On 2/12/2025 08:52, Philippe Mathieu-Daudé wrote:
On 11/2/25 17:19, Konstantin Shkolnyy wrote:
Add .set_vnet_le() function that always returns success, assuming that
vDPA h/w always implements LE data format. Otherwise, QEMU disables
vDPA and
outputs the message:
"backend does not support LE v
On 2/12/25 07:43, Philippe Mathieu-Daudé wrote:
Looking at the Zynq 7000 SoC Technical Reference Manual (UG585 v1.14)
on Appendix A: Register Details, the mpcore Interrupt Controller Type
Register (ICDICTR) has the IT_Lines_Number field read-only with value
0x2, described as:
IT_Lines_Number
On 2/12/25 07:43, Philippe Mathieu-Daudé wrote:
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit 528622421eb
"hw/cpu/a15mpcore: Correct default value for num
On 12/2/25 17:49, Konstantin Shkolnyy wrote:
VDPA didn't work on a big-endian machine due to missing/incorrect
CPU<->LE data format conversions.
Signed-off-by: Konstantin Shkolnyy
---
Changes in v2: Change desc_next[] from LE format to "CPU".
hw/virtio/vhost-shadow-virtqueue.c | 18 +
On 12/2/25 17:23, BALATON Zoltan wrote:
On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote:
On 12/2/25 14:53, Philippe Mathieu-Daudé wrote:
On 12/2/25 13:56, BALATON Zoltan wrote:
On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote:
On 12/2/25 12:37, Thomas Huth wrote:
On 12/02/2025 12.24, Phil
Il mer 12 feb 2025, 18:32 Kevin Wolf ha scritto:
> > > +mut buf: MaybeUninit,
> >
> > I think Rust doesn't guarantee no copies here, so maybe this could be
>
> Do you think that in practice the compiler won't optimise the copy away?
>
It's possiblr that it does not, because it has to bui
On 2/12/25 07:43, Philippe Mathieu-Daudé wrote:
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit 528622421eb
"hw/cpu/a15mpcore: Correct default value for num
On 2/11/25 23:22, Philippe Mathieu-Daudé wrote:
On 5/2/25 05:03, Richard Henderson wrote:
The declarations use vaddr for size.
Which seems dubious, since TARGET_PAGE_SIZE is int IIUC.
This parameter must handle guest huge pages. Most often this is 2MiB or 1GiB, which do
fit in "int", but l
On 2/12/25 07:43, Philippe Mathieu-Daudé wrote:
We already have a definition to distinct GIC internal
IRQs versus external ones, use it. No logical changes.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/arm/xilinx_zynq.c | 34 --
1 fil
On 2/12/25 7:42 PM, Peter Xu wrote:
On Wed, Feb 12, 2025 at 07:17:45PM +0300, Daniil Tatianin wrote:
-static inline int os_mlock(void)
+static inline int os_mlock(bool on_fault)
{
+(void)on_fault;
Is this really needed ? Our compiler flags don't enable warnings
about unused variables.
On 2/12/25 16:13, Kevin Wolf wrote:
Or if you have to define the constants anyway - you currently do this
only for Windows, but for into_negative_errno() you might need it on
Linux, too - and it wouldn't be a problem for the constants to be
signed (that they are unsigned is the main reason why it
On 2/12/25 07:43, Philippe Mathieu-Daudé wrote:
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"). Add the GIC_EXT_IRQS definition (with a comment)
to make that explicit.
Except explicitly settin
On Wed, Feb 12, 2025 at 12:56:46PM -0500, Peter Xu wrote:
> On Wed, Feb 12, 2025 at 05:48:46PM +, Daniel P. Berrangé wrote:
> > On Wed, Feb 12, 2025 at 12:38:23PM -0500, Peter Xu wrote:
> > > From: Daniil Tatianin
> > >
> > > This will be used in the following commits to make it possible to o
Am 12.02.2025 um 18:16 hat Paolo Bonzini geschrieben:
> On 2/12/25 16:13, Kevin Wolf wrote:
> > Or if you have to define the constants anyway - you currently do this
> > only for Windows, but for into_negative_errno() you might need it on
> > Linux, too - and it wouldn't be a problem for the consta
On 2/12/2025 12:07, Philippe Mathieu-Daudé wrote:
On 12/2/25 18:24, Konstantin Shkolnyy wrote:
On 2/12/2025 08:52, Philippe Mathieu-Daudé wrote:
On 11/2/25 17:19, Konstantin Shkolnyy wrote:
Add .set_vnet_le() function that always returns success, assuming that
vDPA h/w always implements LE dat
Hello members of QEMU dev,
My name is Gil, I'm an architect at Zerto (now part of HPE).
Currently Zerto support block device replication, with 5 seconds RPO and RTO of
minutes, for the VmWare and HyperV platforms.
We would like to support also QEMU based hypervisors. For that, we need to
creat
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
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