[PATCH 16/22] target/riscv: generalize custom CSR functionality

Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h| 13 +++-- target/riscv/cpu.c| 23 ++- target/riscv/th_csr.c | 21 +++-- 3 files changed, 36 insertions(+), 21 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 66ce72f7d

[PATCH 11/22] target/riscv: convert dynamic CPU models to RISCVCPUDef

Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 110 + 1 file changed, 30 insertions(+), 80 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8fa05912698..ce439f1159d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines

On Thu, Feb 06, 2025 at 07:24:55PM +0100, Philippe Mathieu-Daudé wrote: > +Michal > > On 6/2/25 19:06, Daniel P. Berrangé wrote: > > On Thu, Feb 06, 2025 at 06:49:38PM +0100, Philippe Mathieu-Daudé wrote: > > > On 6/2/25 18:12, Daniel P. Berrangé wrote: > > > > On Thu, Feb 06, 2025 at 04:04:20PM +

[PATCH 01/22] target/riscv: remove unused macro DEFINE_CPU

Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 9 - 1 file changed, 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3d4bd157d2c..ed9da692030 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3051,15 +3051,6 @@ void riscv_isa_write_fdt(RISCVCPU

[PATCH 5/7] hw/riscv/iommu: Reduce needs for target-specific code

Use the qemu_target_page_size() runtime function instead of the TARGET_PAGE_SIZE definition, remove unnecessary "exec/exec-all.h" header. Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/riscv-iommu-pci.c | 5 +++-- hw/riscv/riscv-iommu-sys.c | 1 - hw/riscv/riscv-iommu.c | 1 + 3 files ch

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