"Kim, Dongwon" writes:
> Hi,
>
> The commit below could change the timing of drawing by making the drawing
> done at refresh cycle instead of via drawing event. So it looks like either
> dmabuf
> or client's framebuffer is being written and read at the same time. Hey, can
> you
> describe how t
On Mon, Feb 03, 2025 at 01:25:29PM -0500, Stefan Hajnoczi wrote:
> BLOCK_OP_TYPE_DATAPLANE prevents BlockDriverState from being used by
> virtio-blk/virtio-scsi with IOThread. Commit b112a65c52aa ("block:
> declare blockjobs and dataplane friends!") eliminated the main reason
> for this blocker in
On 11/26/24 5:56 AM, Jean-Philippe Brucker wrote:
Initialize the IPA state of RAM. Collect the images copied into guest
RAM into a sorted list, and issue POPULATE_REALM KVM ioctls once we've
created the Realm Descriptor. The images are part of the Realm Initial
Measurement.
Signed-off-by: Jean-P
On 11/26/24 5:56 AM, Jean-Philippe Brucker wrote:
Add a function to register a notifier, that is invoked after a ROM gets
loaded into guest memory.
It will be used by Arm confidential guest support, in order to register
all blobs loaded into memory with KVM, so that their content is moved
into R
On 3/2/25 10:10, Alex Bennée wrote:
Peter Maydell writes:
On Wed, 29 Jan 2025 at 06:23, Thomas Huth wrote:
So unless someone complains immediately with a good reason, I'm also in
favor of marking it as deprecated now. If then someone complains during the
deprecation period, we still can reco
On 3/2/25 15:50, Daniel P. Berrangé wrote:
On Mon, Feb 03, 2025 at 02:45:06PM +, Peter Maydell wrote:
On Mon, 3 Feb 2025 at 14:33, Daniel P. Berrangé wrote:
On Mon, Feb 03, 2025 at 02:29:49PM +, Alex Bennée wrote:
Peter Maydell writes:
On Sat, 1 Feb 2025 at 12:57, BALATON Zoltan
From: Li Zhijian
Simply pass the errp to its callee which will set errp if needed, to
enhance error reporting for CXL Type 3 device initialization by setting
the errp when realization functions fail.
Previously, failing to set `errp` could result in errors being overlooked,
causing the system to
From: Yao Xingtao
Since the kernel does not check the interleave capability, a
3-way, 6-way, 12-way or 16-way region can be create normally.
Applications can access the memory of 16-way region normally because
qemu can convert hpa to dpa correctly for the power of 2 interleave
ways, after kernel
Steve Sistare writes:
> Define a vmstate priority that is lower than the default, so its handlers
> run after all default priority handlers. Since 0 is no longer the default
> priority, translate an uninitialized priority of 0 to MIG_PRI_DEFAULT.
>
> CPR for vfio will use this to install handler
From: Li Zhijian
Address a memory leak issue by ensuring `regs->special_ops` is freed when
`msix_init_exclusive_bar()` encounters an error during CXL Type3 device
initialization.
Additionally, this patch renames err_address_space_free to err_msix_uninit
for better clarity and logical flow
Signe
From: Li Zhijian
msix_uninit_exclusive_bar() should be paired with msix_init_exclusive_bar()
Ensure proper resource cleanup by adding the missing
`msix_uninit_exclusive_bar()` call for the Type3 CXL device.
Signed-off-by: Li Zhijian
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 2
First set of CXL updates for the 10.0 cycle.
- Mixture of cleanup and hardening against a repeat of recent MSI-X
numbering bug.
- Expanded interleave support (been on my tree a long time)
Whilst I think these are in a good state, review always welcome.
Li Zhijian (4):
hw/cxl: Introduce CXL_T3
From: Li Zhijian
Introduce the `CXL_T3_MSIX_VECTOR` enumeration to specify MSIX vector
assignments specific to the Type 3 (T3) CXL device.
The primary goal of this change is to encapsulate the MSIX vector uses
that are unique to the T3 device within an enumeration, improving code
readability and
On Fri, Jan 31, 2025 at 10:50:46AM +0100, Kevin Wolf wrote:
> Currently, block jobs can't handle inactive images correctly. Incoming
> write requests would run into assertion failures. Make sure that we
> return an error when creating an export can't activate the image.
>
> Signed-off-by: Kevin Wo
QEMU supports GICv3 Non-maskable Interrupt, adds to support Non-maskable
Interrupt for AST2700.
Reference:
https://github.com/qemu/qemu/commit/b36a32ead
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/
On 2/3/25 10:30, Philippe Mathieu-Daudé wrote:
On 3/2/25 04:18, Richard Henderson wrote:
Define TARGET_LONG_BITS in each target's configure fragment.
Do this without removing the define in target/*/cpu-param.h
so that errors are caught like so:
In file included from .../src/include/exec/cpu-def
On Fri, Jan 31, 2025 at 10:50:49AM +0100, Kevin Wolf wrote:
> The open-coded form of this filter has been copied into enough tests
> that it's better to move it into iotests.py.
>
> Signed-off-by: Kevin Wolf
> ---
> tests/qemu-iotests/iotests.py | 4
> tests/qemu-iotests/041
On Fri, Jan 31, 2025 at 10:50:50AM +0100, Kevin Wolf wrote:
> Test that it's possible to migrate a VM that uses an image on shared
> storage through qemu-storage-daemon.
>
> Signed-off-by: Kevin Wolf
> ---
> tests/qemu-iotests/tests/qsd-migrate | 132 +++
> tests/qemu-iot
On Fri, Jan 31, 2025 at 10:50:48AM +0100, Kevin Wolf wrote:
> In order to support running an NBD export on inactive nodes, we must
> make sure to return errors for any operations that aren't allowed on
> inactive nodes. Reads are the only operation we know we need for
> inactive images, so to err o
On 3.02.2025 20:58, Peter Xu wrote:
On Mon, Feb 03, 2025 at 02:57:36PM +0100, Maciej S. Szmigiero wrote:
On 2.02.2025 13:45, Dr. David Alan Gilbert wrote:
* Maciej S. Szmigiero (m...@maciej.szmigiero.name) wrote:
On 2.02.2025 03:06, Dr. David Alan Gilbert wrote:
* Maciej S. Szmigiero (m...@ma
Except we alter the device tree blob, the 4B
is just another raspi model.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi.c | 114 -
hw/arm/raspi4b.c | 136 -
hw/arm/meson.build | 2 +-
3 files changed
Full rewrite of v1 [1], addressing Zoltan & Peter suggestion.
Introduce a generic 'raspi' machine, which takes a 'model'
and 'revision' properties, and any memory size. The 'board_rev'
register is filled appropriately.
Before, merge raspi4b.c within raspi.c (more is planned here
with the MPCore r
The generic 'raspi' machine takes a 'model' argument and
create the machine associated with the model, with the
RAM size requested (or default to the minimum of 256MB
if not precised).
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2797
Signed-off-by: Philippe Mathieu-Daudé
---
include/
Raspberry Pi 'B' models have an ethernet chipset (the LAN9512).
Since we don't yet model it, add a /* TODO */ comment.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 1a6a1f8ff22..6
Merge Raspi4bMachineState within RaspiMachineState by
using an unnamed union.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi.c | 21 +++--
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 3fa382d62ce..ef94d57dab5 100644
Expand the current type2model array to include the processor id.
Since the BCM2838 is indistinctly used as BCM2711 (within the
Linux community), add it as alias in RaspiProcessorId.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi.c | 33 +++--
1 file changed,
All the following models can be created (with different RAM size):
$ qemu-system-aarch64 -M raspi
qemu-system-aarch64: Missing model, try -M raspi,model=help
$ qemu-system-aarch64 -M raspi,model=help
Available models (processor):
- A (BCM2835)
- B (BCM2835)
- A+
Add a property to specify the board revision. This allows to
create a Raspberry Pi 2B with BCM2836 SoC (rev 1.0 and 1.1)
or BCM2837 (rev 1.2 up to 1.5).
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi.c | 39 +++
1 file changed, 39 insertions(+)
diff -
We shouldn't access a QOM parent object directly.
Use the appropriate type-cast macro.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi.c | 2 +-
hw/arm/raspi4b.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index a7a662f40db..508
Add the 'max_ramsize' field to the soc_property[] array,
corresponding to the maximum DRAM size a SoC can map.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index
Since callers already have reference to the RaspiBaseMachineClass,
directly pass 'board_rev' as argument to raspi_base_machine_init().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/raspi_platform.h | 2 +-
hw/arm/raspi.c | 8 +++-
2 files changed, 4 insertions(+),
Allow to create the following machines:
- Zero2W
- 400
- CM4 and CM4S
Fill the arrays with the BCM2712-based machines (raspi5),
but since we don't model the SoC, these machines can't
be created (and aren't listed in the 'help' output).
List taken from:
https://github.com/raspberrypi/docume
All previous raspi machines can be created using the
generic machine. Deprecate the old names to maintain
a single one. Update the tests.
Signed-off-by: Philippe Mathieu-Daudé
---
QOM HMP introspection test fails because without the 'model'
argument set, no machine is created...
$ qemu-system-
Jonathan,
> On Feb 4, 2025, at 2:30, Jonathan Cameron wrote:
>
> Add a single complex case for aarch64 virt machine.
> Given existing much more comprehensive tests for x86 cover the
> common functionality, a single test should be enough to verify
> that the aarch64 part continue to work.
>
> Si
On 11/26/24 5:56 AM, Jean-Philippe Brucker wrote:
The target code calls kvm_arm_vcpu_init() to mark the vCPU as part of a
Realm. For a Realm vCPU, only x0-x7 can be set at runtime. Before boot,
the PC can also be set, and is ignored at runtime. KVM also accepts a
few system register changes durin
On Fri, Jan 31, 2025 at 10:50:47AM +0100, Kevin Wolf wrote:
> Add an option in BlockExportOptions to allow creating an export on an
> inactive node without activating the node. This mode needs to be
> explicitly supported by the export type (so that it doesn't perform any
> operations that are forb
On Mon, Feb 03, 2025 at 02:57:36PM +0100, Maciej S. Szmigiero wrote:
> On 2.02.2025 13:45, Dr. David Alan Gilbert wrote:
> > * Maciej S. Szmigiero (m...@maciej.szmigiero.name) wrote:
> > > On 2.02.2025 03:06, Dr. David Alan Gilbert wrote:
> > > > * Maciej S. Szmigiero (m...@maciej.szmigiero.name) w
On Thu, Jan 30, 2025 at 11:08:34AM +0100, Maciej S. Szmigiero wrote:
> From: "Maciej S. Szmigiero"
>
> Add a basic support for receiving device state via multifd channels -
> channels that are shared with RAM transfers.
>
> Depending whether MULTIFD_FLAG_DEVICE_STATE flag is present or not in th
Hi Philippe,
> From: Philippe Mathieu-Daudé
> Sent: Tuesday, February 4, 2025 12:41 AM
> To: Jamin Lin ; Cédric Le Goater ;
> Peter Maydell ; Andrew Jeffery
> ; Joel Stanley ; Alistair
> Francis ; Cleber Rosa ; Wainer
> dos Santos Moschetta ; Beraldo Leal
> ; open list:ASPEED BMCs ; open
> list:A
On 3.02.2025 21:36, Peter Xu wrote:
On Mon, Feb 03, 2025 at 09:15:52PM +0100, Maciej S. Szmigiero wrote:
On 3.02.2025 20:58, Peter Xu wrote:
On Mon, Feb 03, 2025 at 02:57:36PM +0100, Maciej S. Szmigiero wrote:
On 2.02.2025 13:45, Dr. David Alan Gilbert wrote:
* Maciej S. Szmigiero (m...@macie
On 3.02.2025 21:20, Peter Xu wrote:
On Mon, Feb 03, 2025 at 07:53:00PM +0100, Maciej S. Szmigiero wrote:
On 3.02.2025 19:20, Peter Xu wrote:
On Thu, Jan 30, 2025 at 11:08:29AM +0100, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Multifd send channels are terminated by calling
qio_ch
On Thu, Jan 30, 2025 at 11:08:37AM +0100, Maciej S. Szmigiero wrote:
> From: "Maciej S. Szmigiero"
>
> A new function multifd_queue_device_state() is provided for device to queue
> its state for transmission via a multifd channel.
>
> Signed-off-by: Maciej S. Szmigiero
Reviewed-by: Peter Xu
On 3.02.2025 22:13, Daniel P. Berrangé wrote:
On Thu, Jan 30, 2025 at 11:08:31AM +0100, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Automatic memory management helps avoid memory safety issues.
Signed-off-by: Maciej S. Szmigiero
---
include/qapi/error.h | 2 ++
1 file changed,
On Mon, Feb 03, 2025 at 07:53:00PM +0100, Maciej S. Szmigiero wrote:
> On 3.02.2025 19:20, Peter Xu wrote:
> > On Thu, Jan 30, 2025 at 11:08:29AM +0100, Maciej S. Szmigiero wrote:
> > > From: "Maciej S. Szmigiero"
> > >
> > > Multifd send channels are terminated by calling
> > > qio_channel_shutd
Am 03.02.2025 um 20:35 hat Eric Blake geschrieben:
> On Fri, Jan 31, 2025 at 10:50:50AM +0100, Kevin Wolf wrote:
> > Test that it's possible to migrate a VM that uses an image on shared
> > storage through qemu-storage-daemon.
> >
> > Signed-off-by: Kevin Wolf
> > ---
> > tests/qemu-iotests/test
On Thu, Jan 30, 2025 at 11:08:31AM +0100, Maciej S. Szmigiero wrote:
> From: "Maciej S. Szmigiero"
>
> Automatic memory management helps avoid memory safety issues.
>
> Signed-off-by: Maciej S. Szmigiero
> ---
> include/qapi/error.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/i
On 2/3/2025 12:48 PM, Cédric Le Goater wrote:
On 1/29/25 15:43, Steve Sistare wrote:
At vfio creation time, save the value of vfio container, group, and device
descriptors in CPR state. On qemu restart, vfio_realize() finds and uses
the saved descriptors, and remembers the reused status for sub
On 2/3/2025 12:01 PM, Cédric Le Goater wrote:
On 1/29/25 15:43, Steve Sistare wrote:
Register a legacy container for cpr-transfer. Add a blocker if the kernel
does not support VFIO_UPDATE_VADDR or VFIO_UNMAP_ALL.
This is mostly boiler plate. The fields to to saved and restored are added
in su
Reviving a patch that has been sitting in my tree for a while. It's
mostly useful for low-level integration testing (such as debugging
libnbd as an NBD client).
Eric Blake (2):
qemu-nbd: Allow users to adjust handshake limit
nbd/server: Allow users to adjust handshake limit in QMP
docs/tool
Although defaulting the handshake limit to 10 seconds was a nice QoI
change to weed out intentionally slow clients, it can interfere with
integration testing done with manual NBD_OPT commands over 'nbdsh
--opt-mode'. Expose a QMP knob 'handshake-max-secs' to allow the user
to alter the timeout awa
On 2/3/2025 1:25 PM, Cédric Le Goater wrote:
On 1/29/25 15:43, Steve Sistare wrote:
Preserve DMA mappings during cpr-transfer.
In the container pre_save handler, suspend the use of virtual addresses
in DMA mappings with VFIO_DMA_UNMAP_FLAG_VADDR, because guest RAM will
be remapped at a differen
Although defaulting the handshake limit to 10 seconds was a nice QoI
change to weed out intentionally slow clients, it can interfere with
integration testing done with manual NBD_OPT commands over 'nbdsh
--opt-mode'. Expose a command line option to allow the user to alter
the timeout away from the
+Xen maintainers
On Mon, 3 Feb 2025, Richard Henderson wrote:
> On 2/3/25 04:54, Paolo Bonzini wrote:
> > On 2/3/25 04:18, Richard Henderson wrote:
> > > v1: 20250128004254.33442-1-richard.hender...@linaro.org
> > >
> > > For v2, immediately disable 64-on-32 TCG.
> > >
> > > I *suspect* that we
Am 2. Februar 2025 17:09:06 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 1/2/25 16:28, Bernhard Beschow wrote:
>>
>>
>> Am 30. Januar 2025 23:05:53 UTC schrieb "Philippe Mathieu-Daudé"
>> :
>>> Cc'ing AMD folks
>>>
>>> Hi Bernhard,
>>>
>>> TL;DR; can't you use the PCF8574 which is a more com
On Mon, 3 Feb 2025, Philippe Mathieu-Daudé wrote:
On 3/2/25 15:50, Daniel P. Berrangé wrote:
On Mon, Feb 03, 2025 at 02:45:06PM +, Peter Maydell wrote:
On Mon, 3 Feb 2025 at 14:33, Daniel P. Berrangé
wrote:
On Mon, Feb 03, 2025 at 02:29:49PM +, Alex Bennée wrote:
Peter Maydell writ
On 2/3/25 09:38, Thomas Huth wrote:
On 03/02/2025 17.43, Richard Henderson wrote:
On 2/3/25 02:22, Thomas Huth wrote:
On 03/02/2025 04.18, Richard Henderson wrote:
Add tcg_allowed, qmp_x_query_jit, qmp_x_query_opcount.
These are referenced when CONFIG_TCG is enabled globally,
but not for a spe
On Mon, Feb 03, 2025 at 11:18:11PM +0100, Maciej S. Szmigiero wrote:
> On 3.02.2025 22:27, Peter Xu wrote:
> > On Thu, Jan 30, 2025 at 11:08:34AM +0100, Maciej S. Szmigiero wrote:
> > > From: "Maciej S. Szmigiero"
> > >
> > > Add a basic support for receiving device state via multifd channels -
>
On Mon, Feb 03, 2025 at 10:41:32PM +0100, Maciej S. Szmigiero wrote:
> On 3.02.2025 21:20, Peter Xu wrote:
> > On Mon, Feb 03, 2025 at 07:53:00PM +0100, Maciej S. Szmigiero wrote:
> > > On 3.02.2025 19:20, Peter Xu wrote:
> > > > On Thu, Jan 30, 2025 at 11:08:29AM +0100, Maciej S. Szmigiero wrote:
Am 21. Januar 2025 02:52:58 UTC schrieb BALATON Zoltan :
>On Mon, 20 Jan 2025, Bernhard Beschow wrote:
>> The USDHC emulation allows for running real-world images such as those
>> generated
>> by Buildroot. Convert the board documentation accordingly instead of running
>> a
>> Linux kernel wit
On Mon, Feb 03, 2025 at 10:41:43PM +0100, Maciej S. Szmigiero wrote:
> On 3.02.2025 21:36, Peter Xu wrote:
> > On Mon, Feb 03, 2025 at 09:15:52PM +0100, Maciej S. Szmigiero wrote:
> > > On 3.02.2025 20:58, Peter Xu wrote:
> > > > On Mon, Feb 03, 2025 at 02:57:36PM +0100, Maciej S. Szmigiero wrote:
Am 28. Januar 2025 14:33:27 UTC schrieb Gustavo Romero
:
>Hi,
>
>On 1/20/25 17:37, Bernhard Beschow wrote:
>> Input GPIO values such as a present SD card may get notified before the GPIO
>> controller itself gets reset. Claring the input values thus loses data.
>> Assuming
>
>
On 3.02.2025 22:27, Peter Xu wrote:
On Thu, Jan 30, 2025 at 11:08:34AM +0100, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Add a basic support for receiving device state via multifd channels -
channels that are shared with RAM transfers.
Depending whether MULTIFD_FLAG_DEVICE_STATE f
> Subject: Re: [PATCH v6 00/10] Support virtio-gpu DRM native context
>
> "Kim, Dongwon" writes:
>
> > Hi,
> >
> > The commit below could change the timing of drawing by making the
> > drawing done at refresh cycle instead of via drawing event. So it
> > looks like either dmabuf or client's fram
On Mon, Feb 03, 2025 at 09:15:52PM +0100, Maciej S. Szmigiero wrote:
> On 3.02.2025 20:58, Peter Xu wrote:
> > On Mon, Feb 03, 2025 at 02:57:36PM +0100, Maciej S. Szmigiero wrote:
> > > On 2.02.2025 13:45, Dr. David Alan Gilbert wrote:
> > > > * Maciej S. Szmigiero (m...@maciej.szmigiero.name) wrot
On Fri, Jan 31, 2025 at 10:50:48AM +0100, Kevin Wolf wrote:
> In order to support running an NBD export on inactive nodes, we must
> make sure to return errors for any operations that aren't allowed on
> inactive nodes. Reads are the only operation we know we need for
> inactive images, so to err o
On Fri, Jan 31, 2025 at 10:50:47AM +0100, Kevin Wolf wrote:
> Add an option in BlockExportOptions to allow creating an export on an
> inactive node without activating the node. This mode needs to be
> explicitly supported by the export type (so that it doesn't perform any
> operations that are forb
On Fri, Jan 31, 2025 at 10:50:51AM +0100, Kevin Wolf wrote:
> This tests different types of operations on inactive block nodes
> (including graph changes, block jobs and NBD exports) to make sure that
> users manually activating and inactivating nodes doesn't break things.
>
> Support for inactive
On Thu, Jan 30, 2025 at 11:08:31AM +0100, Maciej S. Szmigiero wrote:
> From: "Maciej S. Szmigiero"
>
> Automatic memory management helps avoid memory safety issues.
>
> Signed-off-by: Maciej S. Szmigiero
Reviewed-by: Peter Xu
--
Peter Xu
On 2/3/25 04:54, Paolo Bonzini wrote:
On 2/3/25 04:18, Richard Henderson wrote:
v1: 20250128004254.33442-1-richard.hender...@linaro.org
For v2, immediately disable 64-on-32 TCG.
I *suspect* that we should disable 64-on-32 for *all* accelerators.
The idea that an i686 binary on an x86_64 host m
The test sequence boots a ppce500 machine from kernel and disk.
The buildroot is built with the qemu_ppc64_e5500_defconfig config.
Signed-off-by: Cédric Le Goater
---
tests/functional/test_ppc64_e500.py | 30 +
1 file changed, 30 insertions(+)
diff --git a/tests/fun
On 03/02/2025 04.18, Richard Henderson wrote:
The fact that this is only enabled for x86 probably means it
was done incorrectly. Certainly the set of files selected to
go into the module is woefully incomplete. Drop it for now.
Signed-off-by: Richard Henderson
---
accel/tcg/meson.build | 11
Add support for reporting Hostwide state counters for nested KVM pseries
guests running with 'cap-nested-papr' on Qemu-TCG acting as
L0-hypervisor. sPAPR supports reporting various stats counters for
Guest-Management-Area(GMA) thats owned by L0-Hypervisor and are documented
at [1]. These stats coun
On 03/02/2025 04.18, Richard Henderson wrote:
Use CONFIG_TCG as a project-wide flag to indicate that TCG is enabled
for *some* target. Use CONFIG_TCG_TARGET to indicate that TCG is
enabled for a specific target.
Within a specific compilation unit, we can remap CONFIG_TCG based on
CONFIG_TCG_TAR
Harsh Prateek Bora writes:
> On 1/23/25 17:25, Vaibhav Jain wrote:
>> Add support for reporting Hostwide state counters for nested KVM pseries
>> guests running with 'cap-nested-papr' on Qemu-TCG acting as
>> L0-hypervisor. sPAPR supports reporting various stats counters for
>> Guest-Management-A
On 03/02/2025 10.57, Cédric Le Goater wrote:
The test sequence boots a ppce500 machine from kernel and disk.
The buildroot is built with the qemu_ppc64_e5500_defconfig config.
Signed-off-by: Cédric Le Goater
---
tests/functional/test_ppc64_e500.py | 30 +
1 file
On 03/02/2025 04.18, Richard Henderson wrote:
No need to expand this function inline.
Unexport qemu_plugin_opts to match.
Signed-off-by: Richard Henderson
---
include/qemu/plugin.h | 9 +
plugins/loader.c | 7 ++-
2 files changed, 7 insertions(+), 9 deletions(-)
Reviewed-
On 03/02/2025 04.18, Richard Henderson wrote:
These are not called so frequently as to be
performance sensitive.
Signed-off-by: Richard Henderson
---
include/tcg/perf.h | 23 ---
tcg/perf-stubs.c | 26 ++
tcg/meson.build| 2 ++
3 files cha
On 03/02/2025 04.18, Richard Henderson wrote:
Rather than unconditional linkage via system_ss, conditinally
include the static library via specific_ss. This will elide
the code when CONFIG_TCG is disabled for a specific target.
Signed-off-by: Richard Henderson
---
tcg/meson.build | 6 +-
On 03/02/2025 04.18, Richard Henderson wrote:
Provide out-of-line versions of some of the qemu/plugin.h API.
These will be referenced with --enable-plugin, but CONFIG_TCG
is disabled for a specific target.
Signed-off-by: Richard Henderson
---
plugins/stubs.c | 49 +
On 03/02/2025 04.18, Richard Henderson wrote:
Add tcg_allowed, qmp_x_query_jit, qmp_x_query_opcount.
These are referenced when CONFIG_TCG is enabled globally,
but not for a specific target.
Signed-off-by: Richard Henderson
---
accel/stubs/tcg-stub.c | 24
1 file chan
On 03/02/2025 04.18, Richard Henderson wrote:
Hack around mips32 host allowing kvm acceleration
of mips64 guest, but tcg is disabled.
Signed-off-by: Richard Henderson
---
target/mips/tcg/meson.build| 4 ++--
target/mips/tcg/system/meson.build | 6 +++---
2 files changed, 5 insertion
On 03/02/2025 04.18, Richard Henderson wrote:
Configuration of 64-bit host on 32-bit guest will shortly
be denied. Use a 32-bit guest instead.
Signed-off-by: Richard Henderson
---
.gitlab-ci.d/crossbuilds.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.gitlab-ci.d/c
On 03/02/2025 04.18, Richard Henderson wrote:
Define TARGET_LONG_BITS in each target's configure fragment.
Do this without removing the define in target/*/cpu-param.h
so that errors are caught like so:
In file included from .../src/include/exec/cpu-defs.h:26,
from ../src/target
On 03/02/2025 04.18, Richard Henderson wrote:
This is now handled by the configs/targets/*.mak fragment.
Signed-off-by: Richard Henderson
---
target/alpha/cpu-param.h | 2 --
target/arm/cpu-param.h| 2 --
target/avr/cpu-param.h| 1 -
target/hexagon/cpu-param.h| 1 -
On 03/02/2025 04.18, Richard Henderson wrote:
We deprecated i686 system mode support for qemu 8.0. However, to
make real cleanups to TCG we need to deprecate all 32-bit hosts.
Signed-off-by: Richard Henderson
---
docs/about/deprecated.rst | 7 +++
meson.build | 6 ++
On Fri, 31 Jan 2025 18:42:47 +0100
Mauro Carvalho Chehab wrote:
> The hw_error_le pointer is used for legacy support (virt-9.2).
> Starting from virt-10.0, HEST table is accessed via hest_addr_le.
>
> Remove fw_cfg logic for legacy support if virt is 10.0 or upper.
>
> Signed-off-by: Mauro Carv
On Fri, 31 Jan 2025 18:42:49 +0100
Mauro Carvalho Chehab wrote:
> Move the check logic into a common function and simplify the
> code which checks if GHES is enabled and was properly setup.
>
> Signed-off-by: Mauro Carvalho Chehab
> Reviewed-by: Jonathan Cameron
> Reviewed-by: Igor Mammedov
On Fri, 31 Jan 2025 18:42:44 +0100
Mauro Carvalho Chehab wrote:
> There are two pointers that are needed during error injection:
>
> 1. The start address of the CPER block to be stored;
> 2. The address of the ack.
>
> It is preferable to calculate them from the HEST table. This allows
> check
On 03/02/2025 04.18, Richard Henderson wrote:
For system mode, we can rarely support the amount of RAM that
the guest requires. Emulation is restricted to round-robin
mode, which solves many of the atomicity issues, but not those
associated with virtio. In any case, round-robin does nothing
to h
On Fri, 31 Jan 2025 18:42:53 +0100
Mauro Carvalho Chehab wrote:
> --- a/DSDT.dsl2025-01-28 09:38:15.155347858 +0100
> +++ b/DSDT.dsl2025-01-28 09:39:01.684836954 +0100
> @@ -9,9 +9,9 @@
> *
> * Original Table Header:
> * Signature"DSDT"
> - * Length
On Fri, 31 Jan 2025 18:42:55 +0100
Mauro Carvalho Chehab wrote:
> Using the QMP GHESv2 API requires preparing a raw data array
> containing a CPER record.
>
> Add a helper script with subcommands to prepare such data.
>
> Currently, only ARM Processor error CPER record is supported, by
> using:
On Fri, 24 Jan 2025 at 17:22, Paolo Bonzini wrote:
>
> Queued, thanks.
Thanks; do you plan to send a pullreq with these in soon?
I ask because the Arm FEAT_AFP set is now ready to land
and it has a dependency on these.
thanks
-- PMM
Hi Andrew,
> From: Andrew Jeffery
> Sent: Thursday, January 30, 2025 12:22 PM
> To: Jamin Lin ; Cédric Le Goater ;
> Peter Maydell ; Steven Lee
> ; Troy Lee ; Joel Stanley
> ; open list:ASPEED BMCs ; open
> list:All patches CC here
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re: [PATCH v1 14/18]
Hi Marc-Andre,
Do you plan to pull the latest version of this series,
or is there something which I have to address?
Please let me know.
Thanks.
--
Roman
On Thu, Jan 23, 2025 at 9:53 AM Roman Penyaev wrote:
>
> Mux is a character backend (host side) device, which multiplexes
> multiple fronten
Dmitry Osipenko writes:
> On 1/27/25 19:17, Alex Bennée wrote:
> ...
>> I'm still seeing corruption with -display gtk,gl=on on my x86 system
>> BTW. I would like to understand if that is a problem with QEMU, GTK or
>> something else in the stack before we merge.
>
> I reproduced the display mirro
Peter Maydell writes:
> On Wed, 29 Jan 2025 at 06:23, Thomas Huth wrote:
>> So unless someone complains immediately with a good reason, I'm also in
>> favor of marking it as deprecated now. If then someone complains during the
>> deprecation period, we still can reconsider and remove the depreca
On Mon, Feb 3, 2025 at 7:58 AM wrote:
>
> From: Marc-André Lureau
>
> The following changes since commit 6fccaa2fba391815308a746d68f7fa197bc93586:
>
> Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
> staging (2025-02-02 11:09:10 -0500)
>
> are available in the Git repo
Hello Maciej,
This patch set is targeting QEMU 10.0.
What's not yet present is documentation update under docs/devel/migration
but I didn't want to delay posting the code any longer.
Such doc can still be merged later when the design is 100% finalized.
The changes are quite complex, the design
Peter Maydell writes:
> On Sat, 1 Feb 2025 at 12:57, BALATON Zoltan wrote:
>>
>> On Sat, 1 Feb 2025, Philippe Mathieu-Daudé wrote:
>> > - Deprecate the 'raspi4b' machine name, renaming it as
>> > 'raspi4b-1g' on 32-bit hosts, 'raspi4b-2g' otherwise.
>> > - Add the 'raspi4b-4g' and 'raspi4b-8g'
On Mon, Feb 03, 2025 at 02:29:49PM +, Alex Bennée wrote:
> Peter Maydell writes:
>
> > On Sat, 1 Feb 2025 at 12:57, BALATON Zoltan wrote:
> >>
> >> On Sat, 1 Feb 2025, Philippe Mathieu-Daudé wrote:
> >> > - Deprecate the 'raspi4b' machine name, renaming it as
> >> > 'raspi4b-1g' on 32-bit h
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