Split IPACK Kconfig key as {IPACK, TPCI200, IP_OCTAL_232}
- IPack is a bus
- TPCI200 is a PCI device providing an IPack bus
- IP-Octal232 is an IPack device plugged on an IPack bus
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/Kconfig| 5 +
hw/char/meson.build
No need to dynamically allocate IRQ when we know before hands
how many we'll use. Declare the 2 of them in IPackDevice state
and initialize them in the DeviceRealize handler.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/ipack/ipack.h | 7 ++-
hw/char/ipoctal232.c | 4 ++--
hw/ipa
Clarify what is what in Kconfig,
replace qemu_allocate_irqs() by qemu_init_irq().
Since v1:
- s/qemu_irq/IRQState/ in IPackDevice state
Philippe Mathieu-Daudé (2):
hw/ipack: Clarify KConfig symbols
hw/ipack: Remove legacy qemu_allocate_irqs() use
include/hw/ipack/ipack.h | 7 ++-
Hi Stefano,
On 1/21/25 9:45 AM, Stefano Garzarella wrote:
> On Tue, Jan 21, 2025 at 09:31:53AM +0100, Laurent Vivier wrote:
>> On 20/01/2025 18:33, Eric Auger wrote:
>>> When a guest exposed with a vhost device and protected by an
>>> intel IOMMU gets rebooted, we sometimes observe a spurious war
On 1/21/25 9:31 AM, Laurent Vivier wrote:
> On 20/01/2025 18:33, Eric Auger wrote:
>> When a guest exposed with a vhost device and protected by an
>> intel IOMMU gets rebooted, we sometimes observe a spurious warning:
>>
>> Fail to lookup the translated address e000
>>
>> We observe that th
On 1/21/25 07:55, Philippe Mathieu-Daudé wrote:
No need to dynamically allocate IRQ when we know before hands
how many we'll use. Declare the 2 of them in IPackDevice state
and initialize them in the DeviceRealize handler.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/ipack/ipack.h | 7
On 1/21/25 07:55, Philippe Mathieu-Daudé wrote:
While qemu_init_irq() initialize a single IRQ,
qemu_init_irqs() initialize an array of them.
Suggested-by: Bernhard Beschow
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/irq.h | 11 +++
hw/core/irq.c| 8
2 files c
On 1/21/25 08:18, Philippe Mathieu-Daudé wrote:
MIPS CPU timer is tied to the CPU, no point of modelling it as
a general timer device. Move mips_int.c to target/mips/system/.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/mips_int.c => target/mips/system/interrupts.c | 0
hw/mips/meson.bu
On 1/21/25 08:18, Philippe Mathieu-Daudé wrote:
The MIPS timer and IRQs are tied to the CPU. Creating them outside
in board code isn't correct. Do it once in the DeviceRealize() handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/cps.c| 4
hw/mips/fuloong2e.c | 4
On 1/21/25 08:18, Philippe Mathieu-Daudé wrote:
There are always 8 IRQs created with a MIPS CPU.
Allocate their state once in CPUMIPSState, initialize
them in place in cpu_mips_irq_init_cpu(). Update hw/ uses.
Move cpu_mips_irq_init_cpu() declaration from "cpu.h"
to "internal.h", as it shouldn't
On 1/18/25 09:10, Michael Tokarev wrote:
05.01.2025 16:59, Volker Rümelin wrote:
In function create_long_filname(), the array name[8 + 3] in
struct direntry_t is used as if it were defined as name[32].
This is intentional and works. It's nevertheless an out of
bounds array access. To avoid this
On 1/21/25 10:24, Philippe Mathieu-Daudé wrote:
The FPGA exposes a fixed set of IRQs. Hold them in the FPGA
state and initialize them in place calling qemu_init_irqs().
Move r2d_fpga_irq enums earlier so we can use NR_IRQS within
the r2d_fpga_t structure. r2d_fpga_init() returns r2d_fpga_t,
and
On 1/21/25 09:06, Daniel Henrique Barboza wrote:
In the RISC-V privileged ISA section 3.1.15 table 15, it is determined
that a debug exception that is triggered from a load/store has a higher
priority than a possible fault that this access might trigger.
This is not the case ATM as shown in [1].
On 1/21/25 10:28, Philippe Mathieu-Daudé wrote:
There are a fixed number of PCI IRQs, known beforehand.
Allocate them within PCIMultiSerialState, and initialize
using qemu_init_irq(), allowing to remove the legacy
qemu_allocate_irqs() and qemu_free_irqs() calls.
Signed-off-by: Philippe Mathieu-D
On 1/21/25 03:40, Philippe Mathieu-Daudé wrote:
Cache CPUClass as early as possible, when the instance
is initialized.
Signed-off-by: Philippe Mathieu-Daudé
---
cpu-target.c | 3 ---
hw/core/cpu-common.c | 3 +++
2 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richar
On 1/21/25 16:43, Zhao Liu wrote:
Configuring "--enable-user --disable-system --enable-tools" causes the
build failure with the following information:
/usr/bin/ld: libhwcore.a.p/hw_core_qdev.c.o: in function `device_finalize':
/qemu/build/../hw/core/qdev.c:688: undefined reference to
`qapi_even
Clarify what is what in Kconfig,
replace qemu_allocate_irqs() by qemu_init_irq().
Since v2:
- Introduce qemu_init_irqs (Bernhard)
Since v1:
- s/qemu_irq/IRQState/ in IPackDevice state
Philippe Mathieu-Daudé (3):
hw/irq: Introduce qemu_init_irqs() helper
hw/ipack: Clarify KConfig symbols
hw
On 1/21/25 03:40, Philippe Mathieu-Daudé wrote:
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé
---
disas/disas-common.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
dif
Roman Penyaev writes:
> On Tue, Jan 21, 2025 at 4:02 PM Alex Bennée wrote:
>>
>> Roman Penyaev writes:
>>
>> > This adds a few lines describing `hub` aggregator configuration
>> > for aggregation of several backend devices with a single frontend
>> > device.
>> >
>> > Signed-off-by: Roman Penya
The MIPS timer and IRQs are tied to the CPU. Creating them outside
in board code isn't correct. Do it once in the DeviceRealize() handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/cps.c| 4
hw/mips/fuloong2e.c | 4
hw/mips/jazz.c | 4
hw/mips/lo
Simplify cpu_mips_clock_init() by having it directly take
a CPU env, move its declaration from "cpu.h" to "internal.h",
as it shouldn't be accessible from hw/.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 1 -
target/mips/internal.h | 1 +
target/mips/cpu.c
In the RISC-V privileged ISA section 3.1.15 table 15, it is determined
that a debug exception that is triggered from a load/store has a higher
priority than a possible fault that this access might trigger.
This is not the case ATM as shown in [1]. Adding a breakpoint in an
address that deliberatel
Hi,
In this new version, in patch 2, we're using the address 'size' val from
riscv_cpu_tlb_fill() instead of infering it from the CPU XLEN.
No other changes made. Patches based on master.
Changes from v2:
- patch 2:
- use 'size' instead of infering wp_len using the CPU XLEN
- v2 link:
https:
This "anon" memory cannot be "shared" with other processes, but
virtio-kernel etc. can just use it.
To "share" the memory with other processes, we'd need memfd/file.
Ah OK, thanks David. Is this the planned long term solution for
vhost-kernel?
I think the basic idea was that the memory backe
On Tue, Jan 21, 2025 at 09:41:55PM +0100, David Hildenbrand wrote:
> So far my understanding is that Google that does shared+private guest_memfd
> kernel part won't be working on QEMU patches. I raised that to our
> management recently, that this would be a good project for RH to focus on.
>
> I a
On Tue, Jan 21, 2025 at 05:59:56PM +, “William Roche wrote:
> From: William Roche
>
> Punching a hole in a file with fallocate needs to take into account the
> fd_offset value for a correct file location.
>
> Fixes: 4b870dc4d0c0 ("hostmem-file: add offset option")
>
> Signed-off-by: William
On 21/1/25 18:06, Daniel Henrique Barboza wrote:
The mcontrol select bit (19) is always zero, meaning our triggers will
always match virtual addresses. In this condition, if the user does not
specify a size for the trigger, the access size defaults to XLEN.
At this moment we're using def_size =
The FPGA exposes a fixed set of IRQs. Hold them in the FPGA
state and initialize them in place calling qemu_init_irqs().
Move r2d_fpga_irq enums earlier so we can use NR_IRQS within
the r2d_fpga_t structure. r2d_fpga_init() returns r2d_fpga_t,
and we dereference irq from it in r2d_init().
Signed-
On 21.01.25 18:39, Peter Xu wrote:
On Wed, Mar 20, 2024 at 03:39:03AM -0500, Michael Roth wrote:
From: Xiaoyao Li
Add a new member "guest_memfd" to memory backends. When it's set
to true, it enables RAM_GUEST_MEMFD in ram_flags, thus private kvm
guest_memfd will be allocated during RAMBlock al
On 21.01.25 19:17, Peter Xu wrote:
On Tue, Jan 21, 2025 at 05:59:56PM +, “William Roche wrote:
From: William Roche
Punching a hole in a file with fallocate needs to take into account the
fd_offset value for a correct file location.
Fixes: 4b870dc4d0c0 ("hostmem-file: add offset option")
There are a fixed number of PCI IRQs, known beforehand.
Allocate them within PCIMultiSerialState, and initialize
using qemu_init_irq(), allowing to remove the legacy
qemu_allocate_irqs() and qemu_free_irqs() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: <20250121155526.29982-2-phi...
On 21/1/25 17:18, Philippe Mathieu-Daudé wrote:
There are always 8 IRQs created with a MIPS CPU.
Allocate their state once in CPUMIPSState, initialize
them in place in cpu_mips_irq_init_cpu(). Update hw/ uses.
Move cpu_mips_irq_init_cpu() declaration from "cpu.h"
to "internal.h", as it shouldn't
On Tue, 3 Dec 2024 20:26:19 -0600
Hongjian Fan wrote:
> This patch allows a CXL type3 device to be initialized with zero memory
> size, when there is no memory device property provided.
>
> Signed-off-by: Hongjian Fan
Hi Hongjian
Some remaining questions on the v1 thread.
We need to understan
Hi Jason,
On 1/21/25 4:27 AM, Jason Wang wrote:
> On Tue, Jan 21, 2025 at 1:33 AM Eric Auger wrote:
>> When a guest exposed with a vhost device and protected by an
>> intel IOMMU gets rebooted, we sometimes observe a spurious warning:
>>
>> Fail to lookup the translated address e000
>>
>> W
The mcontrol select bit (19) is always zero, meaning our triggers will
always match virtual addresses. In this condition, if the user does not
specify a size for the trigger, the access size defaults to XLEN.
At this moment we're using def_size = 8 regardless of CPU XLEN. Use
def_size = 4 in case
On 21.01.25 21:59, Peter Xu wrote:
On Tue, Jan 21, 2025 at 09:41:55PM +0100, David Hildenbrand wrote:
So far my understanding is that Google that does shared+private guest_memfd
kernel part won't be working on QEMU patches. I raised that to our
management recently, that this would be a good proj
Am 21. Januar 2025 03:00:17 UTC schrieb BALATON Zoltan :
>On Mon, 20 Jan 2025, Bernhard Beschow wrote:
>> On a real device, the boot ROM contains the very first instructions the CPU
>> executes. Also, U-Boot calls into the ROM to determine the boot device. While
>> we're not actually implementin
On Sun, Jan 19, 2025 at 7:37 AM Sahil Siddiq wrote:
>
> Hi,
>
> On 1/7/25 1:35 PM, Eugenio Perez Martin wrote:
> > On Fri, Jan 3, 2025 at 2:06 PM Sahil Siddiq wrote:
> >>
> >> Hi,
> >>
> >> On 12/20/24 12:28 PM, Eugenio Perez Martin wrote:
> >>> On Thu, Dec 19, 2024 at 8:37 PM Sahil Siddiq
> >>
On Tue, Jan 21, 2025 at 3:53 PM Jonah Palmer wrote:
>
>
>
> On 1/16/25 11:44 AM, Eugenio Perez Martin wrote:
> > On Fri, Jan 10, 2025 at 6:09 PM Jonah Palmer
> > wrote:
> >>
> >> Decouples the IOVA allocator from the full IOVA->HVA tree to support a
> >> SVQ IOVA->HVA tree for host-only memory m
On Tue, Jan 21, 2025 at 10:06:47AM +0800, Tao Su wrote:
> Update SierraForest CPU model to add LAM, 4 bits indicating certain bits
> of IA32_SPEC_CTR are supported(intel-psfd, ipred-ctrl, rrsba-ctrl,
> bhi-ctrl) and the missing features(ss, tsc-adjust, cldemote, movdiri,
> movdir64b)
>
> Also add
On Tue, Jan 21, 2025 at 10:06:48AM +0800, Tao Su wrote:
> Branch History Injection (BHI) is a CPU side-channel vulnerability, where
> an attacker may manipulate branch history before transitioning from user
> to supervisor mode or from VMX non-root/guest to root mode. CPUs that set
> BHI_NO bit in
On Wed, Mar 20, 2024 at 03:39:03AM -0500, Michael Roth wrote:
> From: Xiaoyao Li
>
> Add a new member "guest_memfd" to memory backends. When it's set
> to true, it enables RAM_GUEST_MEMFD in ram_flags, thus private kvm
> guest_memfd will be allocated during RAMBlock allocation.
>
> Memory backen
On 1/21/2025 8:23 AM, Philippe Mathieu-Daudé wrote:
Currently only user emulation is supported.
Assert no target code is built for system emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
target/hexagon/cpu.h | 4
1 file changed, 4 insertions(+)
diff --git a/target/hexagon/cpu.h b
On 20/1/25 21:49, Daniel Henrique Barboza wrote:
The mcontrol select bit (19) is always zero, meaning our triggers will
always match virtual addresses. In this condition, if the user does not
specify a size for the trigger, the access size defaults to XLEN.
At this moment we're using def_size =
On Tue, Jan 21, 2025 at 07:24:29PM +0100, David Hildenbrand wrote:
> On 21.01.25 18:39, Peter Xu wrote:
> > On Wed, Mar 20, 2024 at 03:39:03AM -0500, Michael Roth wrote:
> > > From: Xiaoyao Li
> > >
> > > Add a new member "guest_memfd" to memory backends. When it's set
> > > to true, it enables R
On 1/21/25 03:40, Philippe Mathieu-Daudé wrote:
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/acpi/cpu.c | 4 ++--
hw/acpi/cpu_hotplug.c | 3 +--
2 files changed, 3 i
On 1/21/25 03:40, Philippe Mathieu-Daudé wrote:
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé
---
gdbstub/gdbstub.c | 26 +-
gdbstub/system.c | 7 ++-
On 1/21/25 15:04, Zhao Liu wrote:
(Resend the series since it was missed on https://lore.kernel.org/qemu-devel/.)
Hi,
This series includes the following cleanups:
* Patch 1: Make realize() safe to only accept immutable self
reference, which is in prepare to introduce gpio bindin
On Thu, 12 Dec 2024 05:04:21 -0800
Zhi Wang wrote:
> There are many DVSEC registers in the PCI configuration space that are
> configurable. E.g. DVS control. They are configured and initalized in
> cxl_component_create_dvsec(). When the virtual machine reboots, the
> reset callback in the emulati
On 1/21/25 03:40, Philippe Mathieu-Daudé wrote:
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/alpha/target_proc.h | 2 +-
bsd-user/signal.c | 4 ++--
linu
On 1/21/25 03:40, Philippe Mathieu-Daudé wrote:
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/accel-target.c | 12 +---
accel/tcg/tcg-accel-ops.c | 3 +--
acc
On Tue, Jan 21, 2025 at 09:35:26AM +0800, Chenyi Qiang wrote:
>
>
> On 1/21/2025 2:33 AM, Peter Xu wrote:
> > On Mon, Jan 20, 2025 at 06:54:14PM +0100, David Hildenbrand wrote:
> >> On 20.01.25 18:21, Peter Xu wrote:
> >>> On Mon, Jan 20, 2025 at 11:48:39AM +0100, David Hildenbrand wrote:
>
On Tue, Jan 21, 2025 at 4:25 PM Jonah Palmer wrote:
>
>
>
> On 1/16/25 2:00 PM, Eugenio Perez Martin wrote:
> > On Fri, Jan 10, 2025 at 6:09 PM Jonah Palmer
> > wrote:
> >>
> >> Implements the GPA->IOVA tree for handling mapping and unmapping for
> >> guest memory. This, alongside the SVQ IOVA->
Hi Thomas,
Please take a look at these CI failures:
https://gitlab.com/qemu-project/qemu/-/jobs/8913471007
https://gitlab.com/qemu-project/qemu/-/jobs/8913471508
https://gitlab.com/qemu-project/qemu/-/jobs/8913472011
Thanks,
Stefan
On 1/2/25 10:25, Philippe Mathieu-Daudé wrote:
Very few source files require to access "exec/tb-flush.h"
declarations, and except a pair, they all include it
explicitly. No need to overload the generic "user-internals.h".
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/user-internals.h |
On 1/2/25 10:25, Philippe Mathieu-Daudé wrote:
Since tcg_cpu_reset_hold() is a system emulation specific
helper, factor tcg_exec_reset() out so we can use it from
user emulation, similarly to the [un]realize() handlers.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-common.h | 1
On 1/2/25 10:25, Philippe Mathieu-Daudé wrote:
Commit bb6cf6f0168 ("accel/tcg: Factor tcg_cpu_reset_hold()
out") wanted to restrict tlb_flush() to system emulation,
but inadvertently also restricted tcg_flush_jmp_cache(),
which was before called on user emulation via:
Realize -> Reset -> cpu_
On Tue, Jan 21, 2025 at 4:23 PM Roman Penyaev wrote:
>
> On Tue, Jan 21, 2025 at 4:02 PM Alex Bennée wrote:
> >
> > Roman Penyaev writes:
> >
> > > This adds a few lines describing `hub` aggregator configuration
> > > for aggregation of several backend devices with a single frontend
> > > device
On 21/1/25 17:18, Philippe Mathieu-Daudé wrote:
IRQ cleanup in bonito64 in order to remove legacy qemu_allocate_irqs
call in target/mips/.
Philippe Mathieu-Daudé (6):
hw/pci-host/bonito: Expose output IRQ as QDev GPIO
target/mips: Create clock *after* accelerator vCPU is realized
target
On 28/11/2024 18:29, Joao Martins wrote:
> On 28/11/2024 03:19, Zhangfei Gao wrote:
>> Hi, Joao
>>
>> On Fri, Jun 23, 2023 at 5:51 AM Joao Martins
>> wrote:
>>>
>>> Hey,
>>>
>>> This series introduces support for vIOMMU with VFIO device migration,
>>> particurlarly related to how we do the dirty
On 1/21/25 12:47 PM, Richard Henderson wrote:
On 1/20/25 12:49, Daniel Henrique Barboza wrote:
In the RISC-V privileged ISA section 3.1.15 table 15, it is determined
that a debug exception that is triggered from a load/store has a higher
priority than a possible fault that this access might t
On 07/01/2025 06:55, Zhangfei Gao wrote:
> Hi, Joao
>
> On Fri, Jun 23, 2023 at 5:51 AM Joao Martins
> wrote:
>>
>> Hey,
>>
>> This series introduces support for vIOMMU with VFIO device migration,
>> particurlarly related to how we do the dirty page tracking.
>>
>> Today vIOMMUs serve two purpos
From: William Roche
Punching a hole in a file with fallocate needs to take into account the
fd_offset value for a correct file location.
Fixes: 4b870dc4d0c0 ("hostmem-file: add offset option")
Signed-off-by: William Roche
---
system/physmem.c | 14 --
1 file changed, 8 insertions(
From: William Roche
Working on the poisoned memory recovery mechanisms with David
Hildenbrand, it appeared that the file hole punching done with
the memory discard functions are missing the file offset value
fd_offset to correctly modify the right file location.
I'm not sure that guest_memfd wou
On Tue, Jan 21, 2025 at 06:40:28PM +0530, Prasad Pandit wrote:
> From: Prasad Pandit
>
> Hello,
>
> * Currently Multifd and Postcopy migration can not be used together.
> QEMU shows "Postcopy is not yet compatible with multifd" message.
>
> When migrating guests with large (100's GB) RAM, M
Hi Zhi,
> index 945ee6ffd0..abb2e874b2 100644
> --- a/include/hw/cxl/cxl_component.h
> +++ b/include/hw/cxl/cxl_component.h
> @@ -268,6 +268,9 @@ uint8_t cxl_interleave_ways_enc(int iw, Error **errp);
> int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp);
> uint8_t cxl_interleave_granula
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 1 +
1 file changed, 1 insertion(+)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs
index c95ab49fd62..4f1080ff19f 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/devic
Hi,
On 1/21/25 9:31 AM, Laurent Vivier wrote:
> On 20/01/2025 18:33, Eric Auger wrote:
>> When a guest exposed with a vhost device and protected by an
>> intel IOMMU gets rebooted, we sometimes observe a spurious warning:
>>
>> Fail to lookup the translated address e000
>>
>> We observe that
On 1/19/25 22:15, Philippe Mathieu-Daudé wrote:
Directly pass CPUX86State to x86_cpu_pending_interrupt().
Since it doesn't modify the dereferenced fields, make the
argument const.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.h | 2 +-
target/i386/cpu.c
On 1/21/25 03:40, Philippe Mathieu-Daudé wrote:
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 10 +++-
cpu-common.c | 10
cpu-target
No need to dynamically allocate IRQ when we know before hands
how many we'll use. Declare the 2 of them in IPackDevice state
and initialize them in the DeviceRealize handler.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/ipack/ipack.h | 7 ++-
hw/char/ipoctal232.c | 4 ++--
hw/ipa
Split IPACK Kconfig key as {IPACK, TPCI200, IP_OCTAL_232}
- IPack is a bus
- TPCI200 is a PCI device providing an IPack bus
- IP-Octal232 is an IPack device plugged on an IPack bus
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/Kconfig| 5 +
hw/char/meson.build
While qemu_init_irq() initialize a single IRQ,
qemu_init_irqs() initialize an array of them.
Suggested-by: Bernhard Beschow
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/irq.h | 11 +++
hw/core/irq.c| 8
2 files changed, 19 insertions(+)
diff --git a/include/hw/irq
There are always 8 IRQs created with a MIPS CPU.
Allocate their state once in CPUMIPSState, initialize
them in place in cpu_mips_irq_init_cpu(). Update hw/ uses.
Move cpu_mips_irq_init_cpu() declaration from "cpu.h"
to "internal.h", as it shouldn't be accessible from hw/.
Signed-off-by: Philippe
On Thu, 12 Dec 2024 05:04:22 -0800
Zhi Wang wrote:
> From: Zhi Wang
>
> Introduce a CXL type-2 device emulation that provides a minimum base for
> testing kernel CXL core type-2 support and CXL type-2 virtualization. It
> is also a good base for introducing the more emulated features.
>
> Curr
Expose IRQ using qdev_init_gpio_out() in bonito_host_realize(),
wire it using qdev_connect_gpio_out() in bonito_init().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/mips.h | 2 +-
hw/mips/fuloong2e.c| 2 +-
hw/pci-host/bonito.c | 14 +++---
3 files changed, 9 inserti
MIPS CPU timer is tied to the CPU, no point of modelling it as
a general timer device. Move mips_int.c to target/mips/system/.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/mips_int.c => target/mips/system/interrupts.c | 0
hw/mips/meson.build | 2 +-
target
Architecture specific hardware doesn't have a particular dependency
on the accelerator vCPU (created with cpu_exec_realizefn), and can
be initialized *after* the vCPU is realized.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.c | 28 ++-
IRQ cleanup in bonito64 in order to remove legacy qemu_allocate_irqs
call in target/mips/.
Philippe Mathieu-Daudé (6):
hw/pci-host/bonito: Expose output IRQ as QDev GPIO
target/mips: Create clock *after* accelerator vCPU is realized
target/mips: Initialize CPU-specific timer/IRQs once in Dev
Returning target segment low boundary address multiple
shouldn't need to modify the CPU env. Make it const.
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/arm/target_syscall.h| 2 +-
linux-user/mips/target_syscall.h | 2 +-
linux-user/mips64/target_syscall.h | 2 +-
linux-user/sh4/ta
On 21/1/25 19:47, Daniel Henrique Barboza wrote:
On 1/21/25 2:40 PM, Philippe Mathieu-Daudé wrote:
On 20/1/25 21:49, Daniel Henrique Barboza wrote:
The mcontrol select bit (19) is always zero, meaning our triggers will
always match virtual addresses. In this condition, if the user does not
sp
Thank you Peter and David for your feedback.
On 1/21/25 19:25, David Hildenbrand wrote:
On 21.01.25 19:17, Peter Xu wrote:
On Tue, Jan 21, 2025 at 05:59:56PM +, “William Roche wrote:
From: William Roche
Punching a hole in a file with fallocate needs to take into account the
fd_offset va
On 21.01.25 19:38, William Roche wrote:
Thank you Peter and David for your feedback.
On 1/21/25 19:25, David Hildenbrand wrote:
On 21.01.25 19:17, Peter Xu wrote:
On Tue, Jan 21, 2025 at 05:59:56PM +, “William Roche wrote:
From: William Roche
Punching a hole in a file with fallocate ne
Coverity found a DEADCODE issue in rmw_xireg() claiming that we can't
reach 'RISCV_EXCP_VIRT_INSTRUCTION_FAULT' at the 'done' label:
done:
if (ret) {
return (env->virt_enabled && virt) ?
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_
Change makes code symmetric to the code, which handles
the "connected" state, i.e. send CHR_EVENT_CLOSED when
state changes from "connected" to "disconnected".
This behavior is similar to char-socket, for example.
Signed-off-by: Roman Penyaev
Reviewed-by: "Alex Bennée"
Cc: "Marc-André Lureau"
Hi,
This series contains Coverity fixes for issues found in the latest
RISC-V pull made yesterday.
Coverity CIDs being resolved: 1590355, 1590356, 1590357, 1590358 and
1590359.
Patches based on master.
Daniel Henrique Barboza (5):
target/riscv/csr.c: fix deadcode in rmw_xireg()
target/ri
This adds a few lines describing `hub` aggregator configuration
for aggregation of several backend devices with a single frontend
device.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
qemu-options.hx | 49 +
1
On 1/21/25 2:40 PM, Philippe Mathieu-Daudé wrote:
On 20/1/25 21:49, Daniel Henrique Barboza wrote:
The mcontrol select bit (19) is always zero, meaning our triggers will
always match virtual addresses. In this condition, if the user does not
specify a size for the trigger, the access size def
Coverity reported a DEADCODE ticket in this function, as follows:
CID 1590358: Control flow issues (DEADCODE)
Execution cannot reach this statement: "return ret;".
> 380 return ret;
> 381 }
The cause is that the 'if (ret != RISCV_EXCP_NONE)' condition
This patch implements a new chardev backend `hub` device, which
aggregates input from multiple backend devices and forwards it to a
single frontend device. Additionally, `hub` device takes the output
from the frontend device and sends it back to all the connected
backend devices. This allows for se
This commit introduces a new test function `char_hub_test` to validate
the functionality and constraints of the "hub" chardev backend in QEMU.
The test includes multiple scenarios:
1. Invalid hub creation:
- Creating a hub without defining `chardevs.N` (expects an error).
- Creating a hub wi
Coverity found a DEADCODE issue in rmw_xiregi() claiming that we can't
reach 'RISCV_EXCP_VIRT_INSTRUCTION_FAULT' at the 'done' label:
> 2652 done:
CID 1590357: Control flow issues (DEADCODE)
Execution cannot reach the expression
"RISCV_EXCP_VIRT_INSTRUCTION_FAUL
Coverity found a second DEADCODE issue in rmw_xireg() claiming that we can't
reach 'RISCV_EXCP_NONE' at the 'done' label:
> 2706 done:
> 2707 if (ret) {
> 2708 return (env->virt_enabled && virt) ?
> 2709RISCV_EXCP_VIRT_INSTRUCTION_FAULT :
> RISCV_E
Mux is a character backend (host side) device, which multiplexes
multiple frontends with one backend device. The following is a
few lines from the QEMU manpage [1]:
A multiplexer is a "1:N" device, and here the "1" end is your
specified chardev backend, and the "N" end is the various parts
o
Coverity reported a BAD_SHIFT issue in the following code:
> 2097
CID 1590355: Integer handling issues (BAD_SHIFT)
In expression "hdeleg >> cause", right shifting by more than 63
bits has undefined behavior. The shift amount, "cause", is at least 64.
> 2098
On 21/1/25 12:40, Philippe Mathieu-Daudé wrote:
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/generic-loader.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
On 21/1/25 12:40, Philippe Mathieu-Daudé wrote:
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/microblaze/gdbstub.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
Am 21. Januar 2025 08:44:52 UTC schrieb "Philippe Mathieu-Daudé"
:
>No need to dynamically allocate IRQ when we know before hands
>how many we'll use. Declare the 2 of them in IPackDevice state
>and initialize them in the DeviceRealize handler.
>
>Signed-off-by: Philippe Mathieu-Daudé
>---
> i
In vhost_user_receive() if vhost_net_notify_migration_done() reports
an error we display on the console:
Vhost user backend fails to broadcast fake RARP
This message can be useful if there is a problem to execute
VHOST_USER_SEND_RARP but it is useless if the backend doesn't
support VHOST_USER_P
The code in net_init_ip() currently bails out early if "rc" is less
than 0, so the if-statements that check for negative "rc" codes to
print out some specific error messages with regards to the TFTP server
are never reached. Move them earlier to bring that dead code back to
life.
Reviewed-by: Jare
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