On 19/12/24 18:46, Daniel Henrique Barboza wrote:
Do a cosmetic change in riscv_raise_exception() to change 'exception'
type from uint32_t to RISCVException, making it a bit clear that the
arg is directly correlated to the RISCVException enum.
As a side effect, change 'excp' type from int to RIS
On Fri, Jan 3, 2025 at 2:04 AM Andrea Bolognani wrote:
>
> On Tue, Dec 03, 2024 at 10:47:02AM +0100, Andrea Bolognani wrote:
> > Currently the script won't generate a configuration file that
> > sets up qemu-user-riscv32 on riscv64, likely under the
> > assumption that 64-bit RISC-V machines can n
On Wed, Dec 25, 2024 at 10:38 PM Ivan Klokov wrote:
>
> The RISC-V architecture supports the creation of custom
> CSR-mapped devices. It would be convenient to test them in the same way
> as MMIO-mapped devices. To do this, a new call has been added
> to read/write CSR registers.
>
> Signed-off-by
On Wed, Dec 25, 2024 at 10:39 PM Ivan Klokov wrote:
>
> Added demo for reading CSR register from qtest environment.
>
> Signed-off-by: Ivan Klokov
> Reviewed-by: Fabiano Rosas
> Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Alistair
> ---
> tests/qtest/meson.build |
Bump / Ping
On Thu, Dec 19, 2024 at 6:11 PM Sam Price wrote:
>
> Bump / ping
>
> Sincerely,
>
> Sam Price
>
>
>
> On Thu, Dec 5, 2024 at 10:29 PM Sam Price wrote:
>>
>> I needed to set the registers prior to boot up to mimic what uboot
>> would do prior to loading a binary. This adds a generic
On Tue, Dec 31, 2024 at 1:28 PM wrote:
>
> From: Tommy Wu
>
> Because the RNMI interrupt trap handler address is implementation defined.
> We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property
> of the harts. It’s very easy for users to set the address based on their
> ex
On Thu, Dec 19, 2024 at 12:15 AM Craig Blackmore
wrote:
>
> Changes since v7:
> - Fixed typo `bits` -> `bytes`
> - Tuned threshold for applying the optimization
> - Provided results for larger sizes requested by Max Chou
>
> This patch provides up to 60% speedup on the `memcpy` benchmark from:
>
>
On Mon, Dec 16, 2024 at 7:38 AM Yanfeng Liu wrote:
>
> This adds virtualization mode (V bit) as bit(2) of register `priv`
> per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1.
>
> Note that GDB may display `INVALID` tag for `priv` reg when V bit
> is set, this doesn't affect actual
On Mon, Dec 16, 2024 at 7:38 AM Yanfeng Liu wrote:
>
> This adds virtualization mode (V bit) as bit(2) of register `priv`
> per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1.
>
> Note that GDB may display `INVALID` tag for `priv` reg when V bit
> is set, this doesn't affect actual
On Fri, Jan 3, 2025 at 4:21 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> tcg/riscv/tcg-target-has.h | 8 +++-
> tcg/riscv/tcg-target.c.inc | 13 +++--
> 2 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --g
On Fri, Jan 3, 2025 at 4:28 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> host/include/riscv/host/cpuinfo.h | 5 +++--
> util/cpuinfo-riscv.c | 18 --
> 2 files changed, 19 insertions(+), 4 deletions
On Tue, Dec 17, 2024 at 6:46 PM Chao Liu wrote:
>
> fix:
> https://lore.kernel.org/all/20240322085319.1758843-8-alistair.fran...@wdc.com/
Can you include a commit message of what this fixes?
Instead of linking to the pull request there should be a fixes tag
here, like this
Fixes: df4252b2ecaf
On Tue, Dec 31, 2024 at 1:28 PM wrote:
>
> From: Frank Chang
>
> Zicfilp extension introduces the MNPELP (bit 9) in mnstatus.
> The MNPELP field holds the previous ELP.
>
> When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set
> to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741)
* mn
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h | 7
target/riscv/cpu_bits.h | 11 ++
target
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
From: Frank Chang
Zicfilp extension introduces the MNPELP (bit 9) in mnstatus.
The MNPELP field holds the previous ELP.
When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set
to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the
value y, then ELP is set to the value of MNP
From: Tommy Wu
This adds the properties for ISA extension Smrnmi.
Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set
mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all
interrupts will be disabled. Since our current OpenSBI does not
support Smrnmi yet, let's disabl
On Mon, Jan 6, 2025 at 12:15 PM Alistair Francis
wrote:
> On Tue, Dec 31, 2024 at 1:28 PM wrote:
> >
> > From: Tommy Wu
> >
> > This adds the properties for ISA extension Smrnmi.
> >
> > Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set
> > mnstatus.NMIE to 1 before enabling a
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/
From: Tommy Wu
Because the RNMI interrupt trap handler address is implementation defined.
We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property
of the harts. It’s very easy for users to set the address based on their
expectation. This patch also adds the functionality to
On 4/1/25 01:12, BALATON Zoltan wrote:
On Sat, 4 Jan 2025, Philippe Mathieu-Daudé wrote:
While I was very enthusiast when Avocado was presented to
I think 'enthusiastic' would be correct here.
Oh OK, thanks.
Regards,
BALATON Zoltan
the QEMU community and pushed forward to have it integr
While I was very enthusiastic when Avocado was presented to
the QEMU community and pushed forward to have it integrated,
time passed and I lost interest. Be honest, remove my R: tag
to not give fake expectation I'd review patches related to
Avocado anymore.
Signed-off-by: Philippe Mathieu-Daudé
-
On 4/1/25 08:52, Akihiko Odaki wrote:
The renamed state will not only represent powering state of PFs, but
also represent SR-IOV VF enablement in the future.
Signed-off-by: Akihiko Odaki
---
include/hw/pci/pci.h| 7 ++-
include/hw/pci/pci_device.h | 2 +-
hw/pci/pci.c
On Sat, Jan 4, 2025 at 3:50 PM Akihiko Odaki wrote:
>
> Some features are not always available, and virtio-net used to disable
> them when not available even if the corresponding properties were
> explicitly set to "on".
>
> Convert feature properties to OnOffAuto so that the user can explicitly
>
On 4/1/25 08:52, Akihiko Odaki wrote:
vfio_pci_size_rom() distinguishes whether rombar is explicitly set to 1
by checking dev->opts, bypassing the QOM property infrastructure.
Use -1 as the default value for rombar to tell if the user explicitly
set it to 1. The property is also converted from u
Recently, when I was writing a RISCV test, I found that when VL is set to 0, the
instruction should be nop, but when I tested it, I found that QEMU will treat
all elements as tail elements, and in the case of VTA=1, write all elements
to 1.
After troubleshooting, it was found that the vext_vx_rm_1
Some vector instructions are special, such as the vlm.v instruction,
where setting its vl actually sets evl = (vl + 7) >> 3. To improve
maintainability, we will uniformly use VSTART_CHECK_EARLY_EXIT() to
check for the condition vstart >= vl. This function will also handle
cases involving evl.
Fixe
Hi, all:
In accordance with the review, i improved the commit message of patch and added
the reason for the modification.
There was no change in the patch content.
PATCH v2 review:
https://lore.kernel.org/qemu-devel/61e8f7d8-607a-4d63-b9dd-cfbfc8407...@ventanamicro.com/
PATCH v1 review:
https:/
On Wed, Dec 18, 2024 at 9:42 PM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> In this version the errors with 'bios-tables-test' qtest are fixed in
> each patch that ended up breaking it. The test will break every time
> we're changing the default riscv,isa DT from the 'rv64' CPU.
>
> This doesn't ha
On Fri, Dec 20, 2024 at 3:49 AM Daniel Henrique Barboza
wrote:
>
> Do a cosmetic change in riscv_raise_exception() to change 'exception'
> type from uint32_t to RISCVException, making it a bit clear that the
> arg is directly correlated to the RISCVException enum.
>
> As a side effect, change 'exc
On Fri, Dec 20, 2024 at 3:48 AM Daniel Henrique Barboza
wrote:
>
> When using system mode we can get the CPU traps being taken via the
> 'riscv_trap' trace or the "-d int" qemu log. User mode does not a way of
> logging/showing exceptions to users.
>
> Add a trace in riscv_raise_exception() to all
On Tue, Dec 17, 2024 at 6:57 PM wrote:
>
> From: Alexey Baturo
>
> Signed-off-by: Alexey Baturo
> Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h| 5 +++
> target/riscv/cpu_helper.c | 78 +++
On Fri, Dec 20, 2024 at 3:47 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> Let's add trace capabilities in riscv_raise_exception() to allow users
> of qemu-riscv(32/64) to have a little more information when a SIGILL
> occurs. This is done in patch 2.
>
> Patch 1 is a "look and feel" patch that I
On Tue, Dec 17, 2024 at 6:57 PM wrote:
>
> From: Alexey Baturo
>
> Hi,
>
> Rebased and addressed Alistair's comments on code style.
>
> Thanks
>
> [v13]:
> Rebased and addressed Daniel's comments about the return type of the helper.
>
> Thanks
>
> [v12]:
> Rebased and addressed Richard's comments
On Mon, Jan 6, 2025 at 9:45 AM Alistair Francis
wrote:
> On Tue, Dec 31, 2024 at 1:28 PM wrote:
> >
> > From: Tommy Wu
> >
> > Because the RNMI interrupt trap handler address is implementation
> defined.
> > We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the
> property
> > of
On Tue, Dec 31, 2024 at 1:28 PM wrote:
>
> From: Tommy Wu
>
> This adds the properties for ISA extension Smrnmi.
>
> Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set
> mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all
> interrupts will be disabled. Since our cur
On Tue, Dec 31, 2024 at 1:28 PM wrote:
>
> From: Tommy Wu
>
> This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
> instruction that uses the values in `mnepc` and `mnstatus` to return to the
> program counter, privilege mode, and virtualization mode of the
> interrupted context.
On Tue, Dec 31, 2024 at 1:28 PM wrote:
>
> From: Frank Chang
>
> This patchset added support for Smrnmi Extension in RISC-V.
>
> There are four new CSRs and one new instruction added to allow NMI to be
> resumable in RISC-V, which are:
>
> =
On Fri, Dec 6, 2024 at 1:30 PM Sam Price wrote:
>
> I needed to set the registers prior to boot up to mimic what uboot
> would do prior to loading a binary. This adds a generic option of reg
> to the loader command, it uses the existing gcc commands for setting
> register values.
>
> I'm sorry I
I didn't mean to change all of the submodules.
I was somewhat porting from xilinx-qemu over to the main line, and
messed up the commit on that.
Ill get my gitlab branch fixed up on the next commit.
I am horrible at this email part.
I could malloc memory and push all of the register names/ values i
The similiar with IPI, physical cpu id is used for irq routing. Also
get cpu number from possible_cpu_arch_ids() and remove num-cpu
property for TYPE_LOONGARCH_EXTIOI_COMMON object.
---
v1 ... v2:
1. Move assignment for arch_id and cpu to file loongarch_extioi_common
---
Bibo Mao (3):
hw/
Since cpu number can be acquired from possible_cpu_arch_ids(),
num-cpu property is not necessary. Here remove num-cpu property
for object TYPE_LOONGARCH_EXTIOI_COMMON object.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi_common.c | 1 -
hw/loongarch/virt.c | 1 -
2 files cha
The simliar with IPI interrupt controller, physical cpu id is used
for irq routing for extioi interrupt controller.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c | 30 ++
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/hw/intc/loongarch_extioi.
Supported CPU number can be acquired from function
possible_cpu_arch_ids(), cpu-num property is not necessary.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c| 6 --
hw/intc/loongarch_extioi_common.c | 16 ++--
include/hw/intc/loongarch_extioi_comm
On Mon, Jan 6, 2025 at 2:59 PM Sam Price wrote:
>
> I didn't mean to change all of the submodules.
> I was somewhat porting from xilinx-qemu over to the main line, and
> messed up the commit on that.
> Ill get my gitlab branch fixed up on the next commit.
> I am horrible at this email part.
>
> I
Do not refer to "memory region's reference count"
-
Now MemoryRegions do have their own reference counts, but they will not
be used when their owners are not themselves. However, the documentation
of memory_region_ref() says it adds "1 to a memory re
memory_region_update_container_subregions() used to call
memory_region_ref(), which creates a reference to the owner of the
subregion, on behalf of the owner of the container. This results in a
circular reference if the subregion and container have the same owner.
memory_region_ref() creates a ref
I saw various sanitizer errors when running check-qtest-ppc64. While
I could just turn off sanitizers, I decided to tackle them this time.
Unfortunately, GLib versions older than 2.81.0 do not free test data in
some cases so some sanitizer errors remain. All sanitizer errors will be
gone with this
On 2025/01/04 21:51, BALATON Zoltan wrote:
On Sat, 4 Jan 2025, Akihiko Odaki wrote:
Do not refer to "memory region's reference count"
-
Now MemoryRegions do have their own reference counts, but they will not
be used when their owners are not thems
In function create_long_filname(), the array name[8 + 3] in
struct direntry_t is used as if it were defined as name[32].
This is intentional and works. It's nevertheless an out of
bounds array access. To avoid this problem, this patch adds a
struct lfn_direntry_t with multiple name arrays. A direct
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