[PULL v2 6/6] target/loongarch: Use auto method with LASX feature

Like LSX feature, add type OnOffAuto for LASX feature setting. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- target/loongarch/cpu.c | 50 +++ target/loongarch/cpu.h | 2 ++ target/loongarch/kvm/kvm.c | 53 ++ 3 fil

[PULL v2 1/6] target/loongarch: Fix vldi inst

From: Guo Hongyu Refer to the link below for a description of the vldi instructions: https://jia.je/unofficial-loongarch-intrinsics-guide/lsx/misc/#synopsis_88 Fixed errors in vldi instruction implementation. Signed-off-by: Guo Hongyu Tested-by: Xianglai Li Signed-off-by: Xianglai Li Reviewed

[PULL v2 0/6] loongarch-to-apply queue

The following changes since commit 38d0939b86e2eef6f6a622c6f1f7befda0146595: Merge tag 'pull-vfio-20241226' of https://github.com/legoater/qemu into staging (2024-12-26 04:38:38 -0500) are available in the Git repository at: https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarc

[PULL v2 4/6] hw/loongarch/virt: Improve fdt table creation for CPU object

For CPU object, possible_cpu_arch_ids() function is used rather than smp.cpus. With command -smp x, -device la464-loongarch-cpu, smp.cpus is not accurate for all possible CPU objects, possible_cpu_arch_ids() is used here. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- hw/loongarch/virt.c | 3

Re: [PULL 1/6] target/loongarch: Fix vldi inst

On 2024/12/27 上午1:38, Philippe Mathieu-Daudé wrote: On 26/12/24 05:22, bibo mao wrote: On 2024/12/25 下午7:32, Philippe Mathieu-Daudé wrote: Hi Bibo, On 25/12/24 03:40, Bibo Mao wrote: From: ghy <2247883...@qq.com> Is this authorship correct? Should it be: From: Guo Hongyu yes, this is

[PULL v2 2/6] target/loongarch: Use actual operand size with vbsrl check

Hardcoded 32 bytes is used for vbsrl emulation check, there is problem when options lsx=on,lasx=off is used for vbsrl.v instruction in TCG mode. It injects LASX exception rather LSX exception. Here actual operand size is used. Cc: qemu-sta...@nongnu.org Fixes: df97f338076 ("target/loongarch: Impl

[PULL v2 3/6] hw/loongarch/virt: Create fdt table on machine creation done notification

The same with ACPI table, fdt table is created on machine done notification. Some objects like CPU objects can be created with cold-plug method with command such as -smp x, -device la464-loongarch-cpu, so all objects finish to create when machine is done. Signed-off-by: Bibo Mao Reviewed-by: Bibo

[PATCH 01/17] docs/system/arm: Add Description for NPCM8XX SoC

NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals. Signed-off-by: Hao Wu --- docs/system/arm/nuvoton.rst | 20 +++- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/nuvo

[PATCH 10/17] hw/misc: Support 8-bytes memop in NPCM GCR module

The NPCM8xx GCR device can be accessed with 64-bit memory operations. This patch supports that. Signed-off-by: Hao Wu --- hw/misc/npcm_gcr.c | 94 +--- hw/misc/trace-events | 4 +- 2 files changed, 74 insertions(+), 24 deletions(-) diff --git a/hw/misc

[PATCH 00/17] Changes since v1:

1. Updated vbootrom and pc-bios 2. Split out CLK/GCR patches into refactoring and adding new features 3. Fixed a few misc items from the patches. --- NPCM8XX BMCs are the successors of the NPCM7XX BMCs. They feature quad-core ARM Cortex A35 that supports both 32 bits and 64 bits operations. This

[PATCH 16/17] hw/arm: Add NPCM8XX SoC

Signed-off-by: Hao Wu --- configs/devices/aarch64-softmmu/default.mak | 1 + hw/arm/Kconfig | 11 + hw/arm/meson.build | 1 + hw/arm/npcm8xx.c| 810 include/hw/arm/npcm8xx.h

[PATCH 05/17] hw/misc: Rename npcm7xx_gcr to npcm_gcr

NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module needs to fit both. This commit changes the name of the GCR module. Future commits will add the support for NPCM8XX GCRs. Signed-off-by: Hao Wu --- hw/misc/meson.build | 2 +- hw/misc/{npcm7xx_gcr.c => n

[PATCH 04/17] hw/ssi: Make flash size a property in NPCM7XX FIU

This allows different FIUs to have different flash sizes, useful in NPCM8XX which has multiple different sized FIU modules. Signed-off-by: Hao Wu --- hw/arm/npcm7xx.c | 6 ++ hw/ssi/npcm7xx_fiu.c | 11 +++ include/hw/ssi/npcm7xx_fiu.h | 1 + 3 files changed, 14

[PATCH 06/17] hw/misc: Move NPCM7XX GCR to NPCM GCR

A lot of NPCM7XX and NPCM8XX GCR modules share the same code, this commit moves the NPCM7XX GCR to NPCM GCR for these properties. Signed-off-by: Hao Wu --- hw/misc/npcm_gcr.c | 92 +- hw/misc/trace-events | 6 +-- include/hw/arm/npcm7xx.h | 2

[PATCH 07/17] hw/misc: Add nr_regs and cold_reset_values to NPCM GCR

These 2 values are different between NPCM7XX and NPCM8XX GCRs. So we add them to the class and assign different values to them. Signed-off-by: Hao Wu --- hw/misc/npcm_gcr.c | 24 +++- include/hw/misc/npcm_gcr.h | 13 +++-- 2 files changed, 26 insertions(+), 11

[PATCH 11/17] hw/misc: Rename npcm7xx_clk to npcm_clk

NPCM7XX and NPCM8XX have a different set of CLK registers. This commit changes the name of the clk files to be used by both NPCM7XX and NPCM8XX CLK modules. Signed-off-by: Hao Wu --- hw/misc/meson.build | 2 +- hw/misc/{npcm7xx_clk.c => npcm_clk.c} | 2 +- inclu

[PATCH 09/17] hw/misc: Store DRAM size in NPCM8XX GCR Module

NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR module. Since we don't simulate a detailed memory controller, we need to store this information directly similar to the NPCM7XX's INCTR3 register. Signed-off-by: Hao Wu --- hw/misc/npcm_gcr.c | 24 +++

[PATCH 08/17] hw/misc: Add support for NPCM8XX GCR

Signed-off-by: Hao Wu --- hw/misc/npcm_gcr.c | 131 - include/hw/misc/npcm_gcr.h | 6 +- 2 files changed, 134 insertions(+), 3 deletions(-) diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c index 295073ba14..52d0fa07ea 100644 --- a/hw/misc/npcm_gc

[PATCH 14/17] hw/misc: Support NPCM8XX CLK Module Registers

NPCM8XX adds a few new registers and have a different set of reset values to the CLK modules. This patch supports them. This patch doesn't support the new clock values generated by these registers. Currently no modules use these new clock values so they are not necessary at this point. Implementat

[PATCH 17/17] hw/arm: Add NPCM845 Evaluation board

Signed-off-by: Hao Wu --- hw/arm/meson.build | 2 +- hw/arm/npcm8xx_boards.c | 256 +++ include/hw/arm/npcm8xx.h | 20 +++ 3 files changed, 277 insertions(+), 1 deletion(-) create mode 100644 hw/arm/npcm8xx_boards.c diff --git a/hw/arm/meson.build b

[PATCH 13/17] hw/misc: Add nr_regs and cold_reset_values to NPCM CLK

These 2 values are different between NPCM7XX and NPCM8XX CLKs. So we add them to the class and assign different values to them. Signed-off-by: Hao Wu --- hw/misc/npcm_clk.c | 17 +++-- include/hw/misc/npcm_clk.h | 9 - 2 files changed, 19 insertions(+), 7 deletions(-

[PATCH 12/17] hw/misc: Move NPCM7XX CLK to NPCM CLK

A lot of NPCM7XX and NPCM8XX CLK modules share the same code, this commit moves the NPCM7XX CLK to NPCM CLK for these properties. Signed-off-by: Hao Wu --- hw/misc/npcm_clk.c | 106 + hw/misc/trace-events | 6 +-- include/hw/arm/npcm7xx.h |

[PATCH 15/17] hw/net: Add NPCM8XX PCS Module

The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII PHY. This implementation contains all the default registers and the soft reset feature that are required to load the Linux kernel driver. Further features have not been implemented yet. Signed-off-by: Hao Wu --- hw/net/meson.buil

[PATCH 03/17] pc-bios: Add NPCM8XX vBootrom

The bootrom is a minimal bootrom used to load an NPCM8XX image. The source code is located in the same repo as the NPCM7XX one: github.com/google/vbootrom/tree/master/npcm8xx. Signed-off-by: Hao Wu --- MAINTAINERS | 1 + pc-bios/README | 8 pc-bios/meson

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