On 12/18/24 05:51, Peter Maydell wrote:
On Tue, 17 Dec 2024 at 21:08, Pierrick Bouvier
wrote:
On 12/17/24 02:38, Peter Maydell wrote:
On Tue, 17 Dec 2024 at 07:40, Alex Bennée wrote:
Pierrick Bouvier writes:
I think this is still a change worth to do, because people can get a
100% speedu
On 12/18/24 11:08, Paolo Savini wrote:
This patch aims at emulating the whole register loads and stores through
direct generation of tcg operations rather than through the aid of a helper
function.
Signed-off-by: Paolo Savini
---
target/riscv/insn_trans/trans_rvv.c.inc | 104 +
Sorry but I don't quite follow. Which callbacks are we talking about?
Are you saying that it is fine to call pci_dma_read/pci_dma_write/msix_notify
from a thread without acquiring any particular lock in advance?
Thanks,
Markus
From: John Levon
Sent: Wednesday, D
On 12/17/24 19:20, Richard Henderson wrote:
On 12/17/24 14:03, Pierrick Bouvier wrote:
+__attribute__((unused))
+static bool fold_masks_zs(OptContext *ctx, TCGOp *op,
+ uint64_t z_mask, uint64_t s_mask)
+{
+ return fold_masks_zsa(ctx, op, z_mask, s_mask, -1);
+}
+
+__
From: Nabih Estefan
Create a PLX PEX PCIe Virtual Switch implementation that can be used
for modeling trays. This is a generalized version of the xio3130 switch where
we can set the PCI information on creation, allowing us to model different
trays without creating specific devices for all of them
Peter Maydell writes:
> On Fri, 6 Dec 2024 at 16:02, Alex Bennée wrote:
>>
>> When FEAT_SEL2 was implemented the SEL2 timers where missed. This
>> shows up when building the latest Hafnium with SPMC_AT_EL=2. The
>> actual implementation utilises the same logic as the rest of the
>> timers so all
On 18/12/2024 17.00, Daniel P. Berrangé wrote:
On Wed, Dec 18, 2024 at 04:51:24PM +0100, Thomas Huth wrote:
On 18/12/2024 14.51, Fabiano Rosas wrote:
Thomas Huth writes:
Now that we've got a find_free_port() function in the functional
test framework, we can convert the migration test, too.
W
On Wed, Dec 18, 2024 at 04:59:12PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Wed, 18 Dec 2024 16:59:12 +0100
> From: Philippe Mathieu-Daudé
> Subject: [PATCH 1/2] system: Move 'exec/confidential-guest-support.h' to
> system/
> X-Mailer: git-send-email 2.45.2
>
> "exec/confidential-guest-suppo
On Wed, Dec 18, 2024 at 05:14:11PM +0800, Yuan Liu wrote:
> When compression is enabled on the migration channel and
> the pages processed are all zero pages, these pages will
> not be sent and updated on the target side, resulting in
> incorrect memory data on the source and target sides.
>
> The
Itaru Kitayama writes:
(+CC Markus, Eduardo, Marcel for QMP API)
> Hi,
> I’ve been looking at the libvirt code to add Arm’s CCA support for
> some time and I am wondering how QEMU folk want to implement the CCA
> query command. Any pointer would be appreciated.
Jean-Philippe's latest posting is
Tested-by: Eric Mackay
This patch aims at emulating the whole register loads and stores through
direct generation of tcg operations rather than through the aid of a helper
function.
Signed-off-by: Paolo Savini
---
target/riscv/insn_trans/trans_rvv.c.inc | 104 +---
1 file changed, 56 insertions(+),
On Wed, Dec 18, 2024 at 06:08:01PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Wed, Dec 18, 2024 at 03:13:08PM -0300, Fabiano Rosas wrote:
> >> Peter Xu writes:
> >>
> >> > On Wed, Nov 13, 2024 at 04:46:27PM -0300, Fabiano Rosas wrote:
> >> >> diff --git a/tests/qtest/migration-test
On Wed, 2024-12-18 at 22:42 +0100, David Woodhouse wrote:
>
> It seems like it's because of the way QEMU handles shared level-
> triggered interrupts.
Yeah, this hack seems to confirm it. As I said, PCI INTx manages to
demux correctly, but any time you have non-PCI interrupt sharing, it's
hosed b
On Wed, 2024-12-18 at 16:54 +0100, Thomas Huth wrote:
> On 18/12/2024 12.48, David Woodhouse wrote:
> > On 18 December 2024 12:32:49 CET, Thomas Huth wrote:
> > > Use the serial console to execute the commands in the guest instead
> > > of using ssh since we don't have ssh support in the functiona
The following changes since commit 8032c78e556cd0baec111740a6c636863f9bd7c8:
Merge tag 'firmware-20241216-pull-request' of https://gitlab.com/kraxel/qemu
into staging (2024-12-16 14:20:33 -0500)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-t
From: Daniel Henrique Barboza
MSIx support is added in the RISC-V IOMMU platform device by including
the required MSIx facilities to alow software to properly setup the MSIx
subsystem.
We took inspiration of what is being done in the riscv-iommu-pci device,
mainly msix_init() and msix_notify(),
From: Daniel Henrique Barboza
Interrupt Generation Support (IGS) is a capability that is tied to the
interrupt deliver mechanism, not with the core IOMMU emulation. We
should allow device implementations to set IGS as they wish.
A new helper is added to make it easier for device impls to set IGS
From: Daniel Henrique Barboza
Move all the static initializion of the device to an init() function,
leaving only the dynamic initialization to be done during realize.
With this change s->cap is initialized with RISCV_IOMMU_CAP_DBG during
init(), and realize() will increment s->cap with the extra
From: Daniel Henrique Barboza
The current logic to determine if we don't need an emulated APLIC
controller, i.e. KVM will provide for us, is to determine if we're
running KVM, with in-kernel irqchip support, and running
aia=aplic-imsic. This is modelled by riscv_is_kvm_aia_aplic_imsic() and
virt_
From: Sia Jee Heng
Signed-off-by: Sia Jee Heng
Reviewed-by: Sunil V L
Acked-by: Alistair Francis
Message-ID: <20241028015744.624943-2-jeeheng@starfivetech.com>
Signed-off-by: Alistair Francis
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --gi
From: Daniel Henrique Barboza
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20241106133407.604587-8-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
docs/specs/riscv-iommu.rst | 30 +++---
docs/system/riscv/virt.rst | 1
From: Daniel Henrique Barboza
In create_fdt_sockets() we have the following pattern:
if (kvm_enabled() && virt_use_kvm_aia(s)) {
(... do stuff ...)
} else {
(... do other stuff ...)
}
if (kvm_enabled() && virt_use_kvm_aia(s)) {
(... do more stuff ...)
On Wed, Dec 18, 2024 at 05:50:52PM +, Daniel P. Berrangé wrote:
> On Wed, Dec 18, 2024 at 09:49:39AM -0600, Michael Roth wrote:
> > The GHCB specification[1] defines a VMGEXIT-based Guest Request
> > hypercall to allow an SNP guest to issue encrypted requests directly to
> > SNP firmware to do
From: Daniel Henrique Barboza
The last step to enable KVM AIA aplic-imsic with irqchip in split mode
is to deal with how MSIs are going to be sent. In our current design we
don't allow an APLIC controller to send MSIs unless it's on m-mode. And
we also do not allow Supervisor MSI address configur
From: Daniel Henrique Barboza
Before adding support to kernel-irqchip=split when using KVM AIA we need
to change how we create the in-kernel AIA device.
In the use case we have so far, i.e. in-kernel irqchip without split
mode, both the s-mode APLIC and IMSIC controllers are provided by the
irqc
From: Anton Blanchard
Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to
8 wide RV64 cores. More details can be found at
https://tenstorrent.com/ip/tt-ascalon
Signed-off-by: Anton Blanchard
Acked-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-ID: <202411
From: Yong-Xuan Wang
In the section "4.7 Precise effects on interrupt-pending bits"
of the RISC-V AIA specification defines that:
"If the source mode is Level1 or Level0 and the interrupt domain
is configured in MSI delivery mode (domaincfg.DM = 1):
The pending bit is cleared whenever the rectif
On Wed, Dec 18, 2024 at 06:32:05PM +0100, Markus Armbruster wrote:
> Michael Roth writes:
>
> > The GHCB specification[1] defines a VMGEXIT-based Guest Request
> > hypercall to allow an SNP guest to issue encrypted requests directly to
> > SNP firmware to do things like query the attestation repo
From: Sia Jee Heng
Update the SPCR table to accommodate the SPCR Table revision 4 [1].
The SPCR table has been modified to adhere to the revision 4 format [2].
[1]:
https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
[2]: https://github.com/
From: Daniel Henrique Barboza
Add a riscv_iommu_reset() helper in the base emulation code that
implements the expected reset behavior as defined by the riscv-iommu
spec.
Devices can then use this helper in their own reset callbacks.
Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Fra
From: Jim Shu
Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.
Signed-off-by: Jim Shu
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-ID: <202411
From: Daniel Henrique Barboza
Similar to the riscv_is_kvm_aia_aplic_imsic() helper from riscv_aplic.c,
the existing virt_use_kvm_aia() is testing for KVM aia=aplic-imsic with
in-kernel irqchip enabled. It is not checking for a generic AIA support.
Rename the helper to virt_use_kvm_aia_aplic_imsi
From: "Fea.Wang"
Follow the Svukte spec, do the memory access address checking
1. Include instruction fetches or explicit memory accesses
2. System run in effective privilege U or VU
3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
instruction is HLV, HLVX, HSV and execute from U
From: Sunil V L
Add a new machine option called 'iommu-sys' that enables a
riscv-iommu-sys platform device for the 'virt' machine. The option is
default 'off'.
The device will use IRQs 36 to 39.
We will not support both riscv-iommu-sys and riscv-iommu-pci devices in
the same board in this first
From: "Fea.Wang"
Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be
supported when the svukte extension is enabled.
When senvcfg[UKTE] bit is set, the memory access from U-mode should do
the svukte check only except HLV/HLVX/HSV H-mode instructions which
depend on hstatus[HUKT
From: Sia Jee Heng
Update the virt SPCR golden reference file for RISC-V to accommodate the
SPCR Table revision 4 [1], utilizing the iasl binary compiled from the
latest ACPICA repository. The SPCR table has been modified to
adhere to the revision 4 format [2].
[1]:
https://learn.microsoft.com/
From: Tomasz Jeznach
This device models the RISC-V IOMMU as a sysbus device. The same design
decisions taken in the riscv-iommu-pci device were kept, namely the
existence of 4 vectors are available for each interrupt cause.
The WSIs are emitted using the input of the s->notify() callback as a
in
From: Sai Pavan Boddu
Add a basic board with interrupt controller (intc), timer, serial
(uartlite), small memory called LMB@0 (128kB) and DDR@0x8000
(configured via command line eg. -m 2g).
This is basic configuration which matches HW generated out of AMD Vivado
(design tools). But initial co
From: Daniel Henrique Barboza
Also add a new page, docs/specs/riscv-aia.rst, where we're documenting
the state of AIA support in QEMU w.r.t the controllers being emulated or
not depending on the AIA and accelerator settings.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
From: Jim Shu
DTB is placed to the end of memory, so we will check if the start
address of DTB overlaps to the address of kernel/initrd.
Signed-off-by: Jim Shu
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20241120153935.24706-4-jim@sifive.com>
Signed-off
From: Philippe Mathieu-Daudé
Looking at htif_mm_ops[] read/write handlers, we notice they
expect 32-bit values to accumulate into to the 'fromhost' and
'tohost' 64-bit variables. Explicit by setting the .impl
min/max fields.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Revi
From: Philippe Mathieu-Daudé
Rather than relying on implicit includes, explicit them,
in order to avoid when refactoring unrelated headers:
target/riscv/vector_internals.h:36:12: error: call to undeclared function
'FIELD_EX32'; ISO C99 and later do not support implicit function declarations
From: MollyChen
Add a CPU entry for the RV64 XiangShan NANHU CPU which
supports single-core and dual-core configurations. More
details can be found at
https://docs.xiangshan.cc/zh-cn/latest/integration/overview
Signed-off-by: MollyChen
Acked-by: Alistair Francis
Reviewed-by: Daniel Henrique Ba
From: "Fea.Wang"
Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written
value will be masked when the svukte extension is not enabled.
When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should
do svukte check.
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
Reviewed
From: "Fea.Wang"
Add "svukte" in the ISA string when svukte extension is enabled.
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
Reviewed-by: Jim Shu
Reviewed-by: Alistair Francis
Message-ID: <20241203034932.25185-6-fea.w...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/cp
From: Daniel Henrique Barboza
Remove the 'irqchip_split()' restriction in kvm_arch_init() now that
we have support for "-accel kvm,kernel-irqchip=split".
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20241119191706.718860-8-dbarb...@ventanamicro.com>
Signed-
From: Daniel Henrique Barboza
The helper is_kvm_aia() is checking not only for AIA, but for
aplic-imsic (i.e. "aia=aplic-imsic" in 'virt' RISC-V machine) with an
in-kernel chip present.
Rename it to be a bit clear what the helper is doing since we'll add
more AIA helpers in the next patches.
Ma
From: Philippe Mathieu-Daudé
Since our RISC-V system emulation is only built for little
endian, the HTIF device aims to interface with little endian
memory accesses, thus we can explicit htif_mm_ops:endianness
being DEVICE_LITTLE_ENDIAN.
In that case tswap64() is equivalent to le64_to_cpu(), as
From: Philippe Mathieu-Daudé
Rather than relying on implicit includes, explicit them,
in order to avoid when refactoring unrelated headers:
target/riscv/internals.h:49:15: error: use of undeclared identifier 'PRV_S'
49 | ret = PRV_S;
| ^
target/riscv/intern
From: Philippe Mathieu-Daudé
The HTIF interface is RISC-V specific, add
it within the MAINTAINERS section covering
hw/riscv/.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20241129154304.34946-2-phi...@linaro.org>
Signed-
From: "Fea.Wang"
Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564
Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's addr
From: Daniel Henrique Barboza
Commit 68c9e54bea handled a situation where a warning was being shown
when using the 'sifive_e' cpu when disabling the named extension zic64b.
It makes little sense to show user warnings for named extensions that
users can't control, and the solution taken was to dis
From: Jason Chien
>From RISCV IOMMU spec section 2.1.3:
When SXL is 1, the following rules apply:
- If the first-stage is not Bare, then a page fault corresponding to the
original access type occurs if the IOVA has bits beyond bit 31 set to 1.
- If the second-stage is not Bare, then a guest page
From: Jim Shu
Add a new struct RISCVBootInfo to sync boot information between multiple
boot functions.
Signed-off-by: Jim Shu
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20241120153935.24706-3-jim@sifive.com>
Signed-off-by: Alistair Francis
---
includ
From: Daniel Henrique Barboza
ssstateen is defined in RVA22 as:
"Supervisor-mode view of the state-enable extension. The supervisor-mode
(sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers
must be provided."
Add ssstateen as a named feature that is available if we also have
s
On 12/17/24 16:43, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
contrib/plugins/hotblocks.c | 29 -
1 file changed, 24 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r~
diff --git a/contrib/plugins/hotblocks.c b/contrib/plugins/h
From: Helge Deller
Fixes those warnings:
Unsupported host ancillary data: 0/8
Signed-off-by: Helge Deller
---
linux-user/syscall.c | 12
1 file changed, 12 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 494323efba..bbe2560927 100644
--- a/linux-user
From: Helge Deller
This fixes the following qemu warnings when building debian gupnp package:
Unknown host QEMU_IFLA type: 61
Unknown host QEMU_IFLA type: 58
Unknown host QEMU_IFLA type: 59
Unknown host QEMU_IFLA type: 60
Unknown host QEMU_IFLA type: 32820
QEMU_IFLA type 32820 is actually N
Hi Peter, can we upgrade your Acked-by to an RB? You gave RB to the
similar patch "hostmem-shm: preserve for cpr"
- Steve
On 12/2/2024 8:19 AM, Steve Sistare wrote:
Preserve memory-backend-memfd memory objects during cpr-transfer.
Signed-off-by: Steve Sistare
Acked-by: Peter Xu
---
backen
From: Helge Deller
The following changes since commit 791e3837c1105aec4e328674aad32e34056957e2:
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging
(2024-11-25 10:44:11 +)
are available in the Git repository at:
https://github.com/hdeller/qemu-hppa.git
tags/
From: Helge Deller
Fixes this warning:
Unknown host IFA type: 11
Signed-off-by: Helge Deller
---
linux-user/fd-trans.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-user/fd-trans.c b/linux-user/fd-trans.c
index c04a97c73a..6191e3115b 100644
--- a/linux-user/fd-trans.c
+++ b/linux-
From: Helge Deller
Fixes various warnings in the testsuite while building gupnp:
gssdp-net-DEBUG: Failed to send netlink message: Operation not supported
gupnp-context-DEBUG: Mismatch between host header and host IP (example.com,
expected: 127.0.0.1)
gupnp-context-DEBUG: Mismatch between host
From: Helge Deller
Avoid using the same error message for two different code paths
as it complicates determining the one which actually triggered.
Signed-off-by: Helge Deller
---
linux-user/syscall.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/syscall.c b
From: Helge Deller
Share code with IP_ADD_MEMBERSHIP/IP_DROP_MEMBERSHIP.
Signed-off-by: Helge Deller
---
linux-user/syscall.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index bbe2560927..4360543e20 100644
--- a
On 18 December 2024 18:16:13 CET, Thomas Huth wrote:
>On 18/12/2024 17.19, Thomas Huth wrote:
>> On 18/12/2024 15.11, David Woodhouse wrote:
>>> On Wed, 2024-12-18 at 14:38 +0100, Thomas Huth wrote:
>> ...
But FWIW, there seems to be another issue with this test. While running it
multipl
在 2024/12/19 02:22, Naresh Kamboju 写道:
On Wed, 18 Dec 2024 at 17:33, Naresh Kamboju wrote:
The following kernel crash noticed on qemu-arm64 while running the
Linux next-20241210 tag (to next-20241218) kernel built with
- CONFIG_ARM64_64K_PAGES=y
- CONFIG_ARM64_16K_PAGES=y
and running
On 12/18/24 09:12, Philippe Mathieu-Daudé wrote:
CONFIG_DEVICES is not generated on user emulation, so
do not define it.
Signed-off-by: Philippe Mathieu-Daudé
---
meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 85f74854735..d2
On Wed, Dec 18, 2024 at 09:22:26PM +0530, Naresh Kamboju wrote:
> On Wed, 18 Dec 2024 at 17:33, Naresh Kamboju
> wrote:
> >
> > The following kernel crash noticed on qemu-arm64 while running the
> > Linux next-20241210 tag (to next-20241218) kernel built with
> &g
As we are about to add more physical and virtual timers lets make it
clear what each timer does.
Signed-off-by: Alex Bennée
Reviewed-by: Peter Maydell
Cc: qemu-sta...@nongnu.org
---
target/arm/gtimer.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/arm/gti
Follow Peter's review I've split this into a several patches as there
are some other fixes that should be made to other EL2 times that
shouldn't be rolled together.
v2
- split machine enabling into patches
- rename IRQ
- use CP_ACCESS_TRAP_UNCATEGORIZED for UNDEF cases
v1
- improve GTIMER
We were missing this case and will shortly be adding another.
Re-arrange the code and use a switch statement to group the virtual
timers.
Signed-off-by: Alex Bennée
Cc: qemu-sta...@nongnu.org
---
target/arm/helper.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
di
Signed-off-by: Alex Bennée
Cc: qemu-sta...@nongnu.org
---
hw/arm/virt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 333eaf67ea..5e3589dc6a 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -873,6 +873,8 @@ static void create_gic(VirtMachineState *vms,
When FEAT_SEL2 was implemented the SEL2 timers where missed. This
shows up when building the latest Hafnium with SPMC_AT_EL=2. The
actual implementation utilises the same logic as the rest of the
timers so all we need to do is:
- define the timers and their access functions
- conditionally add
Peter Xu writes:
> On Wed, Nov 13, 2024 at 04:46:27PM -0300, Fabiano Rosas wrote:
>> diff --git a/tests/qtest/migration-test-smoke.c
>> b/tests/qtest/migration-test-smoke.c
>> new file mode 100644
>> index 00..ff2d72881f
>> --- /dev/null
>> +++ b/tests/qtest/migration-test-smoke.c
>> @@
Signed-off-by: Alex Bennée
Cc: qemu-sta...@nongnu.org
---
hw/arm/sbsa-ref.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index e3195d5449..c02344004e 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -484,6 +484,8 @@ static void create_gic(SB
Convert HPTE_DIRTY() macro as hpte_is_dirty() method.
Since sPAPR is in big endian configuration at reset,
use the big endian LD/ST API to access the HPTEs.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/spapr.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/h
Convert HPTE() macro as hpte_get() method.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/spapr.c | 38 ++
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 3b022e8da9e..4845bf3244b 100644
--- a/hw/ppc/spap
Convert HPTE_VALID() macro as hpte_is_valid() method.
Since sPAPR is in big endian configuration at reset,
use the big endian LD/ST API to access the hash PTEs.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/spapr.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --g
When running Clang static analyzer on macOS I'm getting:
include/qemu/osdep.h:634:8: error: redefinition of 'iovec'
634 | struct iovec {
|^
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/usr/include/sys/_types/_iovec_t.h:31:8:
note: previous definition is here
3
Convert CLEAN_HPTE() macro as hpte_set_clean() method.
Since sPAPR is in big endian configuration at reset,
use the big endian LD/ST API to access the HPTEs.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/spapr.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --gi
Convert DIRTY_HPTE() macro as hpte_set_dirty() method.
Since sPAPR is in big endian configuration at reset,
use the big endian LD/ST API to access the HPTEs.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/spapr.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/pp
The ePAPR magic value in $r6 doesn't need to be byte swapped.
See ePAPR-v1.1.pdf chapter 5.4.1 "Boot CPU Initial Register State"
and the following mailing-list thread:
https://lore.kernel.org/qemu-devel/cafeaca_nr4xw5dnl4nq7vnh4xrh5uwbhqcxulykqyk6_fcb...@mail.gmail.com/
Signed-off-by: Philippe Ma
Remove the tswap() calls on ePAPR, and convert
them to big-endian LD/ST API on sPAPR.
Build-tested only.
Philippe Mathieu-Daudé (7):
meson: Run some compiler checks using -Wno-unused-value
hw/ppc/spapr: Convert HPTE() macro as hpte_get() method
hw/ppc/spapr: Convert HPTE_VALID() macro as hp
On 12/18/24 01:27, Alex Bennée wrote:
Pierrick Bouvier writes:
On 12/17/24 02:38, Peter Maydell wrote:
On Tue, 17 Dec 2024 at 07:40, Alex Bennée wrote:
Pierrick Bouvier writes:
On 12/16/24 11:50, Richard Henderson wrote:
On 12/16/24 13:26, Pierrick Bouvier wrote:
On 12/16/24 11:10, Ri
On Wed, 2024-12-18 at 17:19 +0100, Thomas Huth wrote:
> On 18/12/2024 15.11, David Woodhouse wrote:
> > On Wed, 2024-12-18 at 14:38 +0100, Thomas Huth wrote:
> ...
> > > But FWIW, there seems to be another issue with this test. While running it
> > > multiple times, I sometimes see test_kvm_xen_gue
On 12/12/24 18:21, Paolo Bonzini wrote:
The bits in the LineControl struct were backwards. :(
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/lib.rs | 82 +--
1 file changed, 41 insertions(+), 41 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 12/12/24 18:22, Paolo Bonzini wrote:
Use ==/!= instead of going through bool and xor.
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 6 ++
rust/hw/char/pl011/src/lib.rs| 6 --
2 files changed, 2 insertions(+), 10 deletions(-)
Reviewed-by: Philippe Mathi
Add support of VHOST_USER_PROTOCOL_F_DEVICE_STATE in virtio-net
with vhost-user backend.
Cc: Hanna Czenczek
Signed-off-by: Laurent Vivier
---
hw/net/virtio-net.c | 135
1 file changed, 112 insertions(+), 23 deletions(-)
diff --git a/hw/net/virtio-ne
On Wed, 18 Dec 2024 at 12:31, Marcin Juszkiewicz
wrote:
>
> I am ending my time with Linaro and do not have plans to continue
> working on SBSA Reference Platform anymore.
Thank you very much for all your contributions to this platform over the years.
> Signed-off-by: Marcin Juszkiewicz
Review
On 12/12/24 18:22, Paolo Bonzini wrote:
The Data struct is wrong, and does not show how bits 8-15 of DR
are the receive status. Fix it, and use it to fix break
errors ("c >> 8" in the C code does not translate to
"c.to_be_bytes()[3]").
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/
LGTM, still happily deferring to Alex =)
On 12/12/24 18:22, Paolo Bonzini wrote:
The Rust vmstate macros lack the type-safety of their C equivalents (so
safe, much abstraction), and therefore they were predictably wrong.
The registers have already been changed to 32-bits in the previous patch,
On Wed, Dec 18, 2024 at 08:32:59AM +0100, Paolo Bonzini wrote:
> Date: Wed, 18 Dec 2024 08:32:59 +0100
> From: Paolo Bonzini
> Subject: Re: [PATCH 26/26] rust: callbacks: allow passing optional
> callbacks as ()
>
> Il mer 18 dic 2024, 07:50 Zhao Liu ha scritto:
>
> > Am I using the wrong term
Calling `vext_continuous_ldst_tlb` for load/stores up to 6 bytes
significantly improves performance.
Co-authored-by: Helene CHELIN
Co-authored-by: Paolo Savini
Co-authored-by: Craig Blackmore
Signed-off-by: Helene CHELIN
Signed-off-by: Paolo Savini
Signed-off-by: Craig Blackmore
---
target
Replace `continus` with `continuous`.
Signed-off-by: Craig Blackmore
---
target/riscv/vector_helper.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a85dd1d200..0f57e48cc5 100644
--- a/target/riscv/
There were no comments on the RFC so reposting as a final patch.
Changes since v5:
- Removed RFC
Changes since v4:
- Split into a seperate submission to simplify review
- Use load/store atomic functions as suggested by Richard Henderson
- Do 8, 4, 2 byte atomic ldst for sizes smaller than 16 byte
On Mon, Dec 09, 2024 at 01:37:15PM +0100, Paolo Bonzini wrote:
> Date: Mon, 9 Dec 2024 13:37:15 +0100
> From: Paolo Bonzini
> Subject: [PATCH 24/26] rust: qom: move device_id to PL011 class side
> X-Mailer: git-send-email 2.47.1
>
> There is no need to monkeypatch DeviceId::Luminary into the
>
Use atomic load/store functions to access multiple elements from host.
Co-authored-by: Paolo Savini
Signed-off-by: Paolo Savini
Signed-off-by: Craig Blackmore
---
target/riscv/trace-events| 12 +
target/riscv/vector_helper.c | 95 +---
2 files changed,
On Wed, Dec 18, 2024 at 11:26:35AM +0100, Paolo Bonzini wrote:
> Date: Wed, 18 Dec 2024 11:26:35 +0100
> From: Paolo Bonzini
> Subject: Re: [PATCH 24/26] rust: qom: move device_id to PL011 class side
>
> On 12/18/24 08:14, Paolo Bonzini wrote:
> > Moving on to another topic, about the gap (or
On Thu Dec 19, 2024 at 5:18 AM AEST, BALATON Zoltan wrote:
> On Wed, 18 Dec 2024, Philippe Mathieu-Daudé wrote:
> > The ePAPR magic value in $r6 doesn't need to be byte swapped.
> >
> > See ePAPR-v1.1.pdf chapter 5.4.1 "Boot CPU Initial Register State"
> > and the following mailing-list thread:
> >
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