On Fri, 2024-12-13 at 10:04 +0100, Mario Fleischmann wrote:
> Hi,
>
> apologies for the delayed review; I've just gotten to it now.
>
> On 06.12.2024 01:14, Yanfeng Liu wrote:
> > This adds virtualization mode (V bit) as bit(2) of register `priv`
> > per RiscV debug spec v1.0.0-rc3. Checked with
On 13/12/24 20:16, Philippe Mathieu-Daudé wrote:
On 9/12/24 19:12, Brian Cain wrote:
Mea culpa, I don't know how I got this wrong in 2dfe93699c. Still
getting used to the new address, I suppose. Somehow I got it right in
the
mailmap, though.
Signed-off-by: Brian Cain
---
MAINTAINERS | 2
On 13/12/24 14:33, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (7):
hw/nvram/fw_cfg: Rename fw_cfg_add_[file]_from_generator()
hw/nvram/fw_cfg: Pass QOM parent to fw_cfg_add_file_from_generator()
hw/nvram/fw_cfg: Skip FW_CFG_DATA_GENERATOR when no data to generate
hw/pci: Ha
On 12/10/24 3:58 AM, David Hildenbrand wrote:
> Maybe there is a reason s390x needs to handle this using
> memory_region_notify_iommu() callbacks instead of doing it similar to "struct
> vfio_memory_listener" when registered on &address_space_memory without a
> viommu.
>
Hi David,
I think I
Some of the info I was asked for in V1 of the patch:
I'm seeing the failure on 2 different machines, the compiler versions are:
- gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)
- gcc version 14.2.0 (Debian 14.2.0-3+build3)
Both of the outputs below are run on the Debian machine.
Output of the
On Fri, Nov 08, 2024 at 12:52:37PM +, Shameer Kolothum via wrote:
> Hi,
>
> This series adds initial support for a user-creatable "arm-smmuv3-nested"
> device to Qemu. At present the Qemu ARM SMMUv3 emulation is per machine
> and cannot support multiple SMMUv3s.
>
> In order to support vfio-p
On Fri, Nov 22, 2024 at 05:38:54PM +, Shameerali Kolothum Thodi via wrote:
>
>
> > -Original Message-
> > From: Nathan Chen
> > Sent: Friday, November 22, 2024 1:42 AM
> > To: Shameerali Kolothum Thodi
> > Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org;
> > eric.au...@redhat.com; pe
Hi Jean,
On 11/26/24 5:56 AM, Jean-Philippe Brucker wrote:
When RME is enabled, the upper GPA bit is used to distinguish protected
from unprotected addresses. Reserve it when setting up the guest memory
map.
Signed-off-by: Jean-Philippe Brucker
---
hw/arm/virt.c | 14 --
1 file
On Fri, Dec 06, 2024 at 08:11:24PM +0100, Philippe Mathieu-Daudé wrote:
> We maintain one hpet_cfg[] state for all HPET instances.
> Move it to a new HPET class.
It is a conceptually rather wierd having state stored in a
class rather than an instance.
I don't know what hpet_cfg is used for though
On 12/12/2024 16.02, Daniel P. Berrangé wrote:
On Thu, Dec 12, 2024 at 03:14:53PM +0100, Thomas Huth wrote:
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
If downloading of assets has been disabled, then skip running a
test if the assets it has registered are not already downloaded.
Signed-off
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
We see periodic errors caching assets due to a combination of transient
networking and server problems. With the previous patch to skip running
a test when it has missing assets, we can now treat most cache download
errors as non-fatal.
Only HTTP 40
On 12/12/2024 15.42, Matthew Rosato wrote:
On 12/12/24 4:10 AM, Thomas Huth wrote:
On 09/12/2024 20.29, Matthew Rosato wrote:
This series introduces the concept of the relaxed translation requirement
for s390x guests in order to allow bypass of the guest IOMMU for more
efficient PCI passthrough
> > In this commit, this comment is a bit ahead, but I think it's okay.
> >
> > qom and qdev are both good names. In addition, we can rename the files
> > of PL011 as well. Perhaps device_class.rs could be merged into device.rs
> > (and eventually renamed to pl011.rs). I guess you might be plannin
This assertion always happens when we sanitize the CXL memory device.
$ echo 1 > /sys/bus/cxl/devices/mem0/security/sanitize
It is incorrect to register an MSIX number beyond the device's capability.
Expand the device's MSIX number and use the enum to maintain the *USED*
and MAX MSIX number
Fixe
> Which QEMU machine are you using ?
ast2600-evb
Thanks,
Kenneth
-邮件原件-
发件人: Cédric Le Goater
发送时间: 2024年12月13日 17:57
收件人: Kenneth Jia(贾纪东_华硕上海) ; 'qemu-...@nongnu.org'
抄送: 'Cédric Le Goater' ; 'Philippe Mathieu-Daudé'
; 'Jamin Lin' ; 'Andrew Jeffery'
; 'Gavin Shan' ; 'open lis
On 12/12/24 14:31, Kenneth Jia(贾纪东_华硕上海) wrote:
From 24d3badbbb9dcc0d220609a7dd30f8da5002cba7 Mon Sep 17 00:00:00 2001
From: Kenneth Jia
Date: Thu, 12 Dec 2024 20:42:04 +0800
Subject: [PATCH] hw/arm/aspeed: fix connect_serial_hds_to_uarts
In the loop, we need ignore the index increas
By the way, this kind of an implicit dependency in VMState between devices
is really hard to manage, there should be a way to specify it in code somehow..
vmstate has a MigrationPriority field to order loading between
devices. Maybe we could extend but I think it is better to handle
ordering at
On 12/12/24 19:53, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (18):
exec: Introduce 'user/guest-host.h' header
linux-user/aarch64: Include missing 'user/abitypes.h' header
include: Include missing 'qemu/clang-tsa.h' header
accel/tcg: Declare mmap_[un]lock() in 'exec/page-pr
On 6/12/24 19:13, Philippe Mathieu-Daudé wrote:
In order to keep fw_cfg device model clean, remove the PCI
bus specific code. Instead, the equivalent functionality is
implemented within the PCI_BUS object in hw/pci/,
implementing TYPE_FW_CFG_DATA_GENERATOR_INTERFACE.
Philippe Mathieu-Daudé (6):
On 6/12/24 20:11, Philippe Mathieu-Daudé wrote:
No need to have an external hpet_cfg[] array accessed
outside of hpet.c. Move it in the class state.
Philippe Mathieu-Daudé (4):
hw/timer/hpet: Introduce hpet_add_fw_cfg_bytes()
hw/timer/hpet: Reduce hpet_cfg[] scope
hw/timer/hpet: Have hp
On Fri, Dec 06, 2024 at 07:13:47PM +0100, Philippe Mathieu-Daudé wrote:
> fw_cfg_add_from_generator() is adding a 'file' entry,
> so rename as fw_cfg_add_file_from_generator() for
> clarity. Besides, we might introduce generators for
> other entry types.
>
> Signed-off-by: Philippe Mathieu-Daudé
Il ven 13 dic 2024, 10:01 Zhao Liu ha scritto:
> I found vmstate_array_of_pointer_to_struct missed a `info` field, and I
> could submit a patch to fix this nit next week (along with other cleanup
> you and other miantainers suggested for HPET).
>
I wouldn't worry too much about VMState, it's not
On Fri, Dec 06, 2024 at 07:13:48PM +0100, Philippe Mathieu-Daudé wrote:
> Currently fw_cfg_add_file_from_generator() is restricted
> to command line created objects which reside in the
> '/objects' QOM container. In order to extend to other
> types of containers, pass the QOM parent by argument.
>
On Fri, Dec 06, 2024 at 07:13:49PM +0100, Philippe Mathieu-Daudé wrote:
> The FW_CFG_DATA_GENERATOR allows any object to produce
^
^^^
^ insert word 'interface'
> blob of data consumable by the fw_cfg device. Implem
On Fri, Dec 06, 2024 at 07:13:51PM +0100, Philippe Mathieu-Daudé wrote:
> We want to remove fw_cfg_add_extra_pci_roots() which introduced
> PCI bus knowledge within the generic hw/nvram/fw_cfg.c file.
> Replace the calls by the pci_bus_add_fw_cfg_extra_pci_roots()
> which is a 1:1 equivalent, but u
On Fri, Dec 06, 2024 at 07:13:50PM +0100, Philippe Mathieu-Daudé wrote:
> pci_bus_add_fw_cfg_extra_pci_roots() calls the fw_cfg
> API with PCI bus specific arguments.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/pci/pci.h | 3 +++
> hw/pci/pci.c | 16
>
On Fri, Dec 06, 2024 at 07:13:52PM +0100, Philippe Mathieu-Daudé wrote:
> Now that all uses of fw_cfg_add_extra_pci_roots() have been
> converted to the newer pci_bus_add_fw_cfg_extra_pci_roots(),
> we can remove that bogus method. hw/nvram/fw_cfg must
> stay generic. Device specific entries have t
We plans to use a relatively large number of UART connections, and currently
test all UARTs that can be used.
When we use qumu for simulation, the problem was discovered.
The current code does not allocate char devices with index 5 (label serial5).
And even if there are more serial devices, th
Add common header file include/hw/intc/loongarch_extioi_common.h, and
move some macro definition from include/hw/intc/loongarch_extioi.h to
the common header file.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
include/hw/intc/loongarch_extioi.h| 50 +--
include/hw/in
With some structure such as vmstate and property, rename LoongArchExtIOI
with LoongArchExtIOICommonState, these common structure will be moved
to common file.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_extioi.c | 41 +++---
1 file changed
Remove definition about LoongArchPCHPIC and LOONGARCH_PCH_PIC, and
replace them with LoongArchPICCommonState and LOONGARCH_PIC_COMMON
separately. Also remove unnecessary header files.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 24 ++--
Add common header file hw/intc/loongarch_pic_common.h, and move
some macro definition from hw/intc/loongarch_pch_pic.h to the common
header file.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
include/hw/intc/loongarch_pch_pic.h| 36 +++---
include/hw/intc/loongarch_pic_c
With pic vmstate, rename structure name vmstate_loongarch_pch_pic with
vmstate_loongarch_pic_common, and with pic property rename
loongarch_pch_pic_properties with loongarch_pic_common_properties.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 52 +++
Rename structure LoongArchExtIOI with LoongArchExtIOICommonState,
since it is defined in file loongarch_extioi_common.h
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
include/hw/intc/loongarch_extioi.h| 1 +
include/hw/intc/loongarch_extioi_common.h | 2 +-
2 files changed, 2 inserti
Move structure LoongArchPCHPIC from header file loongarch_pch_pic.h
to file loongarch_pic_common.h, and rename structure name with
LoongArchPICCommonState.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
include/hw/intc/loongarch_pch_pic.h| 27 +
include/hw/intc/lo
Move some common functions to file loongarch_pic_common.c, the common
functions include loongarch_pic_common_realize(), property structure
loongarch_pic_common_properties and vmstate structure
vmstate_loongarch_pic_common.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_
Set TYPE_LOONGARCH_PIC inherit from TYPE_LOONGARCH_PIC_COMMON object,
it shares vmsate and property of TYPE_LOONGARCH_PIC_COMMON, and has
its own realize() function.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c| 38 --
hw/intc
Move definiton of structure LoongArchExtIOI from header file loongarch_extioi.h
to file loongarch_extioi_common.h.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
include/hw/intc/loongarch_extioi.h| 26 --
include/hw/intc/loongarch_extioi_common.h | 27
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into
staging (2024-12-11 15:16:47 +)
are available in the Git repository at:
https://gitlab.com/bibo-mao/qemu.git pull-loongarc
Memory region is created in instance_init(), merge it into function
realize(). There is no special class_init() for loongarch_pch object.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --
Add vmstate pre_save and post_load interfaces, which can be used
by pic kvm driver in future.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pic_common.c | 26 ++
include/hw/intc/loongarch_pic_common.h | 2 ++
2 files changed, 28 insertions(
On 12/13/24 10:48, Kenneth Jia(贾纪东_华硕上海) wrote:
We plans to use a relatively large number of UART connections, and currently
test all UARTs that can be used.
When we use qumu for simulation, the problem was discovered.
Which QEMU machine are you using ?
Thanks,
C.
Hi Stefan,
On 13/12/24 02:21, Stefan Hajnoczi wrote:
Applied, thanks.
I guess you are pushing to the 'master' of your personal
repository, not the QEMU project's one.
On Fri, 13 Dec 2024 at 01:25, Stefan Hajnoczi wrote:
>
> Applied, thanks.
This doesn't seem to have been applied -- did you forget
to push to upstream master?
thanks
-- PMM
On Fri, Dec 13, 2024 at 11:58:02AM +, Daniel P. Berrangé wrote:
> Libvirt does not rquire use of pcie-switch. It supports them, but in the
> absence of app requested configs, libvirt will always just populate
> pcie-root-port devices. switches are something that has to be explicitly
> asked fo
On Fri, Dec 13, 2024 at 12:00:43PM +, Daniel P. Berrangé wrote:
> On Fri, Nov 08, 2024 at 12:52:37PM +, Shameer Kolothum via wrote:
> > Hi,
> >
> > This series adds initial support for a user-creatable "arm-smmuv3-nested"
> > device to Qemu. At present the Qemu ARM SMMUv3 emulation is per
>From: Jonathan Cameron
>Sent: Thursday, December 12, 2024 20:02
>
>On Thu, 12 Dec 2024 16:55:33 +0800
>Li Zhijian via wrote:
>
>> This assertion always happens when we sanitize the CXL memory device.
>> $ echo 1 > /sys/bus/cxl/devices/mem0/security/sanitize
>>
>> It is incorrect to register an M
> I see -- though, thinking more about it, since you have
>
> fn init_timer(&mut self) {
> let raw_ptr: *mut HPETState = self;
>
> for i in 0..HPET_MAX_TIMERS {
> let mut timer = self.get_timer(i).borrow_mut();
> timer.init(i, raw_ptr).init_timer_with_s
Hi Kevin and Hanna, could you share your thoughts on this patch?
I’d greatly appreciate your feedback
--
Guoyi
On 2024/11/28 18:51, t...@chinatelecom.cn wrote:
From: Guoyi Tu
Currently, disk I/O encryption and decryption operations are performed
sequentially
in the main thread or IOthread.
Hi,
apologies for the delayed review; I've just gotten to it now.
On 06.12.2024 01:14, Yanfeng Liu wrote:
This adds virtualization mode (V bit) as bit(2) of register `priv`
per RiscV debug spec v1.0.0-rc3. Checked with gdb-multiarch v12.1.
Note that GDB may display `INVALID` tag for the value
On 12/12/24 15:42, Matthew Rosato wrote:
On 12/12/24 4:10 AM, Thomas Huth wrote:
On 09/12/2024 20.29, Matthew Rosato wrote:
This series introduces the concept of the relaxed translation requirement
for s390x guests in order to allow bypass of the guest IOMMU for more
efficient PCI passthrough.
On 13/12/2024 01.26, Nabih Estefan wrote:
Recent CDMSK Watchdog changes (eff9dc5660fad3a610171c56a5ec3fada245e519)
updated the CDMSK APB Watchdog to not free run out of reset. That led to
this test failing since it never triggers the watchdog to start running.
No watchdog running means that the t
On Fri, 13 Dec 2024 at 05:42, Philippe Mathieu-Daudé wrote:
>
> Hi Stefan,
>
> On 13/12/24 02:21, Stefan Hajnoczi wrote:
> > Applied, thanks.
>
> I guess you are pushing to the 'master' of your personal
> repository, not the QEMU project's one.
You're right. Thanks for letting me know!
Stefan
On 12/12/2024 22.52, David Hildenbrand wrote:
On 13.11.24 15:46, David Hildenbrand wrote:
On 08.10.24 12:54, David Hildenbrand wrote:
Based on current master.
There is really not much left to do on s390x, because virtio-mem already
implements most things we need today (e.g., early-migration,
u
On 08/10/2024 12.54, David Hildenbrand wrote:
With memory devices, we will have storage keys for memory that
exceeds the initial ram size.
The TODO already states that current handling is subopimal,
but we won't worry about improving that (TCG-only) thing for now.
Acked-by: Michael S. Tsirkin
On Sat, 2 Nov 2024, BALATON Zoltan wrote:
Originally memory access logs were a debug define that then were
converted to log messages but were classified as guest_errors which
already logs misc errors. As invalid memory access logs can come from
accessing not emulated peripherals or memory areas,
On 08/10/2024 12.54, David Hildenbrand wrote:
Let's prepare our address space for memory devices if enabled via
"maxmem" and if we have CONFIG_MEM_DEVICE enabled at all. Note that
CONFIG_MEM_DEVICE will be selected automatically once we add support
for devices.
Just like on other architectures,
On 08/10/2024 12.54, David Hildenbrand wrote:
Let's remember the value (successfully) set via s390_set_max_pagesize().
This will be helpful to reject hotplugged memory devices that would exceed
this initially set page size.
Handle it just like how we handle s390_get_memory_limit(), storing it in
On 12/13/24 07:37, Peter Maydell wrote:
On Fri, 6 Dec 2024 at 19:23, Pierrick Bouvier
wrote:
Reviewed following things:
- system/arm/cpu-features (options)
- system/arm/virt (options)
- boards documented and listed with -machine help (arm and aarch64)
- grep object_class_property_set_descripti
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20241211163036.2297116-25-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 7 +++
target/arm/tcg/translate-a64.c | 105 +++---
From: Richard Henderson
Arm silliness with naming, the scalar insns described
as part of the vector instructions, as separate from
the "regular" scalar insns which output to general registers.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20241211163036.2297116-58-ric
From: Richard Henderson
Add gvec interfaces for CNT and RBIT operations.
Use ctpop8 for CNT and revbit+bswap for RBIT.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20241211163036.2297116-40-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/he
From: Richard Henderson
These have generic equivalents: tcg_gen_vec_{add,sub}{16,32}_i64.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20241211163036.2297116-48-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 4
Thomas Huth writes:
> On 13/12/2024 01.26, Nabih Estefan wrote:
>> Recent CDMSK Watchdog changes (eff9dc5660fad3a610171c56a5ec3fada245e519)
>> updated the CDMSK APB Watchdog to not free run out of reset. That led to
>> this test failing since it never triggers the watchdog to start running.
>> No
ping for review...
On 11/29/24 15:38, del...@kernel.org wrote:
From: Helge Deller
This patchset adds various missing sockopt calls, so that qemu linux-user
is able to successfully build the debian gupnp package in a chroot.
Tested with a 32-bit big-endian hppa linux-user chroot running on a p
On 9/12/24 19:12, Brian Cain wrote:
Mea culpa, I don't know how I got this wrong in 2dfe93699c. Still
getting used to the new address, I suppose. Somehow I got it right in the
mailmap, though.
Signed-off-by: Brian Cain
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Signed-off-by: Richard Henderson
---
hw/display/artist.c | 2 +-
hw/display/ati.c | 2 +-
hw/display/bcm2835_fb.c | 2 +-
hw/display/bochs-display.c | 2 +-
hw/display/cg3.c | 2 +-
hw/display/cirrus_vga.c | 2 +-
hw/display/cir
Signed-off-by: Richard Henderson
---
hw/ssi/aspeed_smc.c | 4 ++--
hw/ssi/ibex_spi_host.c| 2 +-
hw/ssi/npcm7xx_fiu.c | 2 +-
hw/ssi/pnv_spi.c | 2 +-
hw/ssi/sifive_spi.c | 2 +-
hw/ssi/ssi.c | 2 +-
hw/ssi/xilinx_spi.c | 2 +-
hw/ssi/xilinx_spips.
Signed-off-by: Richard Henderson
---
hw/virtio/vdpa-dev-pci.c | 2 +-
hw/virtio/vdpa-dev.c | 2 +-
hw/virtio/vhost-scsi-pci.c | 2 +-
hw/virtio/vhost-user-blk-pci.c | 2 +-
hw/virtio/vhost-user-device.c| 2 +-
hw/virtio/vhost-user-fs-pci.c| 2 +-
hw/virtio/vhos
Signed-off-by: Richard Henderson
---
hw/riscv/opentitan.c | 2 +-
hw/riscv/riscv-iommu-pci.c | 2 +-
hw/riscv/riscv-iommu.c | 2 +-
hw/riscv/riscv_hart.c | 2 +-
hw/riscv/sifive_u.c| 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/riscv/opentitan.c b
Signed-off-by: Richard Henderson
---
hw/pci-host/astro.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c
index 379095b356..62e9c8acbf 100644
--- a/hw/pci-host/astro.c
+++ b/hw/pci-host/astro.c
@@ -461,10 +461,6 @@ static void elroy_pcihost_init(Ob
Signed-off-by: Richard Henderson
---
hw/ufs/lu.c | 2 +-
hw/ufs/ufs.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ufs/lu.c b/hw/ufs/lu.c
index 81bfff9b4e..74ff52ad09 100644
--- a/hw/ufs/lu.c
+++ b/hw/ufs/lu.c
@@ -274,7 +274,7 @@ static UfsReqResult ufs_process_scsi_
Signed-off-by: Richard Henderson
---
hw/intc/apic_common.c | 2 +-
hw/intc/arm_gic_common.c | 2 +-
hw/intc/arm_gicv2m.c | 2 +-
hw/intc/arm_gicv3_common.c| 2 +-
hw/intc/arm_gicv3_its.c | 2 +-
hw/intc/arm_gicv3_its_kvm.c | 2 +-
hw/intc/armv7m_nvic.c |
Signed-off-by: Richard Henderson
---
hw/nubus/nubus-bridge.c | 2 +-
hw/nubus/nubus-device.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c
index a42c86080f..83893e5a46 100644
--- a/hw/nubus/nubus-bridge.c
+++ b/hw/nubus/nu
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 26 +-
target/arm/cpu64.c | 6 +++---
target/arm/tcg/cpu64.c | 2 +-
3 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0cbda76ba0..1afa07511e 100644
Signed-off-by: Richard Henderson
---
hw/nvram/ds1225y.c | 2 +-
hw/nvram/eeprom_at24c.c| 2 +-
hw/nvram/fw_cfg.c | 6 +++---
hw/nvram/mac_nvram.c | 2 +-
hw/nvram/nrf51_nvm.c | 2 +-
hw/nvram/spapr_nvram.c | 2 +-
Signed-off-by: Richard Henderson
---
hw/ufs/lu.c | 2 +-
hw/ufs/ufs.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ufs/lu.c b/hw/ufs/lu.c
index 81bfff9b4e..74ff52ad09 100644
--- a/hw/ufs/lu.c
+++ b/hw/ufs/lu.c
@@ -274,7 +274,7 @@ static UfsReqResult ufs_process_scsi_
>From what I can tell this is the same issue Thomas was looking at yes.
I saw the failure on the master branch at the v9.2.0 tag (ae35f033) and just
re-tested it against (83aaec1d) and still see it. I haven't seen it be an
intermittent failure, it has failed 100% of the time that I have tested it
Sigh… apologies for re-sending v13 together with v14 here. Please ignore
v13 of course. git send-email is not my friend…
On Fri, 13 Dec 2024 at 16:24, Phil Dennis-Jordan wrote:
>
> This patch series has been through months of review and
> refinement. It now has end-to-end Reviewed-by: tags and
Signed-off-by: Richard Henderson
---
hw/m68k/mcf5206.c | 2 +-
hw/m68k/mcf_intc.c | 2 +-
hw/m68k/next-cube.c | 2 +-
hw/m68k/q800-glue.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c
index 7247cdbe5e..45e5f74600 100644
--- a/hw/m6
Signed-off-by: Richard Henderson
---
hw/xen/xen-legacy-backend.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/xen/xen-legacy-backend.c b/hw/xen/xen-legacy-backend.c
index b15393e934..f6ad58fe13 100644
--- a/hw/xen/xen-legacy-backend.c
+++ b/hw/xen/xen-legacy-backend.c
@@
Use DEFINE_PROP_UNSIGNED instead of DEFINE_PROP_UINT64
so that we can set the PropertyInfo during initialization,
instead of updating within trng_class_init.
Signed-off-by: Richard Henderson
---
hw/misc/xlnx-versal-trng.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/
Signed-off-by: Richard Henderson
---
hw/nvme/ctrl.c | 2 +-
hw/nvme/ns.c | 2 +-
hw/nvme/subsys.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index ec75419566..33a3062466 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -8927,7 +
On 9/11/24 13:32, Dorjoy Chowdhury wrote:
NSM device in AWS Nitro Enclaves supports extending with both
bytestring and string data.
Signed-off-by: Dorjoy Chowdhury
---
hw/virtio/virtio-nsm.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
Queued, thanks!
Signed-off-by: Richard Henderson
---
hw/remote/proxy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/remote/proxy.c b/hw/remote/proxy.c
index 302a0a4d4d..6f84fdd3fa 100644
--- a/hw/remote/proxy.c
+++ b/hw/remote/proxy.c
@@ -191,7 +191,7 @@ static void pci_proxy_write_conf
Signed-off-by: Richard Henderson
---
hw/char/avr_usart.c | 2 +-
hw/char/bcm2835_aux.c | 2 +-
hw/char/cadence_uart.c | 2 +-
hw/char/cmsdk-apb-uart.c| 2 +-
hw/char/debugcon.c | 2 +-
hw/char/digic-uart.c| 2 +-
hw/char/escc.c | 2 +-
hw/char/
Signed-off-by: Richard Henderson
---
hw/watchdog/sbsa_gwdt.c | 2 +-
hw/watchdog/wdt_aspeed.c | 2 +-
hw/watchdog/wdt_imx2.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/watchdog/sbsa_gwdt.c b/hw/watchdog/sbsa_gwdt.c
index 80f9b36e79..2e25d4b4e9 100644
--- a/hw/wat
Signed-off-by: Richard Henderson
---
docs/devel/migration/compatibility.rst | 4 ++--
docs/devel/virtio-backends.rst | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/devel/migration/compatibility.rst
b/docs/devel/migration/compatibility.rst
index 5a5417ef06..c7
Signed-off-by: Richard Henderson
---
hw/xen/xen-bus.c| 2 +-
hw/xen/xen-legacy-backend.c | 4 ++--
hw/xen/xen_pt.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/xen/xen-bus.c b/hw/xen/xen-bus.c
index 95b207ac8b..0d7defb8cd 100644
--- a/hw/xen/xe
Signed-off-by: Richard Henderson
---
hw/usb/bus.c | 2 +-
hw/usb/canokey.c | 2 +-
hw/usb/ccid-card-emulated.c | 2 +-
hw/usb/ccid-card-passthru.c | 2 +-
hw/usb/dev-audio.c| 2 +-
hw/usb/dev-hid.c | 6 +++---
hw/usb/dev-hub.c
Signed-off-by: Richard Henderson
---
hw/timer/a9gtimer.c | 2 +-
hw/timer/allwinner-a10-pit.c | 2 +-
hw/timer/arm_mptimer.c | 2 +-
hw/timer/arm_timer.c | 2 +-
hw/timer/aspeed_timer.c | 2 +-
hw/timer/avr_timer16.c | 2 +-
hw/timer/grlib_gptimer.c | 2 +-
h
Signed-off-by: Richard Henderson
---
hw/vfio/ap.c | 2 +-
hw/vfio/ccw.c | 2 +-
hw/vfio/pci.c | 4 ++--
hw/vfio/platform.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/vfio/ap.c b/hw/vfio/ap.c
index 4013e7b436..2e6ea2dd93 100644
--- a/hw/vfio/ap.c
+++
Signed-off-by: Richard Henderson
---
tests/unit/test-qdev-global-props.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/unit/test-qdev-global-props.c
b/tests/unit/test-qdev-global-props.c
index c8862cac5f..1eb95d2429 100644
--- a/tests/unit/test-qdev-global-props.c
+++
Signed-off-by: Richard Henderson
---
hw/block/fdc-isa.c| 2 +-
hw/block/fdc-sysbus.c | 4 ++--
hw/block/fdc.c| 2 +-
hw/block/m25p80.c | 2 +-
hw/block/nand.c | 2 +-
hw/block/pflash_cfi01.c | 2 +-
hw/block/pflash_cfi02.c | 2 +-
hw/block/swim.c
From: Philippe Mathieu-Daudé
Rather than manually copying each register, use
the libc memcpy(), which is well optimized nowadays.
Suggested-by: Pierrick Bouvier
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20241205205418.6761
From: Richard Henderson
Add gvec interfaces for CLS and CLZ operations.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 20241211163036.2297116-38-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate.h | 5 +
target/
From: Richard Henderson
Remove handle_2misc_narrow as this was the last insn decoded
by that function.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20241211163036.2297116-52-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode
Move the AArch64 TLBI insns that are declared in v8_cp_reginfo[]
into tlb-insns.c.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20241210160452.2427965-4-peter.mayd...@linaro.org
---
target/arm/cpregs.h| 11 +++
target/arm/helper.c| 182 +++
From: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 20241211163036.2297116-9-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 3 ++
target/arm/tcg/translate-a64.c | 72 ++---
From: Richard Henderson
This includes SADDLP, UADDLP, SADALP, UADALP.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20241211163036.2297116-47-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-a64.h| 2 -
target/arm/tcg/a64.deco
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