Devices where the MSI-X addresses are shared with other MMIO on BAR0
can not use msi_enable because it unmaps and remaps BAR0, which
interferes with device MMIO mappings. xhci-nec is one such device we
would like to test msix with.
Use the BAR iomap tracking structure introduced in the previous ch
Add tests which init the host controller registers to the point where
command and event rings, irqs are operational. Enumerate ports and set
up an attached device context that enables device transfer ring to be
set up and tested.
This test does a bunch of things at once and is not yet well librifi
Prepare to use some of these constants in xhci qtest code.
Signed-off-by: Nicholas Piggin
---
hw/usb/hcd-xhci.h | 190 +++
hw/usb/hcd-xhci.c | 283 ++
2 files changed, 250 insertions(+), 223 deletions(-)
diff --git a/hw/usb
Implement XHCI TR NOOP commands by setting up then immediately
completing the packet.
The IBM AIX XHCI HCD driver uses NOOP commands to check driver and
hardware health, which works after this change.
Signed-off-by: Nicholas Piggin
---
hw/usb/hcd-xhci.c | 28 +++-
1 file
Run some TR NOOP commands through the transfer ring.
Signed-off-by: Nicholas Piggin
---
tests/qtest/usb-hcd-xhci-test.c | 41 +++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/usb-hcd-xhci-test.c b/tests/qtest/usb-hcd-xhci-test.c
index 8
Hardcoded 32 bytes is used for vbsrl emulation check, there is
problem when options lsx=on,lasx=off is used for vbsrl.v instruction
in TCG mode. It injects LASX exception rather LSX exception.
Here actual operand size is used.
Signed-off-by: Bibo Mao
---
target/loongarch/tcg/insn_trans/trans_ve
The e1000e and igb tests don't clear the msix pending bit after waiting
for it sit is masked so the irq doesn't get delivered. Failing to clear
the pending interrupt means all subsequent waits for interrupt after the
first do not actually wait for an interrupt genreated by the device.
Explicitly c
Add assertions to ensure a BAR is not mapped twice, and only
previously mapped BARs are unmapped. This can help catch some
bugs.
Cc: Michael S. Tsirkin
Cc: Marcel Apfelbaum
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
tests/qtest/libqos/ahci.h | 1 +
tests/qtest/libqos
Implement MMIO PBA writes, 1 to trigger and 0 to clear.
This functionality is used by some qtests, which keep the msix irq
masked and test irq pending via the PBA bits, for simplicity. Some
tests expect to be able to clear the irq with a store, so a side-effect
of this is that qpci_msix_pending()
Per VT-d spec 4.1, 6.5.2.4, "Table 21. PASID-based-IOTLB Invalidation",
PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb
entries with matching domain id and pasid.
With stage-1 translation introduced, guest could send PASID-selective
PASID-based iotlb invalidation to flush e
From: Yu Zhang
Spec revision 3.0 or above defines more detailed fault reasons for
scalable mode. So introduce them into emulation code, see spec
section 7.1.2 for details.
Note spec revision has no relation with VERSION register, Guest
kernel should not use that register to judge what features a
PASID-based iotlb (piotlb) is used during walking Intel
VT-d stage-1 page table.
This emulates the stage-1 page table iotlb invalidation requested
by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB).
Signed-off-by: Yi Liu
Signed-off-by: Zhenzhong Duan
Reviewed-by: Clément Mathieu--Drif
Acked
Add an new element flts in IntelIOMMUState to mark stage-1 translation support
in scalable mode, this element will be exposed as an intel_iommu property
x-flts finally.
For now, it's only a placehholder and used for address width compatibility
check and block host device passthrough until nesting
From: Yi Liu
Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translation,
rename variable and functions from slpte to pte whenever possible.
But some are SST only, they are renamed with sl_ prefix.
Signed-off-by: Yi Liu
Co-developed-by: Clément Mathieu--Drif
Signed-off-by: Cl
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
Acked-by: Jason Wang
---
hw/i386/intel_iommu_internal.h | 11
hw/i386/intel_iommu.c | 50 ++
2 files changed, 61 insertions(+)
diff --git a/hw/i386
When guest configures Nested Translation(011b) or First-stage Translation only
(001b), type check passed unaccurately.
Fails the type check in those cases as their simulation isn't supported yet.
Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation")
Suggested-by: Yi Liu
Signed-off-by: Zhen
According to VTD spec, stage-1 page table could support 4-level and
5-level paging.
However, 5-level paging translation emulation is unsupported yet.
That means the only supported value for aw_bits is 48. So default
aw_bits to 48 when stage-1 translation is turned on.
For legacy and scalable mode
Per VT-d spec 4.1 section 3.15, "Untranslated requests and translation
requests that result in an address in the interrupt range will be
blocked with condition code LGN.4 or SGN.8."
This applies to both stage-1 and stage-2 IOMMU page table, move the
check from vtd_iova_to_slpte() to vtd_do_iommu_t
Hi,
Per Jason Wang's suggestion, iommufd nesting series[1] is split into
"Enable stage-1 translation for emulated device" series and
"Enable stage-1 translation for passthrough device" series.
PATCH1-5: Some preparing work before support stage-1 translation
PATCH6-9: Implement stage-1 translati
Shameer,
On 12/12/24 09:12, Eric Auger wrote:
> Connie,
>
> On 12/6/24 12:21, Cornelia Huck wrote:
>> A respin/update on the aarch64 KVM cpu models. Also available at
>> gitlab.com/cohuck/qemu arm-cpu-model-rfcv2
>>
>> Find Eric's original cover letter below, so that I do not need to
>> repeat my
This is used by some emulated devices which caches address
translation result. When piotlb invalidation issued in guest,
those caches should be refreshed.
There is already a similar implementation in iotlb invalidation.
So update vtd_iotlb_page_invalidate_notify() to make it work
also for piotlb i
Add the framework to test the intel-iommu device.
Currently only tested cap/ecap bits correctness when x-flts=on in scalable
mode. Also tested cap/ecap bits consistency before and after system reset.
Signed-off-by: Zhenzhong Duan
Acked-by: Thomas Huth
Reviewed-by: Clément Mathieu--Drif
Acked-by
According to spec, Page-Selective-within-Domain Invalidation (11b):
1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through
(PGTT=100b) mappings associated with the specified domain-id and the
input-address range are invalidated.
2. IOTLB entries caching first-stage (PGTT=001b)
Signed-off-by: Zhenzhong Duan
Acked-by: Jason Wang
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..46f80be9ca 100644
--- a/tests/qtest/
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
Reviewed-by: Yi Liu
Acked-by: Jason Wang
---
hw/i386/intel_iommu_internal.h | 3 +++
hw/i386/intel_iommu.c | 25 -
2 files changed, 27 insertions(+), 1 deletion(-)
Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities
related to scalable mode translation, thus there are multiple combinations.
This vIOMMU implementation wants to simplify it with a new property "x-flts".
When turned on in scalable mode, stage-1 translation is supported. W
Hi,
This series adds XHCI "TR NOOP" support, but adding qtests ran into
issues with PCI and MSIX, and fixing those irritated what looks like
a bug in the e1000e/igb tests.
Firstly, the XHCI NEC PCI host has a shared BAR for device registers
and MSIX space, which is not handled by qtest/pci. Keepi
This gives user flexibility to turn off FS1GP for debug purpose.
It is also useful for future nesting feature. When host IOMMU doesn't
support FS1GP but vIOMMU does, nested page table on host side works
after turning FS1GP off in vIOMMU.
This property has no effect when vIOMMU is in legacy mode o
From: Clément Mathieu--Drif
This will be used to implement the device IOTLB invalidation
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
Acked-by: Jason Wang
Reviewed-by: Yi Liu
---
hw/i386/intel_iommu.c | 38 +++---
1 file changed, 23 inse
Differences:
@@ -1,39 +1,39 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/x86/q35/DMAR.dmar, Mon Nov 11 15:31:18 2024
+ * Disassembly of /tmp/aml-SPJ4W2
Needed to build ipxe nic roms.
Reported-by: Liu Jaloo
Fixes: 22e11539e167 ("edk2: replace build scripts")
Signed-off-by: Gerd Hoffmann
---
roms/Makefile | 5 +
1 file changed, 5 insertions(+)
diff --git a/roms/Makefile b/roms/Makefile
index dfed2b216a1e..31e4b97c983b 100644
--- a/roms/Make
The TI TUSB73X0 controller has some interesting differences from NEC,
notably a separate BAR for MSIX, and PM capabilities. The spec is freely
available without sign-up.
This controller is accepted by IBM Power proprietary firmware and
software (when the subsystem IDs are set to Power servers, whi
From: Yi Liu
This adds stage-1 page table walking to support stage-1 only
translation in scalable mode.
Signed-off-by: Yi Liu
Co-developed-by: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
Acked-by: Jason Wang
---
hw/i386/in
Hi,
This adds a new USB XHCI PCI host controller model, the TI TUSB73X0.
The motivation for this is that IBM's AIX and PowerVM do not support
the NEC driver.
hcd-xhci-pci code is changed in patch 1 to make PCI settings
configurable where the new model differs from existing. E.g., the
option to a
This assertion always happens when we sanitize the CXL memory device.
$ echo 1 > /sys/bus/cxl/devices/mem0/security/sanitize
It is incorrect to register an MSIX number beyond the device's capability.
Expand the device's MSIX to 10 and introduce the `request_msix_number()`
helper function to dynam
> Since CLASS_BASE_INIT applies to the type that is being defined,
> and only to it, move it to ObjectImpl.
It makes sense since class_base_init() is used when subclass is being
initialized.
> Signed-off-by: Paolo Bonzini
> ---
> rust/hw/char/pl011/src/device.rs | 19 +--
> rust/qemu-api/s
Without descriptor libvirt cannot discover the EDK II binaries via
the qemu:///system connection.
Signed-off-by: Heinrich Schuchardt
---
pc-bios/descriptors/60-edk2-riscv64.json | 31
pc-bios/descriptors/meson.build | 3 ++-
2 files changed, 33 insertions(+), 1
To prepare to support another USB PCI Host Controller, make some PCI
configuration dynamic.
Signed-off-by: Nicholas Piggin
---
hw/usb/hcd-xhci-pci.h | 9 ++
hw/usb/hcd-xhci-nec.c | 10 +++
hw/usb/hcd-xhci-pci.c | 69 ---
3 files changed, 78 insert
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
Add helper methods that construct paths for
* log files - to be preserved at the end of a test
* scratch files - to be purged at the end of a test
* build files - anything relative to the build root
* data files - anything relative to the fu
On 09/12/2024 20.29, Matthew Rosato wrote:
This series introduces the concept of the relaxed translation requirement
for s390x guests in order to allow bypass of the guest IOMMU for more
efficient PCI passthrough.
With this series, QEMU can indicate to the guest that an IOMMU is not
strictly req
On Thu, Dec 12, 2024 at 09:12:33AM +0100, Eric Auger wrote:
> Connie,
>
> On 12/6/24 12:21, Cornelia Huck wrote:
> > A respin/update on the aarch64 KVM cpu models. Also available at
> > gitlab.com/cohuck/qemu arm-cpu-model-rfcv2
snip
> From a named model point of view, since I do not see much tr
On Wed, Dec 11, 2024 at 08:31:35PM +0100, Thomas Huth wrote:
> On 11/12/2024 18.26, Daniel P. Berrangé wrote:
> > Identified using 'pylint --disable=all --enable=W0611'
> >
> > Reviewed-by: Thomas Huth
> > Signed-off-by: Daniel P. Berrangé
> > ---
> > tests/functional/qemu_test/asset.py
Add tracing for more received packet types, cbw_state changes, and
some more SCSI callbacks. These were useful in debugging relaxed
packet ordering support.
Signed-off-by: Nicholas Piggin
---
hw/usb/dev-storage.c | 23 +--
hw/usb/trace-events | 9 -
2 files changed,
The mass storage reset request handling does not reset in-flight
SCSI requests or USB MSD packets. Implement this by calling the
device reset handler which should take care of everything.
Signed-off-by: Nicholas Piggin
---
hw/usb/dev-storage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-
The async packet handling logic has places that infer whether the
async packet is data or CSW, based on context. This is not wrong,
it just makes the logic easier to follow if they are categorised
when they are accepted.
Signed-off-by: Nicholas Piggin
---
include/hw/usb/msd.h | 5 +-
hw/usb/de
This series ultimately permits relaxed ordering of USB mass-storage
packets from the host, as allowed by the usbmassbulk 1.0 spec, but
not usually seen in drivers. AIX drivers do require this ordering.
The RFC unsurprisingly had no comments, it wasn't polished well so
don't bother to look at it. T
The USB MSD protocol has 3 packets that make up a command, and only one
command may be active at any time.
- CBW to start a command (that contains a SCSI request).
- DATA (IN or OUT) to request data transfer between host and SCSI layer.
- CSW to return status and complete the command.
DATA is omi
The CBW structure is 31 bytes, so CBW DATAOUT packets must be at least
31 bytes. QEMU enforces exactly 31 bytes, but this is inconsistent with
how it handles CSW packets (where it allows greater than or equal to 13
bytes) despite wording in the spec[*] being similar for both packet
types: "shall en
Split in and out packet handling int otheir own functions, to make
them a bit more managable.
Signed-off-by: Nicholas Piggin
---
hw/usb/dev-storage.c | 266 +++
1 file changed, 145 insertions(+), 121 deletions(-)
diff --git a/hw/usb/dev-storage.c b/hw/usb
This is a convenience change that accepts a status when completing a
packet.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/usb/dev-storage.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storag
Errors in incoming USB MSD packet format or context would typically
be guest software errors. Log these under guest errors.
Signed-off-by: Nicholas Piggin
---
hw/usb/dev-storage.c | 53 +++-
1 file changed, 42 insertions(+), 11 deletions(-)
diff --git a/h
Add more assertions to help verify internal logic.
Signed-off-by: Nicholas Piggin
---
hw/usb/dev-storage.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
index 4e23537cd75..c04cee0041b 100644
--- a/hw/usb/d
This reflects a little better what it does, particularly with a
subsequent change to relax the order packets are seen in. This
field is not the general state of the MSD state machine, rather
it follows packets that are completed as part of a CBW command.
The difference is a bit subtle, so for a co
These structures are hardware interfaces, ensure the layout is
correct.
Signed-off-by: Nicholas Piggin
---
hw/usb/dev-storage.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
index 2d7306b0572..87c22476f6b 100644
--- a/hw/usb/d
On Thu, Dec 12, 2024 at 12:16:55AM +0100, Philippe Mathieu-Daudé wrote:
> When running Clang static analyzer on macOS I'm getting:
snip
> Fix by explicitly disabling -Wunused-value from these meson checks.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> RFC: Probably meson should do that in
From: Clément Mathieu--Drif
Stage-1 translation must fail if the address to translate is
not canonical.
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
Acked-by: Jason Wang
Reviewed-by: Yi Liu
---
hw/i386/intel_iommu_internal.h | 1 +
hw/i386/intel_iommu.c | 23
Connie,
On 12/6/24 12:21, Cornelia Huck wrote:
> A respin/update on the aarch64 KVM cpu models. Also available at
> gitlab.com/cohuck/qemu arm-cpu-model-rfcv2
>
> Find Eric's original cover letter below, so that I do not need to
> repeat myself on the aspects that have not changed since RFCv1 :)
>
Hi Thomas,
2 minor comments but LGTM
On 10/12/2024 13:56, Thomas Huth wrote:
Caution: External email. Do not open attachments or click links, unless this
email comes from a known sender and you know the content is safe.
Convert the intel_iommu test to the new functional framework.
This test n
On Thu, Dec 12 2024, Daniel P. Berrangé wrote:
> On Thu, Dec 12, 2024 at 09:12:33AM +0100, Eric Auger wrote:
>> Connie,
>>
>> On 12/6/24 12:21, Cornelia Huck wrote:
>> > A respin/update on the aarch64 KVM cpu models. Also available at
>> > gitlab.com/cohuck/qemu arm-cpu-model-rfcv2
>
> snip
>
>>
On Mon, Dec 09, 2024 at 01:37:11PM +0100, Paolo Bonzini wrote:
> Date: Mon, 9 Dec 2024 13:37:11 +0100
> From: Paolo Bonzini
> Subject: [PATCH 20/26] rust: re-export C types from qemu-api submodules
> X-Mailer: git-send-email 2.47.1
>
> Long term we do not want device code to use "bindings" at al
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
This removes direct creation of temporary dirs
Signed-off-by: Daniel P. Berrangé
---
tests/functional/test_arm_aspeed.py | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/tests/functional/test_arm_aspeed.py
b/tests/functiona
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
This removes direct access of the 'BUILD_DIR' variable.
Reviewed-by: Thomas Huth
Signed-off-by: Daniel P. Berrangé
---
...
diff --git a/tests/functional/test_virtio_gpu.py
b/tests/functional/test_virtio_gpu.py
index 7654421e6b..630569bff8 10075
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
More uncompress related code will be added shortly, so having a
separate file makes more sense.
The utils.py imports the functions from archive.py, so that
existing callers don't need to be modified. This avoids
redundant code churn until later in t
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
Currently cpio_extract differs from tar_extract/zip_extract
in that it only allows a file-like object as input. Adapt it
to also support filenames.
Signed-off-by: Daniel P. Berrangé
---
tests/functional/qemu_test/archive.py | 16 +++-
On Mon, Dec 09, 2024 at 01:37:09PM +0100, Paolo Bonzini wrote:
> Date: Mon, 9 Dec 2024 13:37:09 +0100
> From: Paolo Bonzini
> Subject: [PATCH 18/26] rust: qom: add possibility of overriding unparent
> X-Mailer: git-send-email 2.47.1
>
> Add a blanket definition of ClassInitImpl that thunks
> Obj
Only physmem.c includes libpmem and libdaxctl headers.
No need to pass them to all system_ss[] files.
Signed-off-by: Philippe Mathieu-Daudé
---
system/meson.build | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/system/meson.build b/system/meson.build
index f7e2c8b826f.
Extracted from a huge branch where files are moved from
specific_ss[] to system_ss[] after exec/ headers are reworked.
Philippe Mathieu-Daudé (2):
system: Restrict libSDL CPPFLAGS to vl.c
system: Restrict libpmem and libdaxctl CPPFLAGS to physmem.c
system/meson.build | 10 --
1 file
Only vl.c includes libSDL headers.
No need to pass them to all system_ss[] files.
Signed-off-by: Philippe Mathieu-Daudé
---
system/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/system/meson.build b/system/meson.build
index 4952f4b2c7d..f7e2c8b826f 100644
---
> +fn init_qom() {
> +static ONCE: Mutex> = Mutex::new(Cell::new(false));
> +
> +let g = ONCE.lock().unwrap();
> +if !g.get() {
> +unsafe {
> +module_call_init(module_init_type::MODULE_INIT_QOM);
> +}
> +g.set(true);
> +}
> +}
Only one question:
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
More archive related code will be added shortly, so having a
separate file makes more sense.
The utils.py imports the functions from archive.py, so that
existing callers don't need to be modified. This avoids
redundant code churn until later in the
On 12/5/24 8:23 AM, baturo.ale...@gmail.com wrote:
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4e80dcd2e6..fd3ea9ce76 100644
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
This mirrors the existing archive_extract and cpio_extract helpers
Signed-off-by: Daniel P. Berrangé
---
tests/functional/qemu_test/archive.py | 8
1 file changed, 8 insertions(+)
Reviewed-by: Thomas Huth
Hi,
Thanks for the new version, changes are ok for me!
@Michael @LiuYi, @Jason, do you think we are ready to move forward?
Thanks
>cmd
On 12/12/2024 09:37, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender a
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
There are many types of archives that the tests deal with. Provide
a generalized 'archive_extract' that can detect the format and
delegate to the appropriate helper for extraction. This ensures
that all archive extraction code follows the same design
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
This helper wrappers archive.archive_extract, forcing the use of the
scratch directory, to ensure any extracted files are cleaned at test
termination. If a specific member is requested, then the path to the
extracted file is also returned.
Signed-of
Am 11.12.2024 um 22:39 hat Peter Xu geschrieben:
> On Wed, Dec 11, 2024 at 05:25:10PM -0300, Fabiano Rosas wrote:
> > Peter Xu writes:
> >
> > > Coroutines are used in many cases in block layers. It's also used in live
> > > migration when on destination side, and it'll be handy to diagnose crash
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
Replace use of lzma_uncompress and gzip_uncompress with the
new uncompress helper.
Signed-off-by: Daniel P. Berrangé
---
Reviewed-by: Thomas Huth
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
Now that all tests are converted over to the higher level wrapper
functions, the back compat imports from utils.py are redundant.
Signed-off-by: Daniel P. Berrangé
---
tests/functional/qemu_test/utils.py | 5 -
1 file changed, 5 deletions(-)
The "special_features" field / parameter holds the subset of schema
features that are for internal code use. Specifically 'DEPRECATED'
and 'UNSTABLE'.
This special casing of internal features is going to be removed, so
prepare for that by renaming to 'features'. Using a fixed size type
is also bes
This replaces use of the constants from the QapiSpecialFeatures
enum, with constants from the auto-generate QapiFeatures enum
in qapi-features.h
The 'deprecated' and 'unstable' features still have a little bit of
special handling, being force defined to be the 1st + 2nd features
in the enum, regar
When we shortly expose all feature names to code, it will be valid to
include a '-', which must be translated to a '_' for the enum constants.
Signed-off-by: Daniel P. Berrangé
---
scripts/qapi/gen.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/scripts/qapi/gen.py b/scr
This series is a spin-off from
https://lists.nongnu.org/archive/html/qemu-devel/2024-06/msg00807.html
That series introduced a pragma allowing a schema to declare extra
features that would be exposed to code.
Following Markus' suggestion:
https://lists.nongnu.org/archive/html/qemu-devel/202
This updates the QAPI code generation to refer to 'features' instead
of 'special_features', in preparation for generalizing their exposure.
Signed-off-by: Daniel P. Berrangé
---
scripts/qapi/commands.py | 4 ++--
scripts/qapi/gen.py | 8
scripts/qapi/types.py| 10 +-
This series fixes some runtime overhead when handling interrupts in AHCIState.
It then extracts the SysBus implementation into a dedicated file for separation
of concerns.
v4:
* Port away from qemu_allocate_irq() while at it
v3:
* Remove extra PCI include in ahci-internal.h
* Extract SysBus imple
Implement in dedicated file, just like TYPE_ICH9_AHCI.
Signed-off-by: Bernhard Beschow
---
hw/ide/ahci-sysbus.c | 91
hw/ide/ahci.c| 67
hw/arm/Kconfig | 10 ++---
hw/ide/Kconfig | 4 ++
hw/ide/mes
In some adhoc profiling booting Linux VMs, it's observed that ahci_irq_lower()
can be a hot path (1+ triggers until login prompt appears). Even though the
parent device never changes, this method re-determines whether the parent device
is a PCI device or not using the rather expensive object_dy
On 12/11/24 00:06, Maciej S. Szmigiero wrote:
On 9.12.2024 10:28, Avihai Horon wrote:
On 17/11/2024 21:20, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
Implement the multifd device state transfer via additional per-device
t
On 11/12/2024 18.26, Daniel P. Berrangé wrote:
The 'run_cmd' helper is re-implementing a convenient helper that
already exists in the form of the 'run' and 'check_call' methods
provided by 'subprocess'.
Signed-off-by: Daniel P. Berrangé
---
Reviewed-by: Thomas Huth
On 12/12/24 10:52, Zhao Liu wrote:
On Mon, Dec 09, 2024 at 01:37:10PM +0100, Paolo Bonzini wrote:
Date: Mon, 9 Dec 2024 13:37:10 +0100
From: Paolo Bonzini
Subject: [PATCH 19/26] rust: rename qemu-api modules to follow C code a bit
more
X-Mailer: git-send-email 2.47.1
A full match would mean
Fabiano Rosas writes:
> Fabiano Rosas writes:
>
>> v3:
>> - Fixed some more hook names I had missed;
>> - Move addition of migration-qmp.c in meson to correct patch;
>> - Moved QEMU_ENV_* variables to framework.c where they are used;
>> - patch 7: improve commit message;
>> -
On 12/12/24 15:44, Philippe Mathieu-Daudé wrote:
The TranslationBlock flags are defined in 'exec/translation-block.h'.
tcg_cflags_has/set() and curr_cflags() use them, it is more logical
to declare them in the same place. Move them there too.
Suggested-by: Richard Henderson
Signed-off-by: Phili
On 12/12/24 08:10, Philippe Mathieu-Daudé wrote:
qatomic_cmpxchg__nocheck() is declared in "qemu/atomic.h".
Include it in order to avoid when refactoring unrelated headers:
In file included from ../../accel/tcg/tcg-runtime-gvec.c:22:
In file included from include/exec/helper-proto-comm
On 12/12/24 08:10, Philippe Mathieu-Daudé wrote:
Since commit 139c1837db ("meson: rename included C source files
to .c.inc"), QEMU standard procedure for included C files is to
use *.c.inc.
Besides, since commit 6a0057aa22 ("docs/devel: make a statement
about includes") this is documented in the
On Thu, Dec 12, 2024 at 03:14:53PM +0100, Thomas Huth wrote:
> On 11/12/2024 18.26, Daniel P. Berrangé wrote:
> > If downloading of assets has been disabled, then skip running a
> > test if the assets it has registered are not already downloaded.
> >
> > Signed-off-by: Daniel P. Berrangé
> > ---
On Wed, Dec 11, 2024 at 12:05:03AM +0100, Maciej S. Szmigiero wrote:
> On 4.12.2024 23:43, Peter Xu wrote:
> > On Thu, Nov 28, 2024 at 01:11:53PM +0100, Maciej S. Szmigiero wrote:
> > > > > +static int qemu_loadvm_load_thread(void *thread_opaque)
> > > > > +{
> > > > > + struct LoadThreadData *d
On 12/12/24 13:04, Zhi Wang wrote:
Hi folks:
Per the discussion with Ira/Jonathan in the LPC 2024 and in the CXL
discord channel, we are trying to introduce a CXL type-2 device emulation
in QEMU, as there are work currently on supporting CXL type-2 device [1]
in Linux kernel and CXL type-2 dev
On 12.12.24 02:04, Daniil Tatianin wrote:
Replace the boolean value enable_mlock with an enum and add a helper to
decide whether we should be calling os_mlock.
This is a stepping stone towards introducing a new mlock mode, which
will be the third possible state of this enum.
Signed-off-by: Dani
On 12.12.24 02:04, Daniil Tatianin wrote:
Locking the memory without MCL_ONFAULT instantly prefaults any mmaped
anonymous memory with a write-fault, which introduces a lot of extra
overhead in terms of memory usage when all you want to do is to prevent
kcompactd from migrating and compacting QEMU
On 12/12/24 13:04, Zhi Wang wrote:
From: Zhi Wang
Introduce a CXL type-2 device emulation that provides a minimum base for
testing kernel CXL core type-2 support and CXL type-2 virtualization. It
is also a good base for introducing the more emulated features.
Currently, it only supports:
-
The requested feedback was to convert the tpmdev handler to being json
based, which requires rethreading all the backends. The good news is
this reduced quite a bit of code (especially as I converted it to
error_fatal handling as well, which removes the return status
threading).
v3 pulls out more
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