On Wed, 2024-12-04 at 17:03 +0100, Mario Fleischmann wrote:
> Hi everyone,
>
> I'd like to chime in here because we are sitting on a similar patch
> which I wanted to send to the mailing list as soon as riscv-debug-spec
> v1.0.0 becomes ratified.
>
> For hypervisor support, `(qemu) info registe
On 12/4/24 14:26, Philippe Mathieu-Daudé wrote:
Rather that using the binary endianness, use the vCPU one.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/generic-loader.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/core/generic-loader.c b/hw/core/generic-
On Wed, 2024-12-04 at 12:39 -0800, Pierrick Bouvier wrote:
> Signed-off-by: Pierrick Bouvier
> ---
> docs/system/arm/fby35.rst | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst
> index bf6da6baa2a..ed9faef363c 100644
> --- a/docs/sy
I tested this patch with virtio-net regression tests, these changes
are working fine related to the virtio-net part.
Tested-by: Lei Yang
On Wed, Dec 4, 2024 at 2:27 AM Richard Henderson
wrote:
>
> On 12/3/24 11:24, Philippe Mathieu-Daudé wrote:
> > Headers in include/sysemu/ are not only relate
On 12/4/24 14:41, Philippe Mathieu-Daudé wrote:
Rather than manually copying each register, use
the libc memcpy(), which is well optimized.
Signed-off-by: Philippe Mathieu-Daudé
---
Worth renaming as reg8cpy()?
---
target/sparc/win_helper.c | 9 +
1 file changed, 1 insertion(+), 8 de
HPET device (Rust device) needs to define the bit type property.
Add a variant of define_property macro to define bit type property.
Signed-off-by: Zhao Liu
---
rust/qemu-api/src/qdev.rs | 12
1 file changed, 12 insertions(+)
diff --git a/rust/qemu-api/src/qdev.rs b/rust/qemu-api/
From: Paolo Bonzini
Similar to the existing BqlCell, introduce a custom interior mutability
primitive that resembles RefCell but accounts for QEMU's threading model.
Borrowing the RefCell requires proving that the BQL is held, and
attempting to access without the BQL is a runtime panic.
Almost a
The get_mut() is useful when doing compound assignment operations, e.g.,
*c.get_mut() += 1.
Implement get_mut() for BqlCell by referring to Cell.
Signed-off-by: Zhao Liu
---
rust/qemu-api/src/cell.rs | 25 +
1 file changed, 25 insertions(+)
diff --git a/rust/qemu-api/sr
Add the HPETTimer and HPETState (HPET timer block), along with their
basic methods and register definitions.
This is in preparation for supporting the QAPI interfaces.
Note, wrap all items in HPETState that may be changed in the callback
called by C code into the BqlCell/BqlRefCell.
Signed-off-b
The MemTxAttrs structure is composed of bitfield members, and bindgen is
unable to generate an equivalent macro definition for
MEMTXATTRS_UNSPECIFIED.
Therefore, we have to manually define a global constant variable
MEMTXATTRS_UNSPECIFIED to support calls from Rust code.
However, the binding meth
The bindgen supports `static inline` function binding since v0.64.0 as
an experimental feature (`--wrap-static-fns`), and stabilizes it after
v0.70.0.
But the oldest version of bindgen supported by QEMU is v0.60.1, so
there's no way to generate the bindings for timer_new() and its variants
which a
Add HPET configuration in PC's Kconfig options, and select HPET device
(Rust version) if Rust is supported.
Signed-off-by: Zhao Liu
---
hw/i386/Kconfig | 2 ++
hw/timer/Kconfig | 1 -
rust/hw/Kconfig | 1 +
rust/hw/timer/Kconfig | 2 ++
4 files changed, 5 insertions(+), 1 deleti
Implement QAPI support for HPET device in qdev.rs.
Additionally, wrap the handling of HPET internal details as traits to be
specifically implemented in hpet.rs.
Signed-off-by: Zhao Liu
---
rust/hw/timer/hpet/src/fw_cfg.rs | 2 -
rust/hw/timer/hpet/src/hpet.rs | 232 +
The bindgen supports `static inline` function binding since v0.64.0 as
an experimental feature (`--wrap-static-fns`), and stabilizes it after
v0.70.0.
But the oldest version of bindgen supported by QEMU is v0.60.1, so
there's no way to generate the binding for deposit64() which is `static
inline`
From: Paolo Bonzini
The Big QEMU Lock (BQL) is used to provide interior mutability to Rust
code. While BqlCell performs indivisible accesses, an equivalent of
RefCell will allow the borrower to hold to the interior content for a
long time. If the BQL is dropped, another thread could come and mu
HPET device needs to access and update hpet_cfg variable, but now it is
defined in hw/i386/fw_cfg.c and Rust code can't access it.
Move hpet_cfg definition to hpet.c (and rename it to hpet_fw_cfg). This
allows Rust HPET device implements its own global hpet_fw_cfg variable,
and will further reduce
The qdev_init_gpio_{in|out} are qdev interfaces, so that it's natural to
wrap them as DeviceState's methods in Rust API, which could eliminate
unsafe cases in the device lib.
Wrap qdev_init_gpio_{in|out} as methods in a new trait DeviceGPIOImpl.
In addition, for qdev_init_gpio_in(), to convert th
Hi,
After making empty promises for many months, I have finally written the
Rust version of HPET :-) I'm also very grateful for the help from Paolo,
Manos, and Junjie!
Overall, HPET in Rust maintains the same logic as the original C
version, adhering to the IA-HPET spec v1.0a [1]. While keeping t
Define HPETFwEntry structure with the same memory layout as
hpet_fw_entry in C.
Further, define the global hpet_fw_cfg variable in Rust which is the
same as the C version. This hpet_fw_cfg variable in Rust will replace
the C version one and allows both Rust code and C code to access it.
The Rust
> After making empty promises for many months, I have finally written the
> Rust version of HPET :-) I'm also very grateful for the help from Paolo,
> Manos, and Junjie!
>
> Overall, HPET in Rust maintains the same logic as the original C
> version, adhering to the IA-HPET spec v1.0a [1]. While ke
Add a CPU entry for the RV64 XiangShan NANHU CPU which
supports single-core and dual-core configurations. More
details can be found at
https://docs.xiangshan.cc/zh-cn/latest/integration/overview
Signed-off-by: MollyChen
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 29 +
Hi Xiaoyao,
Sorry for late reply.
> @@ -7490,6 +7489,7 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu)
> void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
> {
> CPUX86State *env = &cpu->env;
> +CPUState *cs = CPU(cpu);
> FeatureWord w;
> int i;
> GList
I'm also very sorry, but I have a slightly different opinion...
> accel/tcg/user-exec-stub.c | 4 +++
> hw/core/cpu-common.c | 2 +-
> include/hw/core/cpu.h | 8 +
> system/cpus.c | 6 +++-
> target/alpha/cpu.c | 2 ++
> target/arm/cpu.c | 2 ++
Hi Cedric,
> Subject: Re: [PATCH v3 3/7] hw:sdhci: Introduce a new "capareg" class member
> to set the different Capability Registers
>
> On 12/4/24 09:05, Jamin Lin wrote:
> > Currently, it set the hardcode value of capability registers to all
> > ASPEED SOCs However, the value of capability re
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast2600.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index be3eb70cdd..c40d3d8443 100644
--- a/hw/arm
change from v1:
This patch series do not support boot from an eMMC.
Only support eMMC and SD Slot 0 as storages.
change from v2:
- Add hw/sd/aspeed_sdhci: Fix coding style patch
change from v3:
- Directly set capareg and sd_spec_version instead of property
- Keep DEFINE_TYPES
change from v4:
- K
Introduce a new ast2700 class to support AST2700. Add a new ast2700 SDHCI class
init function and set the value of capability register to "0x000719f80080".
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/sd/aspeed_sdhci.c | 14 ++
include/hw/sd/aspeed_sdhci
On 4/12/24 08:11, Thomas Huth wrote:
This file should belong to the R2D machine in the MAINTAINERS file.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1
slot and registers base address is start at 0x1408_ and its interrupt is
connected to GICINT133_INTC at bit 1.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 20 +
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/sd/aspeed_sdhci.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index 98d5460905..acd6538261 100644
--- a/hw/sd/aspee
Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capability registers should be different for all ASPEED
SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for
64-bits System Bus support for AST2700.
Introduce a new "capareg"
From: Hendrik Wüthrich
Add code to initialize all necessary state for the RDT device.
Signed-off-by: Hendrik Wüthrich
---
hw/i386/rdt.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c
index d0afbd04fb..2fb9fb476b 100644
--- a/h
From: Hendrik Wüthrich
A branch with the patches applied can be found at:
https://github.com/Gray-Colors/Intel_RDT_patches_applied
The changes made introduce the following features:
* Feature enumeration for Intel RDT allocation.
* Feature enumeration for Intel RDT monitoring.
* Intel RDT monit
From: Hendrik Wüthrich
Implement rdmsr and wrmsr for the following MSRs:
* MSR_IA32_PQR_ASSOC
* MSR_IA32_QM_EVTSEL
* MSR_IA32_QM_CTR
* IA32_L3_QOS_Mask_n
* IA32_L2_QOS_Mask_n
* IA32_L2_QoS_Ext_BW_Thrtl_n
This allows for the guest to call RDT-internal functions to
associate an RMID with a CLOSID
From: Hendrik Wüthrich
Make sure that RDT monitoring and allocation features are included in
in full_cpuid_auto_level.
Signed-off-by: Hendrik Wüthrich
---
target/i386/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a400839216..787bb5ba9
From: Hendrik Wüthrich
Add RDT code to Associate CLOSID with RMID / set RMID for monitoring,
write COS, and read monitoring data. This patch does not add code for
the guest to interact through these things with MSRs, only the actual
ability for the RDT device to do them.
Signed-off-by: Hendrik
On Tue, 3 Dec 2024 10:14:28 +0100
Christian Schoenebeck wrote:
> 'Twalk' is the most important request type in the 9p protocol to look out
> for when debugging 9p communication. That's because it is the only part
> of the 9p protocol which actually deals with human-readable path names,
> whereas
From: Hendrik Wüthrich
Adjust minimum CPUID level if RDT monitoring or allocation features are
enabled to ensure that CPUID will return them.
Signed-off-by: Hendrik Wüthrich
---
target/i386/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/c
Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1
slot and registers base address is start at 0x1209_ and its interrupt is
connected to GICINT 15.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 15 +++
1 file chang
From: Hendrik Wüthrich
Change config to show RDT, add minimal code to the rdt.c module to make
sure things still compile.
Signed-off-by: Hendrik Wüthrich
---
hw/i386/Kconfig | 4 ++
hw/i386/meson.build | 1 +
hw/i386/rdt.c | 96 +++
in
Em Wed, 4 Dec 2024 08:54:40 +0100
Igor Mammedov escreveu:
> On Tue, 3 Dec 2024 14:47:30 +0100
> Mauro Carvalho Chehab wrote:
>
> > Em Tue, 3 Dec 2024 12:51:43 +0100
> > Igor Mammedov escreveu:
> >
> > > On Fri, 22 Nov 2024 10:11:30 +0100
> > > Mauro Carvalho Chehab wrote:
> > >
> > >
On Tue, Dec 03, 2024 at 05:22:50PM +, Alex Bennée wrote:
> Peter Maydell writes:
>
> > On Mon, 18 Nov 2024 at 17:24, Pierrick Bouvier
> > wrote:
> >>
> >> Present the various parts of QEMU and organization of codebase.
> >>
> >> Signed-off-by: Pierrick Bouvier
> >
> > I like this; it's some
On Wed, Dec 04, 2024 at 08:07:57AM +0100, Thomas Huth wrote:
> When running "make -j$(nproc) check SPEED=thorough", the sh4_tuxrun
> test is timing out for me, and using TIMEOUT_MULTIPLIER I can see
> that it clearly takes more than 100 seconds to finish. Thus increase
> the timeout setting of this
From: Hendrik Wüthrich
Add CPUID enumeration for intel RDT monitoring and allocation, as well
as the flags used in the enumeration code.
Signed-off-by: Hendrik Wüthrich
---
hw/i386/rdt.c | 33 +
include/hw/i386/rdt.h | 31 +++
target/i386/cpu.c
From: Hendrik Wüthrich
Add RDT features to feature word / TCG.
Signed-off-by: Hendrik Wüthrich
---
target/i386/cpu.c | 30 --
target/i386/cpu.h | 2 ++
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a819
Reviewed-by: Konstantin Kostiuk
On Mon, Dec 2, 2024 at 2:19 PM Daniel P. Berrangé
wrote:
> Provide a way to report the process load average, via a new
> 'guest-get-load' command.
>
> This is only implemented for POSIX platforms providing 'getloadavg'.
>
> Example illustrated with qmp-shell:
>
>
Reviewed-by: Konstantin Kostiuk
On Mon, Nov 4, 2024 at 11:54 AM Michal Privoznik
wrote:
> The run_agent_once() function is already given GAState via an
> argument. There's no need to access the global ga_state variable
> which points to the argument anyways (thanks to
> initialize_agent()). Wor
Hi Michal,
Please fix the issue that Jan mentioned.
All commits should be logically correct even if it part of one series.
Applying this will cause regression.
Best Regards,
Konstantin Kostiuk.
On Wed, Nov 6, 2024 at 6:07 PM Ján Tomko wrote:
> On a Monday in 2024, Michal Privoznik wrote:
> >C
Pierrick Bouvier writes:
> This boot an OP-TEE environment, and launch a nested guest VM inside it
> using the Realms feature. We do it for virt and sbsa-ref platforms.
>
> Signed-off-by: Pierrick Bouvier
Queued to testing/next, thanks.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Mon, Nov 4, 2024 at 11:54 AM Michal Privoznik
wrote:
> If the agent is set to daemonize but for whatever reason fails to
> init the channel, the error message is lost. Worse, the agent
> daemonizes needlessly and returns success. For instance:
>
> # qemu-ga -m virtio-serial \
> -
Le 03/12/2024 à 10:47, Andrea Bolognani a écrit :
Currently the script won't generate a configuration file that
sets up qemu-user-riscv32 on riscv64, likely under the
assumption that 64-bit RISC-V machines can natively run 32-bit
RISC-V code.
However this functionality, while theoretically possi
On 2024/12/02 23:17, Peter Maydell wrote:
On Fri, 29 Nov 2024 at 03:33, Tomoyuki HIROSE
wrote:
OK, thanks! I got understand. I thought MemoryRegionOps had to be
'static const' .
I will try to improve code so that it does not require the use of
memaccess-testdev.h.inc .
Great. The other thing I
On Tue, Dec 03, 2024 at 07:57:14AM -0600, Richard Henderson wrote:
> On 12/3/24 04:35, Peter Maydell wrote:
> > On Tue, 3 Dec 2024 at 10:19, Daniel P. Berrangé wrote:
> > > Separatley this from patch, we should also consider whether
> > > it is time to do the same for aarch64/arm7.
> > >
> > > If
On Wed, Dec 04, 2024 at 08:19:08AM +0100, Thomas Huth wrote:
> We'll need this functionality in other functional tests, too, so
> let's extract it into the qemu_test module.
> Also add an __enter__ and __exit__ function that can be used for
> using this functionality in a locked context, so that t
On Wed, 4 Dec 2024 09:56:35 +0100
Mauro Carvalho Chehab wrote:
> Em Wed, 4 Dec 2024 08:54:40 +0100
> Igor Mammedov escreveu:
>
> > On Tue, 3 Dec 2024 14:47:30 +0100
> > Mauro Carvalho Chehab wrote:
> >
> > > Em Tue, 3 Dec 2024 12:51:43 +0100
> > > Igor Mammedov escreveu:
> > >
> > > >
On Wed, Dec 04, 2024 at 08:19:10AM +0100, Thomas Huth wrote:
> This test matches exactly the first three lines of the following
> test_no_vnc_change_password test, so there is exactly zero additional
> test coverage in here.
>
> Signed-off-by: Thomas Huth
> ---
> tests/functional/test_vnc.py | 5
On Wed, Dec 04, 2024 at 08:19:08AM +0100, Thomas Huth wrote:
> We'll need this functionality in other functional tests, too, so
> let's extract it into the qemu_test module.
> Also add an __enter__ and __exit__ function that can be used for
> using this functionality in a locked context, so that t
Daniel P. Berrangé writes:
> NB, this series is targetting 10.0, NOT for 9.2 freeze.
>
> With code like
>
> Object *obj = object_new(TYPE_BLAH)
>
> the caller can be pretty confident that they will successfully create
> an object instance of TYPE_BLAH. They know exactly what type has been
> r
On 1/12/24 16:05, Richard Henderson wrote:
This function is identical with helper_vfp_sqrth.
Replace all uses.
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-a64.h| 1 -
target/arm/tcg/helper-a64.c| 11 ---
target/arm/tcg/translate-a64.c | 4 ++--
3 files chan
On 2024-12-02 10:53, Marcin Juszkiewicz wrote:
W dniu 26.11.2024 o 14:14, Peter Maydell pisze:
On Tue, 26 Nov 2024 at 08:49, Marcin Juszkiewicz
wrote:
We are working on adding RME support to SBSA Reference Platform.
When RME is enabled then RMM (Realm Managment Monitor) takes 1072MB of
memory
On 12/3/24 7:46 PM, Peter Maydell wrote:
On Tue, 3 Dec 2024 at 16:25, Anastasia Belova wrote:
Both counter and tick are uint32_t and the result
of their addition may not fit this type. Add
explicit casting to uint64_t.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes:
On 12/3/24 8:14 PM, Atish Patra wrote:
From: Kaiwen Xue
The Smcdeleg/Ssccfg adds the support for counter delegation via
S*indcsr and Ssccfg.
It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE)
to enable this extension and scountovf virtualization.
Signed-off-by: Kaiwen
On 12/3/24 8:14 PM, Atish Patra wrote:
From: Kaiwen Xue
This adds the indirect access registers required by sscsrind/smcsrind
and the operations on them. Note that xiselect and xireg are used for
both AIA and sxcsrind, and the behavior of accessing them depends on
whether each extension is e
Signed-off-by: Rajnesh Kanwal
Reviewed-by: Alistair Francis
Reviewed-by: Jason Chien
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_privileged.c.inc | 5 -
2 files changed, 6 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32
The Control Transfer Records (CTR) extension provides a method to
record a limited branch history in register-accessible internal chip
storage.
This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable and the latest release can be found here
https://github.com/ri
Hi,
Can you please re-send the patch rebased on top of:
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
This is the branch we use to queue RISC-V patches that are pending upstreaming.
Thanks,
Daniel
On 12/4/24 12:15 AM, MollyChen wrote:
Add a CPU entry for the RV64 XiangShan NA
This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and
sctrdepth CSRs handling.
Signed-off-by: Rajnesh Kanwal
---
target/riscv/cpu.h | 5 ++
target/riscv/cpu_cfg.h | 2 +
target/riscv/csr.c | 144 +
3 files changed, 151 inserti
CTR entries are accessed using ctrsource, ctrtarget and ctrdata
registers using smcsrind/sscsrind extension. This commits extends
the csrind extension to support CTR registers.
ctrsource is accessible through xireg CSR, ctrtarget is accessible
through xireg1 and ctrdata is accessible through xireg
Add a subsection to machine.c to migrate CTR CSR state
Signed-off-by: Rajnesh Kanwal
---
target/riscv/machine.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index
e1bdc31c7c53a8a4f539113d501c8e46f7a914e9..b67e660e
On Tue, Nov 5, 2024 at 3:58 PM Richard Henderson
wrote:
>
> On 11/4/24 21:51, Rajnesh Kanwal wrote:
> > target/riscv/cpu.c | 26 ++-
> > target/riscv/cpu.h | 13 ++
> > target/riscv/cpu_bits.h| 94
> >
On Wed, 4 Dec 2024 08:41:16 +0100
Mauro Carvalho Chehab wrote:
> The 'physical_address' value is a faulty page. As such, 0 is
> as valid as any other value.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
> ---
> hw/acpi/ghes.c | 4
>
This series enables Control Transfer Records extension support on riscv
platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable and this series is based on v1.0_rc6 [0]
CTR extension depends on both the implementation of S-mode and Sscsrind
extension v
Hi Craig,
I think that the unexpected vstart issue persists in this patchset.
This version is unable to update the vstart CSR to the correct index when
grouping load/store elements.
For instance, if an exception is raised by an element following the first
one, and the optimization attempts to gr
CTR extension adds a new instruction sctrclr to quickly
clear the recorded entries buffer.
Signed-off-by: Rajnesh Kanwal
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 7 +++
target/riscv/helper.h | 1 +
This commit adds logic to records CTR entries of different types
and adds required hooks in TCG and interrupt/Exception logic to
record events.
This commit also adds support to invoke freeze CTR logic for breakpoint
exceptions and counter overflow interrupts.
Signed-off-by: Rajnesh Kanwal
---
t
On 12/4/24 06:56, Rajnesh Kanwal wrote:
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc
b/target/riscv/insn_trans/trans_privileged.c.inc
index
0bdfa9a0ed3313223ce9032fb24484c3887cddf9..a5c2410cfa0779b1a928e7b89bd2ee5bb24216e4
100644
--- a/target/riscv/insn_trans/trans_privileged.c.
On Tue, Dec 03, 2024 at 07:51:33PM -0500, Peter Xu wrote:
> diff --git a/migration/migration.c b/migration/migration.c
> index 8f7d09ca84..e01264168f 100644
> --- a/migration/migration.c
> +++ b/migration/migration.c
> @@ -701,6 +701,12 @@ migration_incoming_state_setup(MigrationIncomingState
> *m
On 12/4/24 04:12, Alex Williamson wrote:
> On Tue, 3 Dec 2024 21:35:39 +0800
> Tomita Moeko wrote:
>
>> This patchset extends the support of legacy mode igd passthrough to
>> all Intel Gen 11 and 12 devices (including Ice Lake, Jasper Lake,
>> Rocket Lake, Alder Lake and Raptor Lake), and emulat
Create a new property (x-has-hest-addr) and use it to detect if
the GHES table offsets can be calculated from the HEST address
(qemu 9.2 and upper) or via the legacy way via an offset obtained
from the hardware_errors firmware file.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Camer
The current code is actually dependent on having just one error
structure with a single source.
As the number of sources should be arch-dependent, as it will depend on
what kind of synchronous/assynchronous notifications will exist, change
the logic to dynamically build the table.
Yet, for a prop
The GHES migration logic at GED should now support HEST table
location too.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
---
hw/acpi/generic_event_device.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/acpi/generic_event_device.c b/h
Store HEST table address at GPA, placing its content at
hest_addr_le variable.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
---
Change from v8:
- hest_addr_lr is now pointing to the error source size and data.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c
There are two pointers that are needed during error injection:
1. The start address of the CPER block to be stored;
2. The address of the ack, which needs a reset before next error.
It is preferable to calculate them from the HEST table. This allows
checking the source ID, the size of the table
Hi everyone,
I'd like to chime in here because we are sitting on a similar patch
which I wanted to send to the mailing list as soon as riscv-debug-spec
v1.0.0 becomes ratified.
For hypervisor support, `(qemu) info registers` isn't enough. We need to
have both read and write access to the V-b
This series was part of the previous PR to add generic error injection
support on GHES. It depends on a cleanup patch series sent earlier
today:
https://lore.kernel.org/qemu-devel/cover.1733297707.git.mchehab+hua...@kernel.org/T/#t
It contains the changes of the math used to calculate offse
On 12/2/2024 8:20 AM, Steve Sistare wrote:
[...]
+
+/*
+ * If qmp_migrate_finish has not been called, then there is no path that
+ * will complete the cancellation. Do it now.
+ */
+if (setup && !s->to_dst_file) {
+migrate_set_state(&s->state, s->state, MIGRATION_STAT
acpi_ghes_record_errors() has an assert() at the beginning
to ensure that source_id will be lower than
ACPI_GHES_ERROR_SOURCE_COUNT. Remove a duplicated check.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes.c | 4 +---
1 file chan
On Wed, 4 Dec 2024 08:41:21 +0100
Mauro Carvalho Chehab wrote:
> The hardware error firmware is where HEST error structures are
^^^ I can't parse this, suspect you've meant
something else here
> stored. Those can be GHESv2, but they can also be other types.
>
> Bette
On Wed, 4 Dec 2024 08:41:17 +0100
Mauro Carvalho Chehab wrote:
> Split the code into separate functions to allow using the
> common CPER filling code by different error sources.
>
> The generic code was moved to ghes_record_cper_errors(),
> and ghes_gen_err_data_uncorrectable_recoverable() now
On Wed, 4 Dec 2024 08:41:18 +0100
Mauro Carvalho Chehab wrote:
> The current function used to generate GHES data is specific for
> memory errors. Give a better name for it, as we now have a generic
> function as well.
>
> Reviewed-by: Igor Mammedov
> Reviewed-by: Jonathan Cameron
> Signed-off
On Wed, 4 Dec 2024 08:41:22 +0100
Mauro Carvalho Chehab wrote:
> Currently, CPER address location is calculated as an offset of
> the hardware_errors table. It is also badly named, as the
> offset actually used is the address where the CPER data starts,
> and not the beginning of the error sourc
This boolean option 'hmem' allows users to set a memory region from
memory-backend-file as heterogeneous memory. If 'hmem=on', QEMU will
set the flag RAM_HMEM in the RAM block of the corresponding memory
region and set the e820 type to E820_SOFT_RESERVED for this region.
Signed-off-by: Zhigang Luo
On Tue, Dec 03, 2024 at 07:51:27PM -0500, Peter Xu wrote:
> migration/block: Merge block reactivations for fail/cancel
> migration/block: Extend the migration_block_* API to dest side
> migration/block: Apply the migration_block_* API to postcopy
I just noticed these three patches cannot be
On Mon, Dec 02, 2024 at 07:01:33PM -0300, Fabiano Rosas wrote:
> Make sure postcopy threads are released when migrate_cancel is
> issued. Kick the postcopy_pause semaphore and have the fault thread
> read 'fault_thread_quit' when joining.
>
> While here fix the comment mentioning userfault_event_f
On Mon, Dec 02, 2024 at 07:01:36PM -0300, Fabiano Rosas wrote:
> If the destination side fails at migration_ioc_process_incoming()
> before starting the coroutine, it will report the error but QEMU will
> not exit.
>
> Set the migration state to FAILED and exit the process if
> exit-on-error allow
On Mon, Dec 02, 2024 at 07:01:32PM -0300, Fabiano Rosas wrote:
> Introduce a new migration_test_add_suffix to allow programmatic
> creation of tests based on a suffix. Pass the test name into the test
> so it can know which variant to run.
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: Peter Xu
Peter Xu writes:
> On Mon, Dec 02, 2024 at 07:01:33PM -0300, Fabiano Rosas wrote:
>> Make sure postcopy threads are released when migrate_cancel is
>> issued. Kick the postcopy_pause semaphore and have the fault thread
>> read 'fault_thread_quit' when joining.
>>
>> While here fix the comment me
Peter Xu writes:
> On Mon, Dec 02, 2024 at 07:01:36PM -0300, Fabiano Rosas wrote:
>> If the destination side fails at migration_ioc_process_incoming()
>> before starting the coroutine, it will report the error but QEMU will
>> not exit.
>>
>> Set the migration state to FAILED and exit the proces
On Tue, Nov 26, 2024 at 12:29:35PM +, Daniel P. Berrangé wrote:
> On Mon, Nov 25, 2024 at 07:56:00PM +, Jean-Philippe Brucker wrote:
> > The KVM_CHECK_EXTENSION ioctl can be issued either on the global fd
> > (/dev/kvm), or on the VM fd obtained with KVM_CREATE_VM. For most
> > extensions,
On Tue, Nov 26, 2024 at 12:37:02PM +, Daniel P. Berrangé wrote:
> When you create a new "user creatable" object, there should also be a
> corresponding addition to qapi/qom.json.
>
> I believe you have the qom.json addition in a later patch, but it
> should actually be here
Yes, I'll move it
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