On 02/12/2024 12.44, Daniel P. Berrangé wrote:
On Sat, Nov 30, 2024 at 11:16:30AM +0100, Thomas Huth wrote:
On 29/11/2024 18.31, Daniel P. Berrangé wrote:
Put the 'which' function into shared code.
Signed-off-by: Daniel P. Berrangé
---
tests/functional/qemu_test/__init__.py | 2 +-
test
Set the Float3NaNPropRule explicitly for HPPA, and remove the
ifdef from pickNaNMulAdd().
HPPA is the only target that was using the default branch of the
ifdef ladder (other targets either do not use muladd or set
default_nan_mode), so we can remove the ifdef fallback entirely now
(allowing the "
Set the Float3NaNPropRule explicitly for i386. We had no
i386-specific behaviour in the old ifdef ladder, so we were using the
default "prefer a then b then c" fallback; this is actually the
correct per-the-spec handling for i386.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
On 1/12/24 16:05, Richard Henderson wrote:
We already use ### for 4.1.92 Data Processing (immediate),
but not the two following two third-level sections:
4.1.93 Branches, and 4.1.94 Loads and stores.
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 4 ++--
1 file changed, 2 i
On 12/2/24 17:48, Corvin Köhne wrote:
> On Mon, 2024-12-02 at 00:09 +0800, Tomita Moeko wrote:
>> CAUTION: External Email!!
>> DSM region is likely to store framebuffer in Windows, a small DSM
>> region may cause display issues (e.g. half of the screen is black).
>> By default, QEMU uses host's
On 12/2/24 07:13, Peter Maydell wrote:
Set the default NaN pattern explicitly for s390x.
Signed-off-by: Peter Maydell
---
target/s390x/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index e74055bad79..adb27504ad5 100644
--- a/target/s390x/
On 11/28/24 7:54 AM, Jason Gunthorpe wrote:
On Wed, Nov 27, 2024 at 08:44:47PM -0800, Nicolin Chen wrote:
On Wed, Nov 27, 2024 at 11:29:06PM -0500, Donald Dutile wrote:
On 11/27/24 5:21 AM, Shameerali Kolothum Thodi wrote:
W.r.t naming, maybe something related to "hardware-accelerated"?
G
On 12/2/24 07:13, Peter Maydell wrote:
Set the default NaN pattern explicitly for xtensa.
Signed-off-by: Peter Maydell
---
target/xtensa/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 3163b758235..0d4d79b58b4 100644
--- a/target/xt
On Mon, 2024-12-02 at 00:09 +0800, Tomita Moeko wrote:
> CAUTION: External Email!!
> All gen 11 and 12 igd devices have 64 bit BDSM register at 0xC0 in its
> config space, add them to the list to support igd passthrough on
> Alder/
> Raptor/Rocket/Ice/Jasper Lake platforms.
>
> Tested legacy mode
Pierrick Bouvier writes:
> On 12/2/24 02:57, Peter Maydell wrote:
>> On Sun, 1 Dec 2024 at 18:09, Pierrick Bouvier
>> wrote:
>>>
>>> Hi Marcin,
>>>
>>> On 12/1/24 05:34, Marcin Juszkiewicz wrote:
W dniu 28.11.2024 o 22:37, Pierrick Bouvier pisze:
> This boot an OP-TEE environment, and l
On Mon, Nov 25, 2024 at 9:00 PM Dorjoy Chowdhury wrote:
>
> On Mon, Nov 18, 2024 at 7:12 PM Dorjoy Chowdhury
> wrote:
> >
> > Ping.
> >
>
> Ping...
> This is a small one that can be reviewed and picked up for merging. Thanks!
>
Gentle ping.
Regards,
Dorjoy
Set the default NaN pattern explicitly for SPARC, and remove
the ifdef from parts64_default_nan.
Signed-off-by: Peter Maydell
---
target/sparc/cpu.c | 2 ++
fpu/softfloat-specialize.c.inc | 5 +
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/sparc/cpu.c b/t
On 1/12/24 16:05, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 94 +++---
target/arm/tcg/a64.decode | 7 +++
2 files changed, 59 insertions(+), 42 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 12/2/24 14:04, Alex Williamson wrote:
> On Mon, 2 Dec 2024 00:09:34 +0800
> Tomita Moeko wrote:
>
>> Define the igd device generations according to i915 kernel driver to
>> avoid confusion, and adjust comment placement to clearly reflect the
>> relationship between ids and devices.
>>
>> Sign
For IEEE fused multiply-add, the (0 * inf) + NaN case should raise
Invalid for the multiplication of 0 by infinity. Currently we handle
this in the per-architecture ifdef ladder in pickNaNMulAdd().
However, since this isn't really architecture specific we can hoist
it up to the generic code.
For
Explicitly set a rule in the softfloat tests for the inf-zero-nan
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
and so we should select here the Arm rule of
float_infzeronan_dnan_if_qnan.
Reviewed-by: Richard Henderson
---
tests/fp/fp-bench.c | 5 +
tests/fp/fp-test.c
IEEE 758 does not define a fixed rule for what NaN to return in
the case of a fused multiply-add of inf * 0 + NaN. Different
architectures thus do different things:
* some return the default NaN
* some return the input NaN
* Arm returns the default NaN if the input NaN is quiet,
and the input
If the target sets default_nan_mode then we're always going to return
the default NaN, and pickNaNMulAdd() no longer has any side effects.
For consistency with pickNaN(), check for default_nan_mode before
calling pickNaNMulAdd().
When we convert pickNaNMulAdd() to allow runtime selection of the Na
Set the FloatInfZeroNaNRule explicitly for the Arm target,
so we can remove the ifdef from pickNaNMulAdd().
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/cpu.c | 3 +++
fpu/softfloat-specialize.c.inc | 8 +---
2 files changed, 4 insertions(+), 7 de
Set the FloatInfZeroNaNRule explicitly for the HPPA target,
so we can remove the ifdef from pickNaNMulAdd().
As this is the last target to be converted to explicitly setting
the rule, we can remove the fallback code in pickNaNMulAdd()
entirely.
Signed-off-by: Peter Maydell
Reviewed-by: Richard H
Set the FloatInfZeroNaNRule explicitly for the PPC target,
so we can remove the ifdef from pickNaNMulAdd().
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/ppc/cpu_init.c | 7 +++
fpu/softfloat-specialize.c.inc | 7 +--
2 files changed, 8 insertions(+), 6
Set the Float3NaNPropRule explicitly for loongarch, and remove the
ifdef from pickNaNMulAdd().
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/loongarch/tcg/fpu_helper.c | 1 +
fpu/softfloat-specialize.c.inc| 2 --
2 files changed, 1 insertion(+), 2 deletions(-)
diff
Extend the -incoming option to allow an @MigrationChannel to be specified.
This allows channels other than 'main' to be described on the command
line, which will be needed for CPR.
Signed-off-by: Steve Sistare
---
include/migration/misc.h | 2 ++
migration/migration.c| 18 ++
Signed-off-by: Steve Sistare
---
docs/devel/migration/CPR.rst | 176 ++-
1 file changed, 174 insertions(+), 2 deletions(-)
diff --git a/docs/devel/migration/CPR.rst b/docs/devel/migration/CPR.rst
index 63c3647..a8a57c0 100644
--- a/docs/devel/migration/CPR
What?
This patch series adds the live migration cpr-transfer mode, which
allows the user to transfer a guest to a new QEMU instance on the same
host with minimal guest pause time, by preserving guest RAM in place,
albeit with new virtual addresses in new QEMU, and by preserving device
file descrip
Set the default NaN pattern explicitly for ppc.
Signed-off-by: Peter Maydell
---
target/ppc/cpu_init.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index eb9d7b13701..1253dbf622c 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init
Set the default NaN pattern explicitly for hexagon.
Remove the ifdef from parts64_default_nan(); the only
remaining unconverted targets all use the default case.
Signed-off-by: Peter Maydell
---
target/hexagon/cpu.c | 2 ++
fpu/softfloat-specialize.c.inc | 5 -
2 files changed, 2 i
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
so we can remove the ifdef from pickNaNMulAdd().
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/sparc/cpu.c | 2 ++
fpu/softfloat-specialize.c.inc | 3 +--
2 files changed, 3 insertions(+), 2 deleti
IEEE 758 does not define a fixed rule for which NaN to pick as the
result if both operands of a 3-operand fused multiply-add operation
are NaNs. As a result different architectures have ended up with
different rules for propagating NaNs.
QEMU currently hardcodes the NaN propagation logic into the
Explicitly set a rule in the softfloat tests for propagating NaNs in
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
so we should select here the Arm rule of float_3nan_prop_s_cab.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
tests/fp/fp-bench.c | 1 +
t
On Mon, Dec 02, 2024 at 01:52:46PM +0100, Thomas Huth wrote:
> On 02/12/2024 13.13, Daniel P. Berrangé wrote:
> > On Mon, Dec 02, 2024 at 11:30:28AM +0100, Thomas Huth wrote:
> > > On 29/11/2024 18.31, Daniel P. Berrangé wrote:
> > > > This helper wrappers utils.archive_extract, forcing the use of
Let's factor it out so we can reuse it.
Signed-off-by: David Hildenbrand
---
backends/hostmem-shm.c | 45 ---
include/qemu/osdep.h | 2 ++
meson.build| 8 +--
util/oslib-posix.c | 58 ++
u
Define VMSTATE_FD for declaring a file descriptor field in a
VMStateDescription.
Signed-off-by: Steve Sistare
Reviewed-by: Peter Xu
---
include/migration/vmstate.h | 9 +
migration/vmstate-types.c | 23 +++
2 files changed, 32 insertions(+)
diff --git a/include/m
Allow each migration test to define its own memory backend, replacing
the standard "-m " specification.
Signed-off-by: Steve Sistare
Reviewed-by: Fabiano Rosas
---
tests/qtest/migration-test.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/tests/qtest/
Define functions to put/get file descriptors to/from a QEMUFile, for qio
channels that support SCM_RIGHTS. Maintain ordering such that
put(A), put(fd), put(B)
followed by
get(A), get(fd), get(B)
always succeeds. Other get orderings may succeed but are not guaranteed.
Signed-off-by: Steve Sis
Add the 'cpr' channel type, and stash the incoming cpr channel for use
in a subsequent patch.
Signed-off-by: Steve Sistare
---
include/migration/cpr.h | 3 +++
migration/cpr.c | 15 +++
qapi/migration.json | 3 ++-
system/vl.c | 6 ++
4 files changed, 2
Save the memfd for ramblocks in CPR state, along with a name that
uniquely identifies it. The block's idstr is not yet set, so it
cannot be used for this purpose. Find the saved memfd in new QEMU when
creating a block. If the block size is larger in new QEMU, extend the
block using fallocate, an
Allocate auxilliary guest RAM as an anonymous file that is shareable
with an external process. This option applies to memory allocated as
a side effect of creating various devices. It does not apply to
memory-backend-objects, whether explicitly specified on the command
line, or implicitly created
Add functions to create a QEMUFile based on a unix URI, for saving or
loading, for use by cpr-transfer mode to preserve CPR state.
Signed-off-by: Steve Sistare
Reviewed-by: Peter Xu
---
include/migration/cpr.h | 3 ++
migration/cpr-transfer.c | 76 +
Set the default NaN pattern explicitly for loongarch.
Signed-off-by: Peter Maydell
---
target/loongarch/tcg/fpu_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/loongarch/tcg/fpu_helper.c
b/target/loongarch/tcg/fpu_helper.c
index aea5e0fe5e6..a83acf64b08 100644
--- a/target
Preserve memory-backend-shm memory objects during cpr-transfer.
Signed-off-by: Steve Sistare
---
backends/hostmem-shm.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/backends/hostmem-shm.c b/backends/hostmem-shm.c
index 837b9f1..0946f2a 100644
--- a/backends/ho
Set the default NaN pattern explicitly for sh4. Note that sh4
is one of the only three targets (the others being HPPA and
sometimes MIPS) that has snan_bit_is_one set.
Signed-off-by: Peter Maydell
---
target/sh4/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/sh4/cpu.c b/targe
On Thu, 28 Nov 2024 at 12:59, Richard Henderson
wrote:
>
> On 11/28/24 04:38, Peter Maydell wrote:
> > In riscv_cpu_do_interrupt() we use the 'cause' value we got out of
> > cs->exception as a shift value. However this value can be larger
> > than 31, which means that "1 << cause" is undefined be
Add a migration test for cpr-transfer mode. Defer the connection to the
target monitor, else the test hangs because in cpr-transfer mode QEMU does
not listen for monitor connections until we send the migrate command to
source QEMU.
To test -incoming defer, send a migrate incoming command to the t
Set the default NaN pattern explicitly for riscv.
Signed-off-by: Peter Maydell
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f219f0c3b52..80b09952e78 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1022,6 +
On 1/12/24 16:05, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 64 +-
target/arm/tcg/a64.decode | 22
2 files changed, 54 insertions(+), 32 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
From: Roman Penyaev
This patch simplifies (and makes less confusing) bit checks by
replacing `find_next_bit()` calls with boolean AND operation.
Resolves: Coverity CID 1563776
Signed-off-by: Roman Penyaev
Reviewed-by: "Marc-André Lureau"
Cc: Peter Maydell
Cc: Paolo Bonzini
Reviewed-by: Cléme
On 02/12/2024 13.13, Daniel P. Berrangé wrote:
On Mon, Dec 02, 2024 at 11:30:28AM +0100, Thomas Huth wrote:
On 29/11/2024 18.31, Daniel P. Berrangé wrote:
This helper wrappers utils.archive_extract, forcing the use of the
scratch directory, to ensure any extracted files are cleaned at test
term
The use_first_nan field in float_status was an xtensa-specific way to
select at runtime from two different NaN propagation rules. Now that
xtensa is using the target-agnostic NaN propagation rule selection
that we've just added, we can remove use_first_nan, because there is
no longer any code that
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
to get the NaN bit pattern to reset the FPU registers. This
works because it happens that our implementation of
floatx80_default_nan() doesn't actually look at the float_status
pointer except for TARGET_MIPS. However, this isn't guara
Set the default NaN pattern explicitly for the alpha target.
Signed-off-by: Peter Maydell
---
target/alpha/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 5d75c941f7a..70f67e6fd4e 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@
Set the default NaN pattern explicitly, and remove the ifdef from
parts64_default_nan().
Signed-off-by: Peter Maydell
---
target/i386/tcg/fpu_helper.c | 4
fpu/softfloat-specialize.c.inc | 3 ---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/i386/tcg/fpu_helper.c b
Set the FloatInfZeroNaNRule explicitly for the x86 target.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
v1->v2: Update the comment to give the info from the x86
spec rather than a TODO comment saying we need to check it...
---
target/i386/tcg/fpu_helper.c | 7 +++
fpu/s
Set the FloatInfZeroNaNRule explicitly for s390, so we
can remove the ifdef from pickNaNMulAdd().
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/s390x/cpu.c | 2 ++
fpu/softfloat-specialize.c.inc | 2 --
2 files changed, 2 insertions(+), 2 deletions(-)
diff
Set the default NaN pattern explicitly, and remove the ifdef from
parts64_default_nan().
Signed-off-by: Peter Maydell
---
target/hppa/fpu_helper.c | 2 ++
fpu/softfloat-specialize.c.inc | 3 ---
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/hppa/fpu_helper.c b/targe
Set the default NaN pattern explicitly for the arm target.
This includes setting it for the old linux-user nwfpe emulation.
For nwfpe, our default doesn't match the real kernel, but we
avoid making a behaviour change in this commit.
Signed-off-by: Peter Maydell
---
linux-user/arm/nwfpe/fpa11.c |
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion
from float64 to floatx80 using a scratch float_status, because we
don't want the conversion to affect the CPU's floating point exception
status. Currently we use a zero-initialized float_status. This will
get steadily more awkwar
The new implementation of pickNaNMulAdd() will find it convenient
to know whether at least one of the three arguments to the muladd
was a signaling NaN. We already calculate that in the caller,
so pass it in as a new bool have_snan.
Signed-off-by: Peter Maydell
---
fpu/softfloat-parts.c.inc
Set the Float3NaNPropRule explicitly for s390x, and remove the
ifdef from pickNaNMulAdd().
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/s390x/cpu.c | 1 +
fpu/softfloat-specialize.c.inc | 2 --
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/t
Set the Float3NaNPropRule explicitly for Arm, and remove the
ifdef from pickNaNMulAdd().
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/cpu.c | 5 +
fpu/softfloat-specialize.c.inc | 8 +---
2 files changed, 6 insertions(+), 7 deletions(-)
diff
Set the FloatInfZeroNaNRule explicitly for the loongarch target.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/loongarch/tcg/fpu_helper.c | 5 +
fpu/softfloat-specialize.c.inc| 7 +--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/loon
In the helper_compute_fprf functions, we pass a dummy float_status
in to the is_signaling_nan() function. This is unnecessary, because
we have convenient access to the CPU env pointer here and that
is already set up with the correct values for the snan_bit_is_one
and no_signaling_nans config settin
Set the default NaN pattern explicitly for m68k.
Signed-off-by: Peter Maydell
---
target/m68k/cpu.c | 2 ++
fpu/softfloat-specialize.c.inc | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 13b76e22488..9de8ce67078 10064
Set the Float3NaNPropRule explicitly for Arm, and remove the
ifdef from pickNaNMulAdd().
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/mips/fpu_helper.h | 4
target/mips/msa.c | 3 +++
fpu/softfloat-specialize.c.inc | 8 +---
3 files changed,
Set the default NaN pattern explicitly for tricore.
Signed-off-by: Peter Maydell
---
target/tricore/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 7014255f77c..e8b0ec51611 100644
--- a/target/tricore/helper.c
+++ b/target/tr
Add the cpr-transfer migration mode. Usage:
qemu-system-$arch -machine aux-ram-share=on ...
start new QEMU with "-incoming -incoming "
Issue commands to old QEMU:
migrate_set_parameter mode cpr-transfer
{"execute": "migrate", ...
{"channel-type": "main"...}, {"channel-typ
In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass
a zero-initialized float_status struct to float32_is_quiet_nan() and
float64_is_quiet_nan(), with the cryptic comment "for
snan_bit_is_one".
This pattern appears to have been copied from target/riscv, where it
is used because th
Set the default NaN pattern explicitly for s390x.
Signed-off-by: Peter Maydell
---
target/s390x/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index e74055bad79..adb27504ad5 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -209,6 +2
Set the default NaN pattern explicitly for MIPS. Note that this
is our only target which currently changes the default NaN
at runtime (which it was previously doing indirectly when it
changed the snan_bit_is_one setting).
Signed-off-by: Peter Maydell
---
target/mips/fpu_helper.h | 7 +++
tar
In the helper functions flcmps and flcmpd we use a scratch float_status
so that we don't change the CPU state if the comparison raises any
floating point exception flags. Instead of zero-initializing this
scratch float_status, initialize it as a copy of env->fp_status. This
avoids the need to expli
CPR must save state that is needed after QEMU is restarted, when devices
are realized. Thus the extra state cannot be saved in the migration
channel, as objects must already exist before that channel can be loaded.
Instead, define auxilliary state structures and vmstate descriptions, not
associate
Add an option to defer connection to the target monitor, needed by the
cpr-transfer test.
Signed-off-by: Steve Sistare
Reviewed-by: Fabiano Rosas
---
tests/qtest/migration-test.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/tests/qtest/migratio
On 02.12.24 16:41, William Roche wrote:
Hello David,
Hi,
sorry for reviewing yet, I was rather sick the last 1.5 weeks.
I've finally tested many page mapping possibilities and tried to
identify the error injection reaction on these pages to see if mmap()
can be used to recover the impacted
On 1/12/24 16:05, Richard Henderson wrote:
Add gvec interfaces for CLS and CLZ operations.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h | 5 +
target/arm/tcg/gengvec.c| 35 +
target/arm/tcg/translate-a64.c | 29 +++---
On Mon, 2 Dec 2024 at 17:04, Richard Henderson
wrote:
>
> On 12/2/24 07:12, Peter Maydell wrote:
> > Explicitly set a rule in the softfloat tests for the inf-zero-nan
> > muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
> > and so we should select here the Arm rule of
> > floa
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for ARM (and Aarch64) targets. We decided to
treat th
The plugin API allows registration of callbacks for a variety of VCPU
related events, such as VCPU reset, idle and resume. In addition to
those events, we recently defined discontinuity events, which include
traps.
This change introduces a function to register callbacks for these
events. We define
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places the hook for AVR targets. That architecture appears
to only
Set the default NaN pattern explicitly, and remove the ifdef from
parts64_default_nan().
Signed-off-by: Peter Maydell
---
target/microblaze/cpu.c| 2 ++
fpu/softfloat-specialize.c.inc | 3 +--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/cpu.c b/target
Add an option to defer making the connecting to the monitor and qtest
sockets when calling qtest_init_with_env. The client makes the connection
later by calling qtest_connect_deferred and qtest_qmp_handshake.
A test cannot specify port=0 for a deferred connection, because qmp_migrate
cannot query
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
so we can remove the ifdef from pickNaNMulAdd().
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/xtensa/cpu.c| 2 ++
fpu/softfloat-specialize.c.inc | 2 +-
2 files changed, 3 insertions(+), 1 deleti
On 1/12/24 16:05, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 46 --
target/arm/tcg/a64.decode | 4 +++
2 files changed, 25 insertions(+), 25 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
We recently introduced plugin API for the registration of callbacks for
discontinuity events, specifically for interrupts, exceptions and host
call events. The callback receives, among other information, the VCPU
index and the PC after the event. This change introduces a test plugin
asserting that
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for SPARC (32bit and 64bit) targets. We treat
any int
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for MIPS targets.
---
target/mips/tcg/sysemu/tlb_hel
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for Alpha targets.
---
target/alpha/helper.c | 12 ++
The plugin API allows registration of callbacks for a variety of VCPU
related events, such as VCPU reset, idle and resume. However, traps of
any kind, i.e. interrupts or exceptions, were previously not covered.
These kinds of events are arguably quite significant and usually go hand
in hand with a
Some analysis greatly benefits, or depends on, information about
certain types of dicontinuities such as interrupts. For example, we may
need to handle the execution of a new translation block differently if
it is not the result of normal program flow but of an interrupt.
Even with the existing in
The plugin API allows registration of callbacks for a variety of VCPU
related events, such as VCPU reset, idle and resume. In addition, we
recently introduced API for registering callbacks for discontinuity
events, specifically for interrupts, exceptions and host calls.
This change introduces the
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for RISC-V targets.
---
target/riscv/cpu_helper.c |
On 12/2/24 16:54, Corvin Köhne wrote:
> On Mon, 2024-12-02 at 00:09 +0800, Tomita Moeko wrote:
>> CAUTION: External Email!!
>> Both intel documentation [1][2] and i915 driver shows GGMS represents
>> GTT stolen memory size in multiple of 1MB, not 2MB starting from gen
>> 8.
>>
>> [1]
>> https://ww
We recently introduced new plugin API for registration of discontinuity
related callbacks. This change introduces a minimal plugin showcasing
the new API. It simply counts the occurances of interrupts, exceptions
and host calls per CPU and reports the counts when exitting.
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contrib/plugins/meso
On Sun, 2024-12-01 at 22:28 -0700, Alex Williamson wrote:
> CAUTION: External Email!!
> On Mon, 2 Dec 2024 00:09:32 +0800
> Tomita Moeko wrote:
>
> > Add helper functions igd_gtt_memory_size() and igd_stolen_size() for
> > calculating GTT stolen memory and Data stolen memory size in bytes,
> > a
On Mon, Nov 25, 2024 at 9:01 PM Dorjoy Chowdhury wrote:
>
> On Mon, Nov 18, 2024 at 7:13 PM Dorjoy Chowdhury
> wrote:
> >
> > Ping.
> >
>
> Ping...
> This hasn't been reviewed and I think this one simplifies the code in
> eif.c and is quite small.
>
Gentle ping.
Regards,
Dorjoy
ping?
On 29/11/24 11:17, Philippe Mathieu-Daudé wrote:
The 'pci-vga' device allow setting a 'big-endian-framebuffer'
property since commit 3c2784fc864 ("vga: Expose framebuffer
byteorder as a QOM property"). Similarly, the 'virtio-vga'
device since commit 8be61ce2ce3 ("virtio-vga: implement
big-
On Sat, Nov 30, 2024 at 10:01:43PM +0800, Yong Huang wrote:
> On Fri, Nov 29, 2024 at 9:44 PM Fabiano Rosas wrote:
>
> > Fabiano Rosas writes:
> >
> > > Yong Huang writes:
> > >
> > >> On Wed, Oct 23, 2024 at 11:06 PM Fabiano Rosas wrote:
> > >>
> > >>> yong.hu...@smartx.com writes:
> > >>>
>
On Fri, Nov 29, 2024 at 10:19:36AM -0300, Fabiano Rosas wrote:
> Fabiano Rosas writes:
>
> > The current build structure for migration tests is confusing. There is
> > the tests/migration directory, which contains two different guest code
> > implementations, one for the qtests (a-b-{bootblock|ke
Use self_set_machine() to set and check for the availability of the
default pc machine (so that the test is not failing if the machine
has not been included in the QEMU binary).
Message-ID: <20241128120142.593408-1-th...@redhat.com>
Signed-off-by: Thomas Huth
---
tests/functional/test_virtio_ver
On Mon, 2 Dec 2024 at 18:36, Pierrick Bouvier
wrote:
> Maybe our enable-debug should produced optimized builds by default, and
> we could have a new --enable-debug-unopt for the "I need to use a
> debugger" use case. Would save a lot of time for devs, and in CI where
> minutes are precious.
The w
On 12/2/24 07:13, Peter Maydell wrote:
Set the default NaN pattern explicitly for MIPS. Note that this
is our only target which currently changes the default NaN
at runtime (which it was previously doing indirectly when it
changed the snan_bit_is_one setting).
Signed-off-by: Peter Maydell
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