Hi Paolo,
On 22/11/24 08:47, Paolo Bonzini wrote:
The InterruptSource bindings let us call qemu_set_irq() and sysbus_init_irq()
as safe code.
Interrupt sources, qemu_irq in C code, are pointers to IRQState objects.
They are QOM link properties and can be written to outside the control
of the de
On 21/11/2024 17.57, Alex Bennée wrote:
Now there are new upto date images available we should update to them.
Signed-off-by: Alex Bennée
Cc: Anders Roxell
---
tests/functional/test_mipsel_tuxrun.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Thomas Huth
Te
On 21/11/2024 17.57, Alex Bennée wrote:
Now there are new upto date images available we should update to them.
s/upto/up to/ ?
Signed-off-by: Alex Bennée
Cc: Anders Roxell
---
tests/functional/test_mips_tuxrun.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by
On 21/11/2024 17.57, Alex Bennée wrote:
Now there are new upto date images available we should update to them.
Signed-off-by: Alex Bennée
Cc: Anders Roxell
---
tests/functional/test_mips64_tuxrun.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Thomas Huth
Te
Il ven 22 nov 2024, 10:44 David Hildenbrand ha scritto:
> > I think we can check if qdev_get_machine() gets a valid result. If not,
> > fall back to assign nr_cores and nr_threads to 1.
>
> That sounds reasonable to me.
>
Another possibility is to add a cpu_realize() function that sets two
prope
On 21/11/2024 17.57, Alex Bennée wrote:
Now there are new upto date images available we should update to them.
Signed-off-by: Alex Bennée
Cc: Anders Roxell
---
tests/functional/test_mips64el_tuxrun.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Thomas Huth
On 21/11/2024 22.46, Cédric Le Goater wrote:
On 11/21/24 20:10, Thomas Huth wrote:
On 21/11/2024 20.03, Cédric Le Goater wrote:
Hello Alex,
On 11/21/24 17:57, Alex Bennée wrote:
This is a mostly testing focused set of patches but a few bug fixes as
well. I plan to send the PR in on Monday. I
On 11/22/24 11:30, Philippe Mathieu-Daudé wrote:
On 22/11/24 09:32, Paolo Bonzini wrote:
+/// Interrupt sources are used by devices to pass changes to a
boolean value to
+/// other devices (typically interrupt or GPIO controllers). QEMU
interrupt
+/// sources are always active-high.
So 'alw
On Fri, Nov 22, 2024 at 11:17:39AM +0100, Kevin Wolf wrote:
> Am 20.11.2024 um 14:19 hat Peter Maydell geschrieben:
> > On Wed, 20 Nov 2024 at 10:52, Kevin Wolf wrote:
> > >
> > > The following changes since commit
> > > e6459afb1ff4d86b361b14f4a2fc43f0d2b4d679:
> > >
> > > Merge tag 'pull-targ
On 21/11/2024 17.57, Alex Bennée wrote:
Now there are new upto date images available we should update to them.
Signed-off-by: Alex Bennée
Cc: Anders Roxell
---
tests/functional/test_s390x_tuxrun.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Thomas Huth
Tes
On 21/11/2024 17.57, Alex Bennée wrote:
Now there are new upto date images available we should update to them.
Note we re-use the riscv32 kernel and rootfs for test_riscv64_rv32.
Signed-off-by: Alex Bennée
Cc: Anders Roxell
---
tests/functional/test_riscv64_tuxrun.py | 16
On 21/11/2024 17.58, Alex Bennée wrote:
Now there are new upto date images available we should update to them.
Signed-off-by: Alex Bennée
Cc: Anders Roxell
---
tests/functional/test_sparc64_tuxrun.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Thomas Huth
T
Introduce support for the Zhaoxin Yongfeng CPU model.
The Zhaoxin Yongfeng CPU is Zhaoxin's latest server CPU.
This new cpu model ensure that QEMU can correctly emulate the Zhaoxin
Yongfeng CPU, providing accurate functionality and performance characteristics.
Signed-off-by: EwanHai
Reviewed-by:
Em Wed, 20 Nov 2024 14:33:08 +
Jonathan Cameron escreveu:
> On Wed, 13 Nov 2024 09:37:00 +0100
> Mauro Carvalho Chehab wrote:
>
> > Rename: get_ghes_offsets->get_hw_error_offsets
> > to make clear that this function return offsets based on the
> > hardware error firmware.
> >
> > Signed-of
Zhaoxin currently uses two vendors: "Shanghai" and "Centaurhauls".
It is important to note that the latter now belongs to Zhaoxin. Therefore,
this patch replaces CPUID_VENDOR_VIA with CPUID_VENDOR_ZHAOXIN1.
The previous CPUID_VENDOR_VIA macro was only defined but never used in
QEMU, making this ch
Zhaoxin CPUs (including vendors "Shanghai" and "Centaurhauls") handle the
CMPLegacy bit similarly to Intel CPUs. Therefore, this commit masks the
CMPLegacy bit in CPUID[0x8001].ECX for Zhaoxin CPUs, just as it is done
for Intel CPUs.
AMD uses the CMPLegacy bit (CPUID[0x8001].ECX.bit1) alon
Add new CPUID feature flags for various Zhaoxin PadLock extensions.
These definitions will be used for Zhaoxin CPU models.
Signed-off-by: EwanHai
Reviewed-by: Zhao Liu
---
target/i386/cpu.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/i386/cpu.h b/target/i38
This patch series introduces support for the Zhaoxin Yongfeng CPU model and
includes improvements and updates specific to Zhaoxin CPUs (including vendor
"Centaurhauls" and "Shanghai"). The changes ensure that QEMU can correctly
identify and emulate Zhaoxin CPUs, accurately reflecting their function
On 11/22/24 09:21, Thomas Huth wrote:
On 22/11/2024 08.33, Cédric Le Goater wrote:
Drop the SSH connection which was introduced in the avocado tests to
workaround read issues when interacting with console.
EXTRA_BOOTARGS was introduced to reduce the console output at Linux
boot time. This didn'
Drop the SSH connection which was introduced in the avocado tests to
workaround read issues when interacting with console.
Signed-off-by: Cédric Le Goater
Reviewed-by: Thomas Huth
---
tests/avocado/machine_aspeed.py | 78
tests/functional/meson.build| 2
These were introduced in the avocado tests to workaround read issues
when interacting with console. They are no longer necessary and we can
use the expected "login:" string or the command prompt now. Drop the
last use of exec_command.
Signed-off-by: Cédric Le Goater
Reviewed-by: Thomas Huth
---
Hello,
This series completes the conversion of the Aspeed tests to the new
functional framework and removes the workarounds for capturing the
console output.
Thanks,
C.
Changes in v3:
- Required 'user' netdev in do_test_aarch64_aspeed_sdk_start() and
do_test_arm_aspeed_sdk_start()
Cha
Drop the SSH connection which was introduced in the avocado tests to
workaround read issues when interacting with console.
EXTRA_BOOTARGS was introduced to reduce the console output at Linux
boot time. This didn't have the desired effect as we still had issues
when trying to match patterns on the
Currently, CPER address location is calculated as an offset of
the hardware_errors table. It is also badly named, as the
offset actually used is the address where the CPER data starts,
and not the beginning of the error source.
Move the logic which calculates such offset to a separate
function, in
acpi_ghes_record_errors() has an assert() at the beginning
to ensure that source_id will be lower than
ACPI_GHES_ERROR_SOURCE_COUNT. Remove a duplicated check.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes.c | 4 +---
1 file chan
GHES has two fields that are stored on HEST error source
blocks associated with notifications:
- notification type, which is a number defined at the ACPI spec
containing several arch-specific synchronous and assynchronous
types;
- source id, which is a HW/FW defined number, used to distinguish
The GHES driver requires not only a HEST table, but also a
separate firmware file to store Error Structure records.
It can't do one without the other.
Simplify the caller logic for it to require one function.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Came
This is just duplicating ACPI_GHES_ERROR_SOURCE_COUNT, which
has a better name. So, drop the duplication.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes.c | 7 ++-
include/hw/acpi/ghes.h | 3 ++-
2 files changed, 4 ins
The current function used to generate GHES data is specific for
memory errors. Give a better name for it, as we now have a generic
function as well.
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes-stub.c| 2 +-
hw/acpi/ghes.c
Reduce the ident of the function and prepares it for
the next changes.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes.c | 56 ++
1 file changed, 29 insertions
The hardware error firmware is where HEST error structures are
stored. Those can be GHESv2, but they can also be other types.
Better name the location of the hardware error.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
--
Extending to multiple sources require a BIOS pointer to the
beginning of the HEST table, which in turn requires a backward-compatible
code.
So, the current code supports only one source. Ensure that and simplify
the code.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
---
h
On 22.11.24 03:40, Xiaoyao Li wrote:
On 11/22/2024 2:52 AM, Paolo Bonzini wrote:
On 11/21/24 17:24, Xiaoyao Li wrote:
Could it go into cpu_common_initfn()?
It can, I think.
I'll move them into cpu_common_initfn() in v2 to avoid touching all
the ARCHes.
It does look better than the alternat
> On 21 Nov 2024, at 22:54, Atish Kumar Patra wrote:
>
> On Wed, Nov 20, 2024 at 6:25 AM Aleksei Filippov
> wrote:
>>
>>
>>
>>> On 22 Oct 2024, at 15:58, Atish Kumar Patra wrote:
>>>
>>> On Mon, Oct 21, 2024 at 6:45 AM Aleksei Filippov
>>> wrote:
> On 11 Oct 2024,
On 21/11/2024 17.57, Alex Bennée wrote:
Now there are new upto date images available we should update to them.
Signed-off-by: Alex Bennée
Cc: Anders Roxell
---
tests/functional/test_riscv32_tuxrun.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Thomas Huth
T
On 11/22/24 11:47, Thomas Huth wrote:
On 21/11/2024 22.46, Cédric Le Goater wrote:
On 11/21/24 20:10, Thomas Huth wrote:
On 21/11/2024 20.03, Cédric Le Goater wrote:
Hello Alex,
On 11/21/24 17:57, Alex Bennée wrote:
This is a mostly testing focused set of patches but a few bug fixes as
well.
On 21/11/2024 17.57, Alex Bennée wrote:
Now there are new upto date images available we should update to them.
Signed-off-by: Alex Bennée
Cc: Anders Roxell
---
tests/functional/test_ppc64_tuxrun.py | 16
1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Thomas
On Fri, 22 Nov 2024 08:01:34 +0100
Philippe Mathieu-Daudé wrote:
> Hi Wafer,
>
> On 22/11/24 03:00, Wafer wrote:
> > From: Wafer Xie
> >
> > The virtio-1.2 specification writes:
> >
> > 2.7.6 The Virtqueue Available Ring:
> > "idx field indicates where the driver would put the next descriptor
On Thu, Nov 21, 2024 at 10:43 PM Erwin Jansen wrote:
>
> Would a good next step be to work out some more details in a document that
> outlines what process we are using, what we are planning to do and include a
> set of suggestions as a starting point to see if we can upstream some of the
> cha
While looking at the QEMU binary with "pahole", I noticed that we
could optimize the size of MachineClass a little bit: So far we
are using a mixture of a bitfield and single "bool" members here
for the boolean flags. Declaring all flags as part of the bitfield
helps to shrink the size of the struc
Am 20.11.2024 um 14:19 hat Peter Maydell geschrieben:
> On Wed, 20 Nov 2024 at 10:52, Kevin Wolf wrote:
> >
> > The following changes since commit e6459afb1ff4d86b361b14f4a2fc43f0d2b4d679:
> >
> > Merge tag 'pull-target-arm-20241119' of
> > https://git.linaro.org/people/pmaydell/qemu-arm into s
On 21/11/2024 17.57, Alex Bennée wrote:
From: Daniel P. Berrangé
If a failure occurs early in the QemuBaseTest constructor, the
'log_filename' object atttribute may not exist yet. This happens
s/atttribute/attribute/
most notably if the QEMU_TEST_QEMU_BINARY is not set. We can't
initialize
On 21/11/2024 17.57, Alex Bennée wrote:
This is a mostly testing focused set of patches but a few bug fixes as
well. I plan to send the PR in on Monday. I can drop any patches that
are objected to but I think its pretty safe.
Contains:
- Daniel's clean-up of functional tests
- Another avo
On 21/11/2024 17.57, Alex Bennée wrote:
We didn't have this before and as it exercises the m68k virt platform
it seems worth adding. We don't wait for the shutdown because QEMU
will auto-exit on the shutdown.
Signed-off-by: Alex Bennée
Cc: Laurent Vivier
Cc: Anders Roxell
---
tests/function
On Fri, Nov 22, 2024 at 11:17:39AM +0100, Kevin Wolf wrote:
> Am 20.11.2024 um 14:19 hat Peter Maydell geschrieben:
> > On Wed, 20 Nov 2024 at 10:52, Kevin Wolf wrote:
> > >
> > > The following changes since commit
> > > e6459afb1ff4d86b361b14f4a2fc43f0d2b4d679:
> > >
> > > Merge tag 'pull-targ
On 21/11/2024 17.57, Alex Bennée wrote:
Now there are new upto date images available we should update to them.
Signed-off-by: Alex Bennée
Cc: Anders Roxell
---
tests/functional/test_arm_tuxrun.py | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
Reviewed
Last use of pci_irq_pulse() was removed 7 years ago in commit
5e9aa92eb1 ("hw/block: Fix pin-based interrupt behaviour of NVMe").
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci/pci.h | 10 --
1 file changed, 10 deletions(-)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pc
On 22/11/24 11:53, Paolo Bonzini wrote:
On 11/22/24 11:30, Philippe Mathieu-Daudé wrote:
On 22/11/24 09:32, Paolo Bonzini wrote:
+/// Interrupt sources are used by devices to pass changes to a
boolean value to
+/// other devices (typically interrupt or GPIO controllers). QEMU
interrupt
+///
On 21/11/2024 17.57, Alex Bennée wrote:
Now there are new upto date images available we should update to them.
Signed-off-by: Alex Bennée
Cc: Anders Roxell
---
tests/functional/test_i386_tuxrun.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Thomas Huth
Test
On 21/11/2024 17.58, Alex Bennée wrote:
Now there are new upto date images available we should update to them.
Signed-off-by: Alex Bennée
Cc: Anders Roxell
---
tests/functional/test_x86_64_tuxrun.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Thomas Huth
Te
Call scsi_bus_legacy_handle_cmdline() once in the DeviceRealize
handler, just after scsi_bus_init().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/m68k/next-cube.c | 2 --
hw/m68k/q800.c | 2 --
hw/mips/jazz.c | 2 --
hw/scsi/esp.c | 1 +
hw/sparc/sun4m.c| 1 -
5 files changed
When a device model requires legacy command line handling,
call scsi_bus_legacy_handle_cmdline() in its realize handler
instead of having each user call it.
This applies to:
- spapr_vscsi
- lsi53c810 / lsi53c895a
- sysbus_esp
Note, scsi_bus_legacy_handle_cmdline() prototype could be
made priva
Call scsi_bus_legacy_handle_cmdline() in the DeviceRealize
handler, just after scsi_bus_init().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/scsi/spapr_vscsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c
index c75a6c8807..
On 22/11/2024 08.33, Cédric Le Goater wrote:
Drop the SSH connection which was introduced in the avocado tests to
workaround read issues when interacting with console.
EXTRA_BOOTARGS was introduced to reduce the console output at Linux
boot time. This didn't have the desired effect as we still h
On 11/22/24 08:05, Michael Tokarev wrote:
Maybe a more general question would be:
what is our main build entry point? Is it `make` (or `make all`)
still, or is it meson now?
s/meson/ninja/
But no, it's always make. Using make ensures that:
1) you build stuff that is not emulators (option RO
Em Wed, 20 Nov 2024 14:18:38 +
Jonathan Cameron escreveu:
> On Tue, 12 Nov 2024 11:14:52 +0100
> Mauro Carvalho Chehab wrote:
>
> > Split the code into separate functions to allow using the
> > common CPER filling code by different error sources.
> >
> > The generic code was moved to ghes_
> > +/// Interrupt sources are used by devices to pass changes to a boolean
> > value to
> > +/// other devices (typically interrupt or GPIO controllers). QEMU
> > interrupt
> > +/// sources are always active-high.
>
> So 'always active-high' = true below? (Wondering about pulsation, if the
> tr
During the development of a patch series meant to allow GHESv2 error injections,
it was requested a change on how CPER offsets are calculated, by adding a new
BIOS pointer and reworking the GHES logic. See:
https://lore.kernel.org/qemu-devel/cover.1726293808.git.mchehab+hua...@kernel.org/
Such ch
As described at: ACPI 6.5 spec at:
18.3.2. ACPI Error Source
In particular at GHES/GHESv2 table:
Table 18.10 Generic Hardware Error Source Structure
HEST source ID is actually a 16-bit value.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes-s
While the spec defines a CPER size of 4KiB for each record,
currently it is set to 1KiB. Fix the documentation and add
a pointer to the macro name there, as this may help to keep
it updated.
Signed-off-by: Mauro Carvalho Chehab
Acked-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
docs/spe
Align the header file with the actual implementation of
this function, as the first argument is source ID and not
notification type.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
Changes from v8:
- Non-rename/cleanup changes merged altogethe
Split the code into separate functions to allow using the
common CPER filling code by different error sources.
The generic code was moved to ghes_record_cper_errors(),
and ghes_gen_err_data_uncorrectable_recoverable() now contains
only a logic to fill the Generic Error Data part of the record,
as
Make error handling within ghes_record_cper_errors() consistent,
i.e. instead abort just print a error in case ghes GED is not found.
Reviewed-by: Jonathan Cameron
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/
Now that we have also have a file to store HEST data location,
which is part of GHES, better name the file where CPER records
are stored.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes.c | 38 ++
Em Wed, 20 Nov 2024 14:59:30 +
Jonathan Cameron escreveu:
> On Wed, 13 Nov 2024 09:37:01 +0100
> Mauro Carvalho Chehab wrote:
>
> > There are two pointers that are needed during error injection:
> >
> > 1. The start address of the CPER block to be stored;
> > 2. The address of the ack, whi
On 22/11/24 09:32, Paolo Bonzini wrote:
+/// Interrupt sources are used by devices to pass changes to a boolean value to
+/// other devices (typically interrupt or GPIO controllers). QEMU interrupt
+/// sources are always active-high.
So 'always active-high' = true below? (Wondering about puls
Em Wed, 20 Nov 2024 15:01:19 +
Jonathan Cameron escreveu:
> On Wed, 13 Nov 2024 09:37:02 +0100
> Mauro Carvalho Chehab wrote:
>
> > The GHES migration logic at GED should now support HEST table
> > location too.
> >
> > Increase migration version and change needed to check for both
> > ghe
On 21/11/2024 17.57, Alex Bennée wrote:
Now there are new upto date images available we should update to them.
Signed-off-by: Alex Bennée
Cc: Anders Roxell
---
tests/functional/test_ppc_tuxrun.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Thomas Huth
Teste
On 21/11/2024 18.31, Alex Bennée wrote:
Peter Maydell writes:
On Thu, 21 Nov 2024 at 16:58, Alex Bennée wrote:
This is a mostly testing focused set of patches but a few bug fixes as
well. I plan to send the PR in on Monday. I can drop any patches that
are objected to but I think its pretty
Call scsi_bus_legacy_handle_cmdline() once in the DeviceRealize
handler, just after scsi_bus_init().
No need for lsi53c8xx_handle_legacy_cmdline(), remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci/pci.h | 2 --
hw/arm/realview.c| 3 +--
hw/arm/versatilepb.c | 3 +--
hw/hpp
On 22/11/2024 11.34, Philippe Mathieu-Daudé wrote:
Last use of pci_irq_pulse() was removed 7 years ago in commit
5e9aa92eb1 ("hw/block: Fix pin-based interrupt behaviour of NVMe").
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci/pci.h | 10 --
1 file changed, 10 deletions(-)
Create a new property (x-has-hest-addr) and use it to detect if
the GHES table offsets can be calculated from the HEST address
(qemu 9.2 and upper) or via the legacy way via an offset obtained
from the hardware_errors firmware file.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/generic_event_
The current code is actually dependent on having just one error
structure with a single source.
As the number of sources should be arch-dependent, as it will depend on
what kind of synchronous/assynchronous notifications will exist, change
the logic to dynamically build the table.
Yet, for a prop
Store HEST table address at GPA, placing its content at
hest_addr_le variable.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
---
Change from v8:
- hest_addr_lr is now pointing to the error source size and data.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c
There are two pointers that are needed during error injection:
1. The start address of the CPER block to be stored;
2. The address of the ack, which needs a reset before next error.
It is preferable to calculate them from the HEST table. This allows
checking the source ID, the size of the table
This series was part of the previous PR to add generic error injection
support on GHES. It depends on a cleanup patch series sent earlier
today:
https://lore.kernel.org/qemu-devel/cover.1732266152.git.mchehab+hua...@kernel.org/T/#t
It contains the changes of the math used to calculate o
On 11/22/24 14:49, Thomas Huth wrote:
On 22/11/2024 14.08, Cédric Le Goater wrote:
These were introduced in the avocado tests to workaround read issues
when interacting with console. They are no longer necessary and we can
use the expected login string instead.
Signed-off-by: Cédric Le Goater
On 22/11/2024 14.52, Cédric Le Goater wrote:
On 11/22/24 14:49, Thomas Huth wrote:
On 22/11/2024 14.08, Cédric Le Goater wrote:
These were introduced in the avocado tests to workaround read issues
when interacting with console. They are no longer necessary and we can
use the expected login stri
On Tue, 19 Nov 2024 18:02:54 +0800
bibo mao wrote:
> On 2024/11/19 上午12:43, Igor Mammedov wrote:
> > On Tue, 12 Nov 2024 10:17:35 +0800
> > Bibo Mao wrote:
> >
> >> Here generic function virt_init_cpu_irq() is added to init interrupt
> >> pin of CPU object, IPI and extioi interrupt controller
Am 13.11.2024 um 13:55 hat Richard W.M. Jones geschrieben:
> From: Jakub Jelen
>
> The libssh does not handle non-blocking mode in SFTP correctly. The
> driver code already changes the mode to blocking for the SFTP
> initialization, but for some reason changes to non-blocking mode.
> This used to
From: Patrick Eads
init
Promising polling initiated and data moving cursor now
Reverted delete of dev handler for wacom tablet
got the y-axis!
getting closer
more progress. it appears to not quite be WACOM II/IV, but x-axis is controlled
by the first 2-3 bytes
really? 12-bits is the key? o
On 11/20/24 19:49, Anton Johansson wrote:
Adds a meson option for enabling/disabling helper-to-tcg along with a
CONFIG_* definition.
CONFIG_* will in future commits be used to conditionally include the
helper-to-tcg subproject, and to remove unneeded code/memory when
helper-to-tcg is not in use.
On 11/22/24 13:37, Thomas Huth wrote:
On 22/11/2024 12.19, Philippe Mathieu-Daudé wrote:
When a device model requires legacy command line handling,
call scsi_bus_legacy_handle_cmdline() in its realize handler
instead of having each user call it.
This applies to:
- spapr_vscsi
- lsi53c810 /
On Fri, 15 Nov 2024 16:50:38 +, Peter Maydell wrote:
> I noticed while reviewing Roque's patchset that adds tests
> for the CMSDK watchdog device that we are gradually accumulating
> tests in tests/qtest which open-code "now reset the QEMU system".
> Moreover, several of those tests get it wron
On 11/22/24 13:32, Thomas Huth wrote:
On 22/11/2024 12.59, Cédric Le Goater wrote:
On 11/22/24 11:47, Thomas Huth wrote:
On 21/11/2024 22.46, Cédric Le Goater wrote:
On 11/21/24 20:10, Thomas Huth wrote:
On 21/11/2024 20.03, Cédric Le Goater wrote:
Hello Alex,
On 11/21/24 17:57, Alex Bennée
These were introduced in the avocado tests to workaround read issues
when interacting with console. They are no longer necessary and we can
use the expected login string instead.
Signed-off-by: Cédric Le Goater
---
tests/functional/test_sh4_tuxrun.py | 8 +++-
1 file changed, 3 insertions(+)
On Thu, 7 Nov 2024 22:00:17 +0800
Zhao Liu wrote:
> Hi Igor,
>
> > > What's the difference between arch_id and CPU index (CPUState.cpu_index)?
> > >
> >
> > They might be the same but not necessarily.
> > arch_id is unique cpu identifier from architecture point of view
> > (which easily coul
Peter Xu writes:
> To move towards explicit creations of containers, starting that by
> providing a helper for creating container objects.
>
> Signed-off-by: Peter Xu
Reviewed-by: Markus Armbruster
Peter Maydell writes:
> In the device and drive plug/unplug tests we want to trigger
> a system reset and then see if we get the appropriate
> DEVICE_DELETED event. Use qtest_system_reset_nowait() here.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Fabiano Rosas
These were introduced in the avocado tests to workaround read issues
when interacting with console. They are no longer necessary and we can
use the expected login string instead.
Test always passes now. Remove skipUnless test on QEMU_TEST_FLAKY_TESTS.
Signed-off-by: Cédric Le Goater
---
tests/f
On 22/11/24 17:03, Xiaoyao Li wrote:
Currently cpu->nr_cores and cpu->nr_threads are initialized in
qemu_init_vcpu(), which is called a bit late in *cpu_realizefn() for
each ARCHes.
x86 arch would like to use nr_cores and nr_threads earlier in its
realizefn(). To serve this purpose, initialize n
On Fri, Nov 22, 2024 at 3:43 AM Aleksei Filippov
wrote:
>
>
>
> > On 21 Nov 2024, at 22:54, Atish Kumar Patra wrote:
> >
> > On Wed, Nov 20, 2024 at 6:25 AM Aleksei Filippov
> > wrote:
> >>
> >>
> >>
> >>> On 22 Oct 2024, at 15:58, Atish Kumar Patra wrote:
> >>>
> >>> On Mon, Oct 21, 2024 at 6:
> -Original Message-
> From: Nathan Chen
> Sent: Friday, November 22, 2024 1:42 AM
> To: Shameerali Kolothum Thodi
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org;
> eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nvidia.com;
> ddut...@redhat.com; Linuxarm ; Wangzhou (B)
> ; jian
On 11/20/24 19:49, Anton Johansson wrote:
Adds necessary helper functions for mapping LLVM IR onto TCG.
Specifically, helpers corresponding to the bitreverse and funnel-shift
intrinsics in LLVM.
Note: these may be converted to more efficient implementations in the
future, but for the time being
On 11/20/24 19:49, Anton Johansson wrote:
Adds new functions to the gvec API for truncating, sign- or zero
extending vector elements. Currently implemented as helper functions,
these may be mapped onto host vector instructions in the future.
For the time being, allows translation of more compli
On 11/20/24 19:49, Anton Johansson wrote:
Introduces a new python helper script to convert a set of QEMU .c files to
LLVM IR .ll using clang. Compile flags are found by looking at
compile_commands.json, and llvm-link is used to link together all LLVM
modules into a single module.
Signed-off-by:
On 11/20/24 19:49, Anton Johansson wrote:
Adds a functions to return the current mmu index given tb_flags of the
current translation block. Required by helper-to-tcg in order to
retrieve the mmu index for memory operations without changing the
signature of helper functions.
Signed-off-by: Anton
On 11/20/24 19:49, Anton Johansson wrote:
Temporary vectors in helper-to-tcg generated code are allocated from an
array of bytes in CPUArchState, specified with --temp-vector-block.
This commits adds such a block of memory to CPUArchState, if
CONFIG_HELPER_TO_TCG is set.
Signed-off-by: Anton Jo
On 11/21/24 10:58, Alex Bennée wrote:
From: Pierrick Bouvier
Fixes: 4a448b148ca ("plugins: add qemu_plugin_num_vcpus function")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Pierrick Bouvier
Message-Id: <20241112212622.3590693-2-pierrick.bouv...@linaro.org>
Signed-off-by: Alex Bennée
--
On 11/21/24 11:16, Michael Tokarev wrote:
According to Cortex-R5 r1p2 manual, register with opcode2=0 is
BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
qemu labels them. Just swap the labels to avoid confusion, -
both registers are implemented as always-zero.
Signed-off-by: Mi
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