Re: [RFC v4 2/2] target/riscv: rvv: improve performance of RISC-V vector loads and stores on large amounts of data.

On 11/11/24 08:04, Paolo Savini wrote: Hi Richard, Daniel, This might be a silly question, but why do we need to ensure atomicity when emulating these guest instructions? I might be wrong but I didn't see an explicit requirement for the vector instructions to be atomic in the documentation of

[PATCH v2 21/54] accel/tcg: Delay plugin adjustment in probe_access_internal

Remove force_mmio and place the expression into the IF expression, behind the short-circuit logic expressions that might eliminate its computation. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/accel/tcg/c

[PATCH v2 38/54] target/m68k: Convert to TCGCPUOps.tlb_fill_align

Signed-off-by: Richard Henderson --- target/m68k/cpu.h| 7 --- target/m68k/cpu.c| 2 +- target/m68k/helper.c | 22 +- 3 files changed, 18 insertions(+), 13 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index b5bbeedb7a..4401426a0b 100644 --- a/

Re: [PATCH 6/6] linux-user/ppc: Reduce vdso alignment to 4k

On 12/11/24 20:37, Richard Henderson wrote: Signed-off-by: Richard Henderson --- linux-user/ppc/Makefile.vdso | 6 -- linux-user/ppc/vdso-32.so| Bin 3020 -> 3020 bytes linux-user/ppc/vdso-64.so| Bin 3896 -> 3896 bytes linux-user/ppc/vdso-64le.so | Bin 3896 -> 3896 bytes 4

[PATCH v2 23/54] accel/tcg: Check original prot bits for read in atomic_mmu_lookup

In the mist before CPUTLBEntryFull existed, we had to be clever to detect write-only pages. Now we can directly test the saved prot bits, which is clearer. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/accel/tcg

[PATCH v2 12/54] accel/tcg: Remove IntervalTree entries in tlb_flush_range_locked

Flush a masked range of pages from the IntervalTree cache. When the mask is not used there is a redundant comparison, but that is better than duplicating code at this point. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 25 + 1 file changed, 25 insertions(+)

[PATCH v2 54/54] accel/tcg: Return CPUTLBEntryTree from tlb_set_page_full

Avoid a lookup to find the node that we have just inserted. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 14 ++ 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 20af48c6c5..6d316e8767 100644 --- a/accel/tcg/cputl

[PATCH v2 28/54] accel/tcg: Introduce tlb_lookup

Unify 3 instances of tlb lookup, through tlb_hit, tlbtree_hit, and tlb_full_align. Use structures to avoid too many arguments. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 369 ++--- 1 file changed, 178 insertions(+), 191 deletions(-) diff -

Re: [PATCH ssh] ssh: Do not switch session to non-blocking mode

Hello, comments inline below. On Thu, Nov 14, 2024 at 4:21 PM Kevin Wolf wrote: > [...] > > > I'll just note that I'm only forwarding on the patch from Jakub. > > I didn't write it. > > > > I did lightly test it, and it seems to work. However it seems also > > likely that it is causing qemu to b

[PATCH v2 45/54] target/rx: Convert to TCGCPUOps.tlb_fill_align

Signed-off-by: Richard Henderson --- target/rx/cpu.c | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65a74ce720..c83a582141 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -161,16 +161,19 @@ static void rx_cpu_

[PATCH v2 49/54] target/tricore: Convert to TCGCPUOps.tlb_fill_align

Signed-off-by: Richard Henderson --- target/tricore/cpu.h| 7 --- target/tricore/cpu.c| 2 +- target/tricore/helper.c | 19 --- 3 files changed, 17 insertions(+), 11 deletions(-) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 220af69fc2..5f141ce8f3 1

[PATCH v2 25/54] accel/tcg: Return CPUTLBEntryFull not pointer in probe_access_full_mmu

Return a copy of the structure, not a pointer. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 2 +- accel/tcg/cputlb.c | 13 - target/arm/ptw.c | 10 +- target/i386/tcg/sysemu/excp_helper.c | 8 4 f

[PATCH v2 44/54] target/riscv: Convert to TCGCPUOps.tlb_fill_align

Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 8 +--- target/riscv/cpu_helper.c | 22 +- target/riscv/tcg/tcg-cpu.c | 2 +- 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 284b112821..f97c

[PATCH v2 52/54] accel/tcg: Unexport tlb_set_page*

The new tlb_fill_align hook returns page data via structure rather than by function call, so we can make tlb_set_page_full be local to cputlb.c. There are no users of tlb_set_page or tlb_set_page_with_attrs, so those can be eliminated. Signed-off-by: Richard Henderson --- include/exec/exec-all.

[PATCH v2 16/54] accel/tcg: Pass full addr to victim_tlb_hit

Do not mask the address to the page in these calls. It is easy enough to use a different helper instead. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 7ecd3

[PATCH v2 41/54] target/mips: Convert to TCGCPUOps.tlb_fill_align

Signed-off-by: Richard Henderson --- target/mips/tcg/tcg-internal.h | 6 +++--- target/mips/cpu.c | 2 +- target/mips/tcg/sysemu/tlb_helper.c | 29 - 3 files changed, 24 insertions(+), 13 deletions(-) diff --git a/target/mips/tcg/tcg-internal.

Re: [PATCH v3 0/2] qdev-monitor: avoid QemuOpts in QMP device_add()

Am 27.08.2024 um 21:27 hat Stefan Hajnoczi geschrieben: > v3: > - Duplicate drain_call_rcu() into hmp_device_add() because moving it into > qdev_device_add_from_qdict turned out to be unsafe. > v2: > - Rename Patch 1 to indicate that we're avoiding QemuOpts rather than doing a > full conversion

[PULL 4/8] iotests: correct resultclass type in ReproducibleTestRunner

From: John Snow I have a vague memory that I suggested this base class to Vladimir and said "Maybe someday it will break, and I'll just fix it then." Guess that's today. Fixes various mypy errors in the "make check-tox" python test for at least Python3.8; seemingly requires a fairly modern mypy

[PATCH v2 51/54] accel/tcg: Drop TCGCPUOps.tlb_fill

Now that all targets have been converted to tlb_fill_align, remove the tlb_fill hook. Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 10 -- accel/tcg/cputlb.c| 19 --- 2 files changed, 4 insertions(+), 25 deletions(-) diff --git a/includ

[PATCH v2 40/54] target/microblaze: Convert to TCGCPUOps.tlb_fill_align

Signed-off-by: Richard Henderson --- target/microblaze/cpu.h| 7 +++ target/microblaze/cpu.c| 2 +- target/microblaze/helper.c | 33 - 3 files changed, 24 insertions(+), 18 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h i

[PATCH v2 27/54] accel/tcg: Return CPUTLBEntryFull not pointer in probe_access_internal

Return a copy of the structure, not a pointer. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 40 ++-- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 84e7e633e3..41b2f76cc9 100644 --- a/

[PULL 5/8] python: disable too-many-positional-arguments warning

From: John Snow Newest versions of pylint complain about specifically positional arguments in addition to too many in general. We already disable the general case, so silence this new warning too. Signed-off-by: John Snow Message-ID: <20241101173700.965776-4-js...@redhat.com> Reviewed-by: Kevin

[PULL 8/8] vl: use qmp_device_add() in qemu_create_cli_devices()

From: Stefan Hajnoczi qemu_create_cli_devices() should use qmp_device_add() to match the behavior of the QMP monitor. A comment explained that libvirt changes implementing strict CLI syntax were needed. Peter Krempa has confirmed that modern libvirt uses the same JSON for -device (CLI) and devi

[PULL 1/8] migration: Check current_migration in migration_is_running()

From: Peter Xu Report shows that commit 34a8892dec broke iotest 055: https://lore.kernel.org/r/b8806360-a2b6-4608-83a3-db67e264c...@linaro.org When replacing migration_is_idle() with "!migration_is_running()", it was overlooked that the idle helper also checks for current_migration being availa

[PULL 0/8] Block layer patches

The following changes since commit f0a5a31c33a8109061c2493e475c8a2f4d022432: Update version for v9.2.0-rc0 release (2024-11-13 21:44:45 +) are available in the Git repository at: https://repo.or.cz/qemu/kevin.git tags/for-upstream for you to fetch changes up to 378a645b2f6125b1bdbd1fae3

Re: [PATCH 2/6] linux-user: Drop image_info.alignment

On 12/11/24 20:37, Richard Henderson wrote: This field is write-only. Use only the function-local variable within load_elf_image. Signed-off-by: Richard Henderson --- linux-user/qemu.h| 1 - linux-user/elfload.c | 7 +++ 2 files changed, 3 insertions(+), 5 deletions(-) Reviewed-b

[PULL 6/8] python: silence pylint raising-non-exception error

From: John Snow As of (at least) pylint 3.3.1, this code trips pylint up into believing we are raising something other than an Exception. We are not: the first two values may indeed be "None", but the last and final value must by definition be a SystemExit exception. Signed-off-by: John Snow Me

[PULL 3/8] iotests: reflow ReproducibleTestRunner arguments

From: John Snow Trivial reflow to let the type names breathe. (I need to add a longer type name.) Signed-off-by: John Snow Message-ID: <20241101173700.965776-2-js...@redhat.com> Reviewed-by: Kevin Wolf Signed-off-by: Kevin Wolf --- tests/qemu-iotests/iotests.py | 11 +++ 1 file chan

[PATCH 2/2] arm/ptw: respect sctlr.{u}wxn in get_phys_addr_v6

get_phys_addr_v6() is used for decoding armv7's short descriptor format. Based on ARM ARM AArch32.S1SDHasPermissionsFault(), WXN should be respected in !LPAE mode as well. Signed-off-by: Pavel Skripkin --- target/arm/ptw.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/a

[PATCH 1/2] arm/ptw: factor out wxn logic to separate functions

The next patch will add support for WXN for short descriptor format. To prevent code duplication, wxn logic was factored out to separate functions. Signed-off-by: Pavel Skripkin --- target/arm/ptw.c | 41 +++-- 1 file changed, 23 insertions(+), 18 deletions(-)

[PULL 7/8] qdev-monitor: avoid QemuOpts in QMP device_add

From: Stefan Hajnoczi The QMP device_add monitor command converts the QDict arguments to QemuOpts and then back again to QDict. This process only supports scalar types. Device properties like virtio-blk-pci's iothread-vq-mapping (an array of objects) are silently dropped by qemu_opts_from_qdict()

[PULL 2/8] parallels: fix possible int overflow

From: Dmitry Frolov The sum "cluster_index + count" may overflow uint32_t. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Dmitry Frolov Message-ID: <20241106080521.219255-2-fro...@swemel.ru> Reviewed-by: Kevin Wolf Signed-off-by: Kevin Wolf --- block/parall

[PATCH 1/2] arm/ptw: factor out wxn logic to separate functions

The next patch will add support for WXN for short descriptor format. To prevent code duplication, wxn logic was factored out to separate functions. Signed-off-by: Pavel Skripkin --- target/arm/ptw.c | 41 +++-- 1 file changed, 23 insertions(+), 18 deletions(-)

Re: [PATCH v4 7/7] target/i386: Add EPYC-Genoa model to support Zen 4 processor series

On 11/13/24 10:23, Moger, Babu wrote: > Adding Paolo. > > On 11/12/24 04:09, Maksim Davydov wrote: >> >> >> On 11/8/24 23:56, Moger, Babu wrote: >>> Hi Maxim, >>> >>> Thanks for looking into this. I will fix the bits I mentioned below in >>> upcoming Genoa/Turin model update. >>> >>> I have few

[PATCH v2 42/54] target/openrisc: Convert to TCGCPUOps.tlb_fill_align

Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 8 +--- target/openrisc/cpu.c | 2 +- target/openrisc/mmu.c | 39 +-- 3 files changed, 27 insertions(+), 22 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index c9fe9ae

Re: [PATCH 5/6] linux-user/loongarch64: Reduce vdso alignment to 4k

On 12/11/24 20:37, Richard Henderson wrote: Signed-off-by: Richard Henderson --- linux-user/loongarch64/Makefile.vdso | 3 ++- linux-user/loongarch64/vdso.so | Bin 3560 -> 3560 bytes 2 files changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 03/24] exec/translation-block: Include missing 'exec/vaddr.h' header

On 11/14/24 07:23, Philippe Mathieu-Daudé wrote: On 14/11/24 04:10, Pierrick Bouvier wrote: On 11/13/24 17:12, Philippe Mathieu-Daudé wrote: 'vaddr' is declared in "exec/vaddr.h". Include it in order to avoid when refactoring:    include/exec/translation-block.h:56:5: error: unknown type name

[PATCH for-10.0 v2 00/54] accel/tcg: Convert victim tlb to IntervalTree

v1: 20241009150855.804605-1-richard.hender...@linaro.org The initial idea was: how much can we do with an intelligent data structure for the same cost as a linear search through an array? r~ Richard Henderson (54): util/interval-tree: Introduce interval_tree_free_nodes accel/tcg: Split out

[PATCH v2 07/54] accel/tcg: Assert bits in range in tlb_flush_range_by_mmuidx*

The only target that does not use TARGET_LONG_BITS is Arm, which only reduces bits based on TBI. There is no point in handling odd combinations of parameters. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --

[PATCH v2 09/54] accel/tcg: Add IntervalTreeRoot to CPUTLBDesc

Add the data structures for tracking softmmu pages via a balanced interval tree. So far, only initialize and destroy the data structure. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 +++ accel/tcg/cputlb.c| 11 +++ 2 files changed, 14 insertions(+) diff --git a/i

Re: [PATCH 4/6] linux-user/arm: Reduce vdso alignment to 4k

On 12/11/24 20:37, Richard Henderson wrote: Signed-off-by: Richard Henderson --- linux-user/arm/Makefile.vdso | 2 +- linux-user/arm/vdso-be.so| Bin 2648 -> 2648 bytes linux-user/arm/vdso-le.so| Bin 2648 -> 2648 bytes 3 files changed, 1 insertion(+), 1 deletion(-) Reviewed-by:

Re: [PATCH ssh] ssh: Do not switch session to non-blocking mode

Am 14.11.2024 um 17:49 hat Jakub Jelen geschrieben: > Hello, > comments inline below. > > On Thu, Nov 14, 2024 at 4:21 PM Kevin Wolf wrote: > > [...] > > > > > I'll just note that I'm only forwarding on the patch from Jakub. > > > I didn't write it. > > > > > > I did lightly test it, and it seems

Re: [PATCH v2 01/54] util/interval-tree: Introduce interval_tree_free_nodes

On 11/14/24 08:00, Richard Henderson wrote: Provide a general-purpose release-all-nodes operation, that allows for the IntervalTreeNode to be embeded within a larger structure. Signed-off-by: Richard Henderson --- include/qemu/interval-tree.h | 11 +++ util/interval-tree.c |

Re: [PATCH v2 03/54] accel/tcg: Split out tlbfast_{index,entry}

On 11/14/24 08:00, Richard Henderson wrote: Often we already have the CPUTLBDescFast structure pointer. Allows future code simplification. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/accel/tc

Re: [PATCH v2 05/54] accel/tcg: Fix flags usage in mmu_lookup1, atomic_mmu_lookup

On 11/14/24 08:00, Richard Henderson wrote: The INVALID bit should only be auto-cleared when we have just called tlb_fill, not along the victim_tlb_hit path. In atomic_mmu_lookup, rename tlb_addr to flags, as that is what we're actually carrying around. Signed-off-by: Richard Henderson ---

Re: [PATCH v2 06/54] accel/tcg: Assert non-zero length in tlb_flush_range_by_mmuidx*

On 11/14/24 08:00, Richard Henderson wrote: Next patches will assume non-zero length. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 77b972fd93..1346a26d90 100644 --- a/accel/tcg/

Re: [PATCH] pc-bios/s390x: Initialize machine loadparm before probing IPL devices

On 14/11/2024 17.19, jro...@linux.ibm.com wrote: From: Jared Rossi Commit bb185de423 ("s390x: Add individual loadparm assignment to CCW device") allowed boot devices to be assigned a loadparm value independent of the machine value, however, when no boot devices are defined, the machine loadparm

Re: [PATCH] docs/system/s390x/bootdevices: Update loadparm documentation

On 15/11/2024 01.27, jro...@linux.ibm.com wrote: From: Jared Rossi Update documentation to include per-device loadparm support. Signed-off-by: Jared Rossi --- docs/system/s390x/bootdevices.rst | 24 +++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/docs

Re: [PATCH] hw: Add "loadparm" property to scsi disk devices for booting on s390x

On 15/11/2024 00.30, Jared Rossi wrote: On 11/14/24 12:47 PM, Thomas Huth wrote: On 14/11/2024 16.55, Jared Rossi wrote: On 11/14/24 7:29 AM, Thomas Huth wrote: While adding the new flexible boot order feature on s390x recently, we missed to add the "loadparm" property to the scsi-hd and s

Re: [PATCH 05/24] target/i386/helper: Include missing 'exec/translation-block.h' header

On 11/13/24 17:12, Philippe Mathieu-Daudé wrote: TB compile flags are defined in "exec/translation-block.h". Include it in order to avoid when refactoring: target/i386/helper.c:536:28: error: use of undeclared identifier 'CF_PCREL' 536 | if (tcg_cflags_has(cs, CF_PCREL)) { |

[ANNOUNCE] QEMU 9.2.0-rc0 is now available

Hello, On behalf of the QEMU Team, I'd like to announce the availability of the first release candidate for the QEMU 9.2 release. This release is meant for testing purposes and should not be used in a production environment. http://download.qemu.org/qemu-9.2.0-rc0.tar.xz http://download.qemu.

Re: [PATCH v2 39/54] target/m68k: Do not call tlb_set_page in helper_ptest

On 11/14/24 08:01, Richard Henderson wrote: The entire operation of ptest is performed within get_physical_address as part of ACCESS_PTEST. There is no need to install the page into softmmu. Signed-off-by: Richard Henderson --- target/m68k/helper.c | 10 +- 1 file changed, 1 insertio

Re: [PATCH v2 37/54] target/loongarch: Convert to TCGCPUOps.tlb_fill_align

On 11/14/24 08:01, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/loongarch/internals.h | 7 --- target/loongarch/cpu.c| 2 +- target/loongarch/tcg/tlb_helper.c | 17 +++-- 3 files changed, 16 insertions(+), 10 deletions(-) diff --gi

Re: [PATCH v2 45/54] target/rx: Convert to TCGCPUOps.tlb_fill_align

On 11/14/24 08:01, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/rx/cpu.c | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65a74ce720..c83a582141 100644 --- a/target/rx/cpu.c +++ b/target/rx

Re: [PATCH V3 11/16] migration: cpr-transfer mode

On 11/13/2024 4:58 PM, Peter Xu wrote: On Fri, Nov 01, 2024 at 06:47:50AM -0700, Steve Sistare wrote: Add the cpr-transfer migration mode. Usage: qemu-system-$arch -machine anon-alloc=memfd ... start new QEMU with "-incoming -cpr-uri " Issue commands to old QEMU: migrate_set_para

Re: [PATCH v2 3/8] qom: introduce object_new_dynamic()

On Mon, Nov 11, 2024 at 03:55:50PM +, Daniel P. Berrangé wrote: > object_new() has a failure scenario where it will assert() if given > an abstract type. Callers which are creating objects based on user > input, or unknown/untrusted type names, must manually check the > result of object_class_i

Re: [PATCH] hw: Add "loadparm" property to scsi disk devices for booting on s390x

On 14/11/2024 16.55, Jared Rossi wrote: On 11/14/24 7:29 AM, Thomas Huth wrote: While adding the new flexible boot order feature on s390x recently, we missed to add the "loadparm" property to the scsi-hd and scsi-cd devices. This property is required on s390x to pass the information to the boo

Re: [PATCH v2 09/54] accel/tcg: Add IntervalTreeRoot to CPUTLBDesc

On 11/14/24 08:00, Richard Henderson wrote: Add the data structures for tracking softmmu pages via a balanced interval tree. So far, only initialize and destroy the data structure. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 +++ accel/tcg/cputlb.c| 11 +++

Re: [PATCH v2 10/54] accel/tcg: Populate IntervalTree in tlb_set_page_full

On 11/14/24 08:00, Richard Henderson wrote: Add or replace an entry in the IntervalTree for each page installed into softmmu. We do not yet use the tree for anything else. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 34 -- 1 file changed, 28

Re: [PATCH v2 12/54] accel/tcg: Remove IntervalTree entries in tlb_flush_range_locked

On 11/14/24 08:00, Richard Henderson wrote: Flush a masked range of pages from the IntervalTree cache. When the mask is not used there is a redundant comparison, but that is better than duplicating code at this point. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 25 +++

Re: [PATCH v2 11/54] accel/tcg: Remove IntervalTree entry in tlb_flush_page_locked

On 11/14/24 08:00, Richard Henderson wrote: Flush a page from the IntervalTree cache. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ea6a5177de..d532d6

Re: [PATCH v2 13/54] accel/tcg: Process IntervalTree entries in tlb_reset_dirty

On 11/14/24 08:00, Richard Henderson wrote: Update the addr_write copy within each interval tree node. Tidy the iteration within the other two loops as well. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-)

Re: [PATCH v2 08/54] accel/tcg: Flush entire tlb when a masked range wraps

On 11/14/24 08:00, Richard Henderson wrote: We expect masked address spaces to be quite large, e.g. 56 bits for AArch64 top-byte-ignore mode. We do not expect addr+len to wrap around, but it is possible with AArch64 guest flush range instructions. Convert this unlikely case to a full tlb flu

[PATCH v2 37/54] target/loongarch: Convert to TCGCPUOps.tlb_fill_align

Signed-off-by: Richard Henderson --- target/loongarch/internals.h | 7 --- target/loongarch/cpu.c| 2 +- target/loongarch/tcg/tlb_helper.c | 17 +++-- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/target/loongarch/internals.h b/target/loongarc

Re: [PATCH v2 16/54] accel/tcg: Pass full addr to victim_tlb_hit

On 11/14/24 08:00, Richard Henderson wrote: Do not mask the address to the page in these calls. It is easy enough to use a different helper instead. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/

Re: [PATCH v2 14/54] accel/tcg: Process IntervalTree entries in tlb_set_dirty

On 11/14/24 08:00, Richard Henderson wrote: Update the addr_write copy within an interval tree node. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index

Re: [PATCH v2 15/54] accel/tcg: Use tlb_hit_page in victim_tlb_hit

On 11/14/24 08:00, Richard Henderson wrote: This is clearer than directly comparing the page address and the comparator. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c in

Re: [RFC PATCH 00/11] rust: improved integration with cargo

Paolo Bonzini writes: > On 11/14/24 16:22, Alex Bennée wrote: >> ERROR: Build data file './meson-private/build.dat' references >> functions or classes that don't exist. This probably means that it >> was generated with an old version of meson. Try running from the >> source directory meson setup

Re: [PATCH v2 17/54] accel/tcg: Replace victim_tlb_hit with tlbtree_hit

On 11/14/24 08:00, Richard Henderson wrote: Change from a linear search on the victim tlb to a balanced binary tree search on the interval tree. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 59 -- 1 file changed, 31 insertions(+), 28 d

Re: [PATCH v2 07/54] accel/tcg: Assert bits in range in tlb_flush_range_by_mmuidx*

On 11/14/24 08:00, Richard Henderson wrote: The only target that does not use TARGET_LONG_BITS is Arm, which only reduces bits based on TBI. There is no point in handling odd combinations of parameters. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 16 1 file

Re: [PATCH v2 18/54] accel/tcg: Remove the victim tlb

On 11/14/24 08:00, Richard Henderson wrote: This has been functionally replaced by the IntervalTree. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 8 - accel/tcg/cputlb.c| 74 --- 2 files changed, 82 deletions(-) diff --git

Re: [PATCH v2 19/54] accel/tcg: Remove tlb_n_used_entries_inc

On 11/14/24 08:00, Richard Henderson wrote: Expand the function into its only caller, using the existing CPUTLBDesc local pointer. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/

[PATCH v8 2/3] tpm/tpm_tis_spi: activation for the PowerNV machines

The addition to ppc/Kconfig is for building this into the qemu-system-ppc64 binary. The enablement requires the following command line argument: -device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4 Signed-off-by: dan tan --- hw/ppc/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/pp

Re: QEMU wiki theme table of contents changes

On Thu, 14 Nov 2024 at 05:51, Daniel P. Berrangé wrote: > > Looking at > > https://wiki.qemu.org/ChangeLog/9.2 > > I'm thinking that I'm sure there used to be a table of contents present > at the top of pages, but none is to be seen. until I eventually > discover that there's a bare noticabl

Re: [PATCH 06/24] target/rx/cpu: Include missing 'exec/translation-block.h' header

On 11/13/24 17:12, Philippe Mathieu-Daudé wrote: The TranslationBlock structure is declared in "exec/translation-block.h", along with the TB compile flag definitions. Include the header in order to avoid when refactoring: target/rx/cpu.c:50:42: error: use of undeclared identifier 'CF_PCREL'

Re: [PATCH v2 33/54] accel/tcg: Remove CPUTLBDesc.fulltlb

On 11/14/24 08:01, Richard Henderson wrote: This array is now write-only, and may be removed. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 1 - accel/tcg/cputlb.c| 34 +++--- 2 files changed, 7 insertions(+), 28 deletions(-) diff --git a/inc

Re: [PATCH V3 13/16] tests/qtest: defer connection

On 11/13/2024 5:36 PM, Fabiano Rosas wrote: Steve Sistare writes: Add an option to defer making the connecting to the monitor and qtest sockets when calling qtest_init_with_env. The client makes the connection later by calling qtest_connect_deferred and qtest_qmp_handshake. Signed-off-by: St

Re: [PATCH v2 52/54] accel/tcg: Unexport tlb_set_page*

On 11/14/24 08:01, Richard Henderson wrote: The new tlb_fill_align hook returns page data via structure rather than by function call, so we can make tlb_set_page_full be local to cputlb.c. There are no users of tlb_set_page or tlb_set_page_with_attrs, so those can be eliminated. Signed-off-by:

"make clean" after "git pull" runs configure before cleaning.

Apparently because: ../meson.build:1:0: ERROR: Meson version is 0.59.3 but project requires >=1.5.0 A full log can be found at /home/landley/qemu/qemu/build/meson-logs/meson-log.txt /home/landley/qemu/qemu/build/pyvenv/bin/meson setup --reconfigure /home/landley/qemu/qemu WARNING: Regeneratin

[PATCH 1/1] hw/net: Support Marvell 88E1111 phy driver

When the ethernet PHY's compatible string is 'ethernet-phy-id0141.0cc2', it will be matched with the Marvell driver in Linux instead of the generic driver. They differ from reading the PHY register17.11 bit which is for 'Speed and Duplex Resolved' and the value 0 will clear phydev->link and stop th

[PATCH v2 04/19] hw/net/xilinx_ethlite: Update QOM style

Use XlnxXpsEthLite typedef, OBJECT_DECLARE_SIMPLE_TYPE macro; convert type_init() to DEFINE_TYPES(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- hw/net/xilinx_ethlite.c | 48 +++-- 1 file changed, 22 insertions(+), 26 deletions(-)

Re: [PATCH 23/24] exec/memory: Move qemu_map_ram_ptr() declaration to 'exec/ram_addr.h'

On 11/13/24 17:13, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé --- include/exec/memory.h | 2 +- include/exec/ram_addr.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson r~ diff --git a/include/exec/memory.h b/include/exe

Re: [PATCH 24/24] exec: Move 'ram_addr.h' header under sysemu/ namespace

On 11/13/24 17:13, Philippe Mathieu-Daudé wrote: "ram_addr.h" contains declarations specific to system emulation, move it under the sysemu/ directory to clarify the API namespace. Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 +- include/exec/cpu-common.h

Re: [PATCH v2 4/8] convert code to object_new_dynamic() where appropriate

On Mon, Nov 11, 2024 at 03:55:51PM +, Daniel P. Berrangé wrote: > In cases where object_new() is not being passed a static, const > string, the caller cannot be sure what type they are instantiating. > There is a risk that instantiation could fail, if it is an abstract > type. > > Convert such

Re: [PATCH 10/24] target/arm/cpu: Restrict cpu_untagged_addr() to user emulation

On 11/13/24 17:12, Philippe Mathieu-Daudé wrote: Move the #endif guard where it belongs to restrict the cpu_untagged_addr() implementation to user emulation. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/ta

[PATCH v2 00/19] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls

Missing review: patch #19 (new) Since v1: - Addressed Edgar review comments - New patch to map RSVD I/O region (Paolo) - Added Edgar R-b tags This is the result of a long discussion with Edgar (started few years ago!) and Paolo: https://lore.kernel.org/qemu-devel/34f6fe2f-06e0-4e2a-a361-2d662f681

Re: [PATCH 11/24] exec: Introduce 'user/guest-host.h' header

On 11/13/24 17:12, Philippe Mathieu-Daudé wrote: Extract all declarations related to 'guest from/to host' address translation to a new "user/guest-host.h" header. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-all.h| 34 +-- include/exec/cpu_ldst.h | 47 +

[PATCH v4 5/5] target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits

Found that some of the cache properties are not set correctly for EPYC models. l1d_cache.no_invd_sharing should not be true. l1i_cache.no_invd_sharing should not be true. L2.self_init should be true. L2.inclusive should be true. L3.inclusive should not be true. L3.no_invd_sharing should be true.

[PATCH v4 2/5] target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits

Found that some of the cache properties are not set correctly for EPYC models. l1d_cache.no_invd_sharing should not be true. l1i_cache.no_invd_sharing should not be true. L2.self_init should be true. L2.inclusive should be true. L3.inclusive should not be true. L3.no_invd_sharing should be true.

Re: [PATCH V3 11/16] migration: cpr-transfer mode

On Thu, Nov 14, 2024 at 01:36:00PM -0500, Steven Sistare wrote: > On 11/13/2024 4:58 PM, Peter Xu wrote: > > On Fri, Nov 01, 2024 at 06:47:50AM -0700, Steve Sistare wrote: > > > Add the cpr-transfer migration mode. Usage: > > >qemu-system-$arch -machine anon-alloc=memfd ... > > > > > >sta

Re: [PATCH v2 6/8] qom: introduce qdev_new_dynamic()

On Mon, Nov 11, 2024 at 03:55:53PM +, Daniel P. Berrangé wrote: > qdev_new() has a failure scenario where it will assert() if given > an abstract type. Callers which are creating qdevs based on user > input, or unknown/untrusted type names, must manually check the > result of qdev_class_is_abst

Re: [PATCH 22/24] exec/cpu-common: Move ram_addr_t related methods to 'exec/ram_addr.h'

On 11/13/24 17:13, Philippe Mathieu-Daudé wrote: Move methods related to the ram_addr_t type to the specific "exec/ram_addr.h" header. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-common.h| 56 +--- include/exec/ram_addr.h | 56 ++

Re: [PATCH v2 27/54] accel/tcg: Return CPUTLBEntryFull not pointer in probe_access_internal

On 11/14/24 08:01, Richard Henderson wrote: Return a copy of the structure, not a pointer. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 40 ++-- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cpu

Re: [RFC PATCH 00/11] rust: improved integration with cargo

On 11/14/24 18:27, Alex Bennée wrote: Paolo Bonzini writes: On 11/14/24 16:22, Alex Bennée wrote: ERROR: Build data file './meson-private/build.dat' references functions or classes that don't exist. This probably means that it was generated with an old version of meson. Try running from the s

[PATCH v2 47/54] target/sh4: Convert to TCGCPUOps.tlb_fill_align

Signed-off-by: Richard Henderson --- target/sh4/cpu.h| 8 +--- target/sh4/cpu.c| 2 +- target/sh4/helper.c | 24 +--- 3 files changed, 23 insertions(+), 11 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index d928bcf006..161efdefcf 100644 --- a/ta

Re: [PATCH v2 31/54] accel/tcg: Always use IntervalTree for code lookups

On 11/14/24 08:01, Richard Henderson wrote: Because translation is special, we don't need the speed of the direct-mapped softmmu tlb. We cache a lookups in DisasContextBase within the translator loop anyway. Drop the addr_code comparator from CPUTLBEntry. Go directly to the IntervalTree for MMU

Re: [PATCH V3 13/16] tests/qtest: defer connection

On 11/13/2024 5:53 PM, Peter Xu wrote: On Fri, Nov 01, 2024 at 06:47:52AM -0700, Steve Sistare wrote: +void qtest_connect_deferred(QTestState *s) +{ +g_autofree gchar *socket_path = NULL; +g_autofree gchar *qmp_socket_path = NULL; + +socket_path = g_strdup_printf("%s/qtest-%d.sock",

Re: [PATCH v2 35/54] target/avr: Convert to TCGCPUOps.tlb_fill_align

On 11/14/24 08:01, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/avr/cpu.h| 7 --- target/avr/cpu.c| 2 +- target/avr/helper.c | 19 --- 3 files changed, 17 insertions(+), 11 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h

Re: [PATCH v2 34/54] target/alpha: Convert to TCGCPUOps.tlb_fill_align

On 11/14/24 08:01, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/alpha/cpu.h| 6 +++--- target/alpha/cpu.c| 2 +- target/alpha/helper.c | 23 +-- 3 files changed, 21 insertions(+), 10 deletions(-) diff --git a/target/alpha/cpu.h b/target

Re: [PATCH 07/24] system/watchpoint: Include missing 'exec/cpu-all.h' header

On 11/13/24 17:12, Philippe Mathieu-Daudé wrote: TARGET_PAGE_MASK is defined in "exec/cpu-all.h". Include it in order to avoid when refactoring: system/watchpoint.c:52:24: error: use of undeclared identifier 'TARGET_PAGE_MASK' 52 | in_page = -(addr | TARGET_PAGE_MASK); |

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