Re: check-function failing on func-arm-arm_aspeed

2024-11-05 Thread Thomas Huth
On 04/11/2024 13.12, Thomas Huth wrote: On 28/10/2024 18.14, Peter Maydell wrote: Trying a "make check-functional" I find that the func-arm-arm_aspeed test seems to hit a timeout: 18/18 qemu:func-thorough+func-arm-thorough+thorough / func-arm-arm_aspeed  TIMEOUT    600.08s   kil

Re: [PATCH v6 0/3] Add support for the RAPL MSRs series

2024-11-05 Thread Igor Mammedov
On Tue, 5 Nov 2024 08:11:14 +0100 Christian Horn wrote: > Hi all, > > some thoughts: > > - I vote for making the metrics as much as possible in the guest available > as on the host. Allows cascading, and having in-guest-monitoring working > like on bare metal. > - As result, really just pl

Re: [PATCH v3 2/2] vfio/migration: Add vfio_save_block_precopy_empty_hit trace event

2024-11-05 Thread Maciej S. Szmigiero
On 5.11.2024 08:56, Cédric Le Goater wrote: On 11/4/24 22:29, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" This way it is clearly known when there's no more data to send for that device. Signed-off-by: Maciej S. Szmigiero ---   hw/vfio/migration.c   | 8   hw/vfio/t

Re: [PATCH v4 2/2] target: Add system emulation aiming to target any architecture

2024-11-05 Thread Peter Maydell
On Tue, 5 Mar 2024 at 22:11, Philippe Mathieu-Daudé wrote: > > From: Philippe Mathieu-Daudé > > Add the 'any'-architecture target. > > - Only consider 64-bit targets > - Do not use any hardware accelerator (except qtest) > - For architecture constants, use: > . max of supported targets phys/vir

[PATCH] tests/functional: Provide the user with hints where to find more log files

2024-11-05 Thread Thomas Huth
Since the base.log and console.log files are not referenced from the meson test logs yet, they might be hard to find for the casual users. Thus let's print some hints in case a test case failed. For this we have to run unittest.main() with exit=False to get the results of the testing. Then we can i

Re: [PULL 60/65] hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states

2024-11-05 Thread Igor Mammedov
On Mon, 4 Nov 2024 16:09:26 -0500 "Michael S. Tsirkin" wrote: > From: Salil Mehta > > Reflect the QOM vCPUs ACPI CPU hotplug states in the `_STA.Present` and > and `_STA.Enabled` bits when the guest kernel evaluates the ACPI > `_STA` method during initialization, as well as when vCPUs are > hot

Re: [PULL 23/49] hw/core: Add Enclave Image Format (EIF) related helpers

2024-11-05 Thread Paolo Bonzini
On Tue, Nov 5, 2024 at 12:44 PM Peter Maydell wrote: > Hi; Coverity raises a couple of potential issues with the > read_eif_file() function in this commit, which are both > "Coverity assumes the file we're reading is untrusted and is > unsure that we're correctly sanitizing data from it before use

Re: [PATCH v3 2/2] vfio/migration: Add vfio_save_block_precopy_empty_hit trace event

2024-11-05 Thread Cédric Le Goater
On 11/5/24 13:20, Maciej S. Szmigiero wrote: On 5.11.2024 08:56, Cédric Le Goater wrote: On 11/4/24 22:29, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" This way it is clearly known when there's no more data to send for that device. Signed-off-by: Maciej S. Szmigiero ---   hw/vfio/

Re: [PATCH] tests/functional: Provide the user with hints where to find more log files

2024-11-05 Thread Cédric Le Goater
On 11/5/24 13:38, Thomas Huth wrote: Since the base.log and console.log files are not referenced from the meson test logs yet, they might be hard to find for the casual users. Thus let's print some hints in case a test case failed. For this we have to run unittest.main() with exit=False to get th

Re: [PATCH 2/5] migration/postcopy: magic value for postcopy channel

2024-11-05 Thread Peter Xu
On Tue, Nov 05, 2024 at 04:49:23PM +0530, Prasad Pandit wrote: > On Mon, 4 Nov 2024 at 22:48, Peter Xu wrote: > > Firstly, we'll need a way to tell mgmt that the new qemu binary supports > > enablement of both multifd + postcopy feature. That can be done with a > > > > "features": [ "postcopy-w

Re: [PATCH] tests/functional: Convert the RV32-on-RV64 riscv test

2024-11-05 Thread LIU Zhiwei
On 2024/11/5 18:35, Thomas Huth wrote: A straggler that has been added to the Avocado framework while the conversion to the functional framework was already in progress... Move it over now, too! Signed-off-by: Thomas Huth --- tests/avocado/tuxrun_baselines.py | 16 t

[PULL 02/31] tests/fp: Explicitly set 2-NaN propagation rule

2024-11-05 Thread Peter Maydell
Explicitly set a 2-NaN propagation rule in the softfloat tests. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm propagation rule of float_2nan_prop_s_ab. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message

[PULL 22/31] Revert "target/arm: Fix usage of MMU indexes when EL3 is AArch32"

2024-11-05 Thread Peter Maydell
This reverts commit 4c2c0474693229c1f533239bb983495c5427784d. This commit tried to fix a problem with our usage of MMU indexes when EL3 is AArch32, using what it described as a "more complicated approach" where we share the same MMU index values for Secure PL1&0 and NonSecure PL1&0. In theory this

[PULL 30/31] hw/net/npcm_gmac: Change error log to trace event

2024-11-05 Thread Peter Maydell
From: Nabih Estefan Convert the LOG_GUEST_ERROR for the "tx descriptor is owned by software" to a trace message. This condition is normal when there is there is nothing to transmit, and we would otherwise spam the logs with it in that situation. Signed-off-by: Nabih Estefan Signed-off-by: Roque

[PULL 13/31] target/xtensa: Factor out calls to set_use_first_nan()

2024-11-05 Thread Peter Maydell
In xtensa we currently call set_use_first_nan() in a lot of places where we want to switch the NaN-propagation handling. We're about to change the softfloat API we use to do that, so start by factoring all the calls out into a single xtensa_use_first_nan() function. The bulk of this change was don

[PULL 11/31] target/sparc: Move cpu_put_fsr(env, 0) call to reset

2024-11-05 Thread Peter Maydell
Currently we call cpu_put_fsr(0) in sparc_cpu_realizefn(), which initializes various fields in the CPU struct: * fsr_cexc_ftt * fcc[] * fsr_qne * fsr It also sets the rounding mode in env->fp_status. This is largely pointless, because when we later reset the CPU this will zero out all the fiel

[PULL 05/31] target/loongarch: Explicitly set 2-NaN propagation rule

2024-11-05 Thread Peter Maydell
Set the 2-NaN propagation rule explicitly in the float_status word we use. (There are a couple of places in fpu_helper.c where we create a dummy float_status word with "float_status *s = { };", but these are only used for calling float*_is_quiet_nan() so it doesn't matter that we don't set a 2-NaN

[PULL 21/31] softfloat: Remove fallback rule from pickNaN()

2024-11-05 Thread Peter Maydell
Now that all targets have been converted to explicitly set a NaN propagation rule, we can remove the set of target ifdefs (which now list every target) and clean up the references to fallback behaviour for float_2nan_prop_none. The "default" case in the switch will catch any remaining places where

[PULL 24/31] target/arm: Fix SVE SDOT/UDOT/USDOT (4-way, indexed)

2024-11-05 Thread Peter Maydell
Our implementation of the indexed version of SVE SDOT/UDOT/USDOT got the calculation of the inner loop terminator wrong. Although we correctly account for the element size when we calculate the terminator for the first iteration: intptr_t segend = MIN(16 / sizeof(TYPED), opr_sz_n); we don't do

[PULL 00/31] target-arm queue

2024-11-05 Thread Peter Maydell
tags/pull-target-arm-20241105 for you to fetch changes up to 374cdc8efe4a039510cca47e8399d54a1aeb4f2d: target/arm: Enable FEAT_CMOW for -cpu max (2024-11-05 10:10:00 +) target-arm queue: * Fix MMU indexes for AArch32 Secure

Re: [PATCH v6 45/60] i386/tdx: Don't get/put guest state for TDX VMs

2024-11-05 Thread Xiaoyao Li
On 11/5/2024 5:55 PM, Paolo Bonzini wrote: On 11/5/24 07:23, Xiaoyao Li wrote: From: Sean Christopherson Don't get/put state of TDX VMs since accessing/mutating guest state of production TDs is not supported. Note, it will be allowed for a debug TD. Corresponding support will be introduced wh

Re: [PATCH v6 60/60] docs: Add TDX documentation

2024-11-05 Thread Daniel P . Berrangé
On Tue, Nov 05, 2024 at 01:24:08AM -0500, Xiaoyao Li wrote: > Add docs/system/i386/tdx.rst for TDX support, and add tdx in > confidential-guest-support.rst > > Signed-off-by: Xiaoyao Li > --- > Changes in v6: > - Add more information of "Feature configuration" > - Mark TD Attestation as future

[PULL 18/31] target/microblaze: Explicitly set 2-NaN propagation rule

2024-11-05 Thread Peter Maydell
Set the NaN propagation rule explicitly for the float_status word used in the microblaze target. This is probably not the architecturally correct behaviour, but since this is a no-behaviour-change patch, we leave a TODO note to that effect. Signed-off-by: Peter Maydell Reviewed-by: Philippe Math

Re: [PATCH v6 56/60] i386/tdx: Don't treat SYSCALL as unavailable

2024-11-05 Thread Daniel P . Berrangé
On Tue, Nov 05, 2024 at 01:24:04AM -0500, Xiaoyao Li wrote: Preferrably explain the rationale for why this is needed in the commit message. > Signed-off-by: Xiaoyao Li > --- > target/i386/kvm/tdx.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/target/i386/kvm/tdx.c b/target/i

[PULL 01/31] softfloat: Allow 2-operand NaN propagation rule to be set at runtime

2024-11-05 Thread Peter Maydell
IEEE 758 does not define a fixed rule for which NaN to pick as the result if both operands of a 2-operand operation are NaNs. As a result different architectures have ended up with different rules for propagating NaNs. QEMU currently hardcodes the NaN propagation logic into the binary because pic

[PULL 03/31] target/arm: Explicitly set 2-NaN propagation rule

2024-11-05 Thread Peter Maydell
Set the 2-NaN propagation rule explicitly in the float_status words we use. We wrap this plus the pre-existing setting of the tininess-before-rounding flag in a new function arm_set_default_fp_behaviours() to avoid repetition, since we have a lot of float_status words at this point. The situation

[PATCH v6 15/60] i386/tdx: Set APIC bus rate to match with what TDX module enforces

2024-11-05 Thread Xiaoyao Li
TDX advertises core crystal clock with cpuid[0x15] as 25MHz for TD guests and it's unchangeable from VMM. As a result, TDX guest reads the APIC timer as the same frequency, 25MHz. While KVM's default emulated frequency for APIC bus is 1GHz, set the APIC bus rate to match with TDX explicitly to ens

[PULL 25/31] disas: Fix build against Capstone v6 (again)

2024-11-05 Thread Peter Maydell
From: Richard Henderson Like 9971cbac2f3, which set CAPSTONE_AARCH64_COMPAT_HEADER, also set CAPSTONE_SYSTEMZ_COMPAT_HEADER. Fixes the build against capstone v6-alpha. Signed-off-by: Richard Henderson Reviewed-by: Gustavo Romero Message-id: 20241022013047.830273-1-richard.hender...@linaro.org

[PULL 29/31] hw/sensor/tmp105: Convert printf() to trace event, add tracing for read/write access

2024-11-05 Thread Peter Maydell
From: Bernhard Beschow printf() unconditionally prints to the console which disturbs `-serial stdio`. Fix that by converting into a trace event. While at it, add some tracing for read and write access. Fixes: 7e7c5e4c1ba5 "Nokia N800 machine support (ARM)." Signed-off-by: Bernhard Beschow Revie

[PULL 14/31] target/xtensa: Explicitly set 2-NaN propagation rule

2024-11-05 Thread Peter Maydell
Set the NaN propagation rule explicitly in xtensa_use_first_nan(). (When we convert the softfloat pickNaNMulAdd routine to also select a NaN propagation rule at runtime, we will be able to remove the use_first_nan flag because the propagation rules will handle everything.) Signed-off-by: Peter Ma

qemu-devel@nongnu.org

2024-11-05 Thread Peter Maydell
Our current usage of MMU indexes when EL3 is AArch32 is confused. Architecturally, when EL3 is AArch32, all Secure code runs under the Secure PL1&0 translation regime: * code at EL3, which might be Mon, or SVC, or any of the other privileged modes (PL1) * code at EL0 (Secure PL0) This is diff

[PULL 09/31] target/m68k: Explicitly set 2-NaN propagation rule

2024-11-05 Thread Peter Maydell
Explicitly set the 2-NaN propagation rule on env->fp_status and on the temporary fp_status that we use in frem (since we pass that to a division operation function). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/m68k/cpu.c

[PULL 04/31] target/mips: Explicitly set 2-NaN propagation rule

2024-11-05 Thread Peter Maydell
Set the 2-NaN propagation rule explicitly in the float_status words we use. For active_fpu.fp_status, we do this in a new fp_reset() function which mirrors the existing msa_reset() function in doing "first call restore to set the fp status parts that depend on CPU state, then set the fp status par

[PULL 28/31] hw/watchdog/wdt_imx2: Remove redundant assignment

2024-11-05 Thread Peter Maydell
From: Bernhard Beschow The same statement is executed unconditionally right before the if statement. Cc: Guenter Roeck Reviewed-by: Guenter Roeck Signed-off-by: Bernhard Beschow Reviewed-by: Richard Henderson Message-id: 20241103143330.123596-4-shen...@gmail.com Signed-off-by: Peter Maydell

[PULL 10/31] target/m68k: Initialize float_status fields in gdb set/get functions

2024-11-05 Thread Peter Maydell
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we use a temporary float_status variable to pass to floatx80_to_float64() and float64_to_floatx80(), but we don't initialize it, meaning that those functions could access uninitialized data. Zero-init the structs. (We don't need to set a NaN-propag

[PATCH v6 11/60] i386/tdx: Make sept_ve_disable set by default

2024-11-05 Thread Xiaoyao Li
From: Isaku Yamahata For TDX KVM use case, Linux guest is the most major one. It requires sept_ve_disable set. Make it default for the main use case. For other use case, it can be enabled/disabled via qemu command line. Signed-off-by: Isaku Yamahata --- target/i386/kvm/tdx.c | 2 +- 1 file

Re: [PATCH v6 09/60] i386/tdx: Initialize TDX before creating TD vcpus

2024-11-05 Thread Xiaoyao Li
On 11/5/2024 6:34 PM, Daniel P. Berrangé wrote: On Tue, Nov 05, 2024 at 01:23:17AM -0500, Xiaoyao Li wrote: Invoke KVM_TDX_INIT in kvm_arch_pre_create_vcpu() that KVM_TDX_INIT configures global TD configurations, e.g. the canonical CPUID config, and must be executed prior to creating vCPUs. Use

Re: [PATCH v6 34/60] i386/tdx: implement tdx_cpu_realizefn()

2024-11-05 Thread Paolo Bonzini
On 11/5/24 12:38, Xiaoyao Li wrote: On 11/5/2024 6:06 PM, Paolo Bonzini wrote: On 11/5/24 07:23, Xiaoyao Li wrote: +static void tdx_cpu_realizefn(X86ConfidentialGuest *cg, CPUState *cs, +  Error **errp) +{ +    X86CPU *cpu = X86_CPU(cs); +    uint32_t host_phys_bits

Re: [PATCH v6 09/60] i386/tdx: Initialize TDX before creating TD vcpus

2024-11-05 Thread Daniel P . Berrangé
On Tue, Nov 05, 2024 at 07:51:53PM +0800, Xiaoyao Li wrote: > On 11/5/2024 6:34 PM, Daniel P. Berrangé wrote: > > On Tue, Nov 05, 2024 at 01:23:17AM -0500, Xiaoyao Li wrote: > > > Invoke KVM_TDX_INIT in kvm_arch_pre_create_vcpu() that KVM_TDX_INIT > > > configures global TD configurations, e.g. the

Re: [PATCH v6 13/60] i386/tdx: Validate TD attributes

2024-11-05 Thread Xiaoyao Li
On 11/5/2024 6:36 PM, Daniel P. Berrangé wrote: On Tue, Nov 05, 2024 at 01:23:21AM -0500, Xiaoyao Li wrote: Validate TD attributes with tdx_caps that fixed-0 bits must be zero and fixed-1 bits must be set. Besides, sanity check the attribute bits that have not been supported by QEMU yet. e.g.,

Re: [PATCH v6 14/60] i386/tdx: Support user configurable mrconfigid/mrowner/mrownerconfig

2024-11-05 Thread Xiaoyao Li
On 11/5/2024 6:38 PM, Daniel P. Berrangé wrote: On Tue, Nov 05, 2024 at 01:23:22AM -0500, Xiaoyao Li wrote: From: Isaku Yamahata Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD can be provided for TDX attestation. Detailed meaning of them can be found: https://lore.ke

Re: [PATCH v6 13/60] i386/tdx: Validate TD attributes

2024-11-05 Thread Daniel P . Berrangé
On Tue, Nov 05, 2024 at 07:53:57PM +0800, Xiaoyao Li wrote: > On 11/5/2024 6:36 PM, Daniel P. Berrangé wrote: > > On Tue, Nov 05, 2024 at 01:23:21AM -0500, Xiaoyao Li wrote: > > > Validate TD attributes with tdx_caps that fixed-0 bits must be zero and > > > fixed-1 bits must be set. > > > > > > Be

Re: [PATCH 5/5] migration: enable multifd and postcopy together

2024-11-05 Thread Prasad Pandit
On Mon, 4 Nov 2024 at 23:19, Peter Xu wrote: > Precopy keeps sending data even during postcopy, that's the background > stream (with/without preempt feature enabled). May need some amendment > when repost here. * Okay. > > +if (channel == CH_POSTCOPY) { > > +return false; > > +}

Re: [PATCH 4/5] migration: refactor ram_save_target_page functions

2024-11-05 Thread Peter Xu
On Tue, Nov 05, 2024 at 03:31:19PM +0530, Prasad Pandit wrote: > On Mon, 4 Nov 2024 at 22:30, Peter Xu wrote: > > Yes, IMHO it's better when merged. > > > > One more note here, that even with ZERO_PAGE_DETECTION_MULTIFD, qemu will > > fallback to use LEGACY in reality when !multifd before. We nee

[PATCH 00/19] hw/microblaze: Allow running cross-endian vCPUs

2024-11-05 Thread Philippe Mathieu-Daudé
Make machines endianness-agnostic, allowing to run a big-endian vCPU on the little-endian 'qemu-system-microblazeel' binary, and a little endian one on the big-endian 'qemu-system-microblaze' binary. Tests added, following combinations covered: - little-endian vCPU using little-endian binary (in-t

[PATCH 08/19] hw/microblaze: Propagate CPU endianness to microblaze_load_kernel()

2024-11-05 Thread Philippe Mathieu-Daudé
Pass vCPU endianness as argument so we can load kernels with different endianness (different from the qemu-system-binary builtin one). Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/boot.h | 4 ++-- hw/microblaze/boot.c | 8 hw/microblaze

[PATCH 12/19] hw/net/xilinx_ethlite: Only expect big-endian accesses

2024-11-05 Thread Philippe Mathieu-Daudé
The Xilinx 'ethlite' device was added in commit b43848a100 ("xilinx: Add ethlite emulation"), being only built back then for a big-endian MicroBlaze target (see commit 72b675caac "microblaze: Hook into the build-system"). I/O endianness access was then clarified in commit d48751ed4f ("xilinx-ethli

[PATCH 06/19] hw/microblaze: Fix MemoryRegionOps coding style

2024-11-05 Thread Philippe Mathieu-Daudé
Fix few MemoryRegionOps style before adding new fields in the following commits. Signed-off-by: Philippe Mathieu-Daudé --- hw/char/xilinx_uartlite.c | 4 ++-- hw/intc/xilinx_intc.c | 4 ++-- hw/net/xilinx_ethlite.c | 4 ++-- hw/timer/xilinx_timer.c | 4 ++-- 4 files changed, 8 insertions

[PATCH 13/19] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx

2024-11-05 Thread Philippe Mathieu-Daudé
Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/microblaze); \ done Signed-off-by: Philip

[PATCH 14/19] target/microblaze: Set MO_TE once in do_load() / do_store()

2024-11-05 Thread Philippe Mathieu-Daudé
All callers of do_load() / do_store() set MO_TE flag. Set it once in the callees. Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/translate.c | 36 +++ 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/target/microblaze/translate.c b/targ

[PATCH 19/19] tests/functional: Add microblaze cross-endianness tests

2024-11-05 Thread Philippe Mathieu-Daudé
Copy/paste the current tests, but call the opposite endianness machines, testing: - petalogix-s3adsp1800-le machine (little-endian CPU) on the qemu-system-microblaze binary (big-endian) - petalogix-s3adsp1800-be machine (big-endian CPU) on the qemu-system-microblazeel binary (little-endian). S

[PATCH 02/19] hw/microblaze: Deprecate big-endian petalogix-ml605 & xlnx-zynqmp-pmu

2024-11-05 Thread Philippe Mathieu-Daudé
The petalogix-ml605 machine was explicitly added as little-endian only machine in commit 00914b7d970 ("microblaze: Add PetaLogix ml605 MMU little-endian ref design"). Mark the big-endian version as deprecated. When the xlnx-zynqmp-pmu machine's CPU was added in commit 133d23b3ad1 ("xlnx-zynqmp-pmu

[PATCH 04/19] hw/microblaze/s3adsp1800: Rename unimplemented MMIO region as xps_gpio

2024-11-05 Thread Philippe Mathieu-Daudé
The machine datasheet mentions the GPIO device as 'xps_gpio'. Rename it accordingly to easily find its documentation. Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/microblaze/petalogix_s3a

[PATCH 05/19] hw/microblaze/s3adsp1800: Declare machine type using DEFINE_TYPES macro

2024-11-05 Thread Philippe Mathieu-Daudé
Replace DEFINE_MACHINE() by DEFINE_TYPES(), converting the class_init() handler. Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/h

[PATCH 01/19] target/microblaze: Rename CPU endianness property as 'little-endian'

2024-11-05 Thread Philippe Mathieu-Daudé
Rename the 'endian' property as 'little-endian' because the 'ENDI' bit is set when the endianness is in little order, and unset in big order. Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_ml605_mmu.c | 2 +- hw/microblaze/xlnx-zynqmp-pmu.c | 2 +- target/microblaze/cpu.c

[PATCH 15/19] target/microblaze: Introduce mo_endian() helper

2024-11-05 Thread Philippe Mathieu-Daudé
mo_endian() returns the target endianness, currently static. Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/translate.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 86f3c196189

[PATCH 17/19] hw/microblaze: Support various endianness for s3adsp1800 machines

2024-11-05 Thread Philippe Mathieu-Daudé
Introduce an abstract machine parent class which defines the 'little_endian' property. Duplicate the current machine, which endian is tied to the binary endianness, to one big endian and a little endian machine; updating the machine description. Keep the current default machine for each binary. 'p

[PATCH 16/19] target/microblaze: Consider endianness while translating code

2024-11-05 Thread Philippe Mathieu-Daudé
Consider the CPU ENDI bit, swap instructions when the CPU endianness doesn't match the binary one. Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.h | 7 +++ target/microblaze/translate.c | 5 +++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/

[PATCH 10/19] hw/timer/xilinx_timer: Only expect big-endian accesses

2024-11-05 Thread Philippe Mathieu-Daudé
Per the datasheet (reference added in file header, p.10): 'Register Data Types and Organization': "The XPS Timer/Counter registers are organized as big-endian data." Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/xilinx_timer.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) di

[PATCH 07/19] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit

2024-11-05 Thread Philippe Mathieu-Daudé
All these MemoryRegionOps read() and write() handlers are implemented expecting 32-bit accesses. Clarify that setting .impl.min/max_access_size fields. Signed-off-by: Philippe Mathieu-Daudé --- hw/char/xilinx_uartlite.c | 4 hw/intc/xilinx_intc.c | 4 hw/net/xilinx_ethlite.c | 4

[PATCH 09/19] hw/intc/xilinx_intc: Only expect big-endian accesses

2024-11-05 Thread Philippe Mathieu-Daudé
Per the datasheet (reference added in file header, p.9) 'Programming Model' -> 'Register Data Types and Organization': "The XPS INTC registers are read as big-endian data" Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/xilinx_intc.c | 13 - 1 file changed, 12 insertions(+), 1

[PATCH 03/19] hw/microblaze/s3adsp1800: Explicit CPU endianness

2024-11-05 Thread Philippe Mathieu-Daudé
By default the machine's CPU endianness is 'big' order ('little-endian' property set to %false). This corresponds to the default when this machine was added; see commits 6a8b1ae2020 "microblaze: Add petalogix s3a1800dsp MMU linux ref-design." and 72b675caacf "microblaze: Hook into the build-system

[PATCH 11/19] hw/timer/xilinx_timer: Allow down to 8-bit memory access

2024-11-05 Thread Philippe Mathieu-Daudé
Allow down to 8-bit access, per the datasheet (reference added in previous commit): "Timer Counter registers are accessed as one of the following types: • Byte (8 bits) • Half word (2 bytes) • Word (4 bytes)" Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/xilinx_timer.c | 2 +- 1 fil

[PATCH 18/19] tests/functional: Explicit endianness of microblaze assets

2024-11-05 Thread Philippe Mathieu-Daudé
The archive used in test_microblaze_s3adsp1800.py (testing a big-endian target) contains a big-endian kernel. Rename using the _BE suffix. Similarly, the archive in test_microblazeel_s3adsp1800 (testing a little-endian target) contains a little-endian kernel. Rename using _LE suffix. These change

Re: [PATCH v6 0/3] Add support for the RAPL MSRs series

2024-11-05 Thread Christian Horn
Hi all, some thoughts: - I vote for making the metrics as much as possible in the guest available as on the host. Allows cascading, and having in-guest-monitoring working like on bare metal. - As result, really just plain vCPU consumption would be made available in the guest as rapl-core.

Re: [PATCH 17/19] hw/microblaze: Support various endianness for s3adsp1800 machines

2024-11-05 Thread Richard Henderson
On 11/5/24 13:04, Philippe Mathieu-Daudé wrote: -static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, void *data) +static void petalogix_s3adsp1800_machine_class_init_be(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); +PetalogixS3adsp1800MachineC

Re: [PATCH 18/19] tests/functional: Explicit endianness of microblaze assets

2024-11-05 Thread Richard Henderson
On 11/5/24 13:04, Philippe Mathieu-Daudé wrote: The archive used in test_microblaze_s3adsp1800.py (testing a big-endian target) contains a big-endian kernel. Rename using the _BE suffix. Similarly, the archive in test_microblazeel_s3adsp1800 (testing a little-endian target) contains a little-end

Re: [PATCH 19/19] tests/functional: Add microblaze cross-endianness tests

2024-11-05 Thread Richard Henderson
On 11/5/24 13:04, Philippe Mathieu-Daudé wrote: Copy/paste the current tests, but call the opposite endianness machines, testing: - petalogix-s3adsp1800-le machine (little-endian CPU) on the qemu-system-microblaze binary (big-endian) - petalogix-s3adsp1800-be machine (big-endian CPU) on the

Re: [PATCH v3 5/5] hw/loongarch/virt: Enable cpu hotplug feature on virt machine

2024-11-05 Thread Igor Mammedov
On Mon, 4 Nov 2024 14:34:35 +0800 Bibo Mao wrote: > On virt machine, enable CPU hotplug feature has_hotpluggable_cpus. For > hot-added CPUs after power on, interrupt pin of extioi and ipi interrupt > controller need connect to pins of new CPU. > > Also change num-cpu property of extioi and ipi

Re: [PATCH v2 5/5] target/loongarch/tcg: Add hardware page table walker support

2024-11-05 Thread Richard Henderson
On 10/10/24 07:35, Song Gao wrote: +base = get_pte_base(env, address); + +/* 0:64bit, 1:128bit, 2:192bit, 3:256bit */ +shift = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTEWIDTH); +shift = (shift + 1) * 3; +ptindex = (address >> ptbase) & ((1 << ptwidth) -1); +

[RFC PATCH v5 1/2] target/riscv: Add RISC-V CSR qtest support

2024-11-05 Thread Ivan Klokov
The RISC-V architecture supports the creation of custom CSR-mapped devices. It would be convenient to test them in the same way as MMIO-mapped devices. To do this, a new call has been added to read/write CSR registers. Signed-off-by: Ivan Klokov --- hw/riscv/riscv_hart.c | 65 ++

Re: [PATCH 01/19] target/microblaze: Rename CPU endianness property as 'little-endian'

2024-11-05 Thread Anton Johansson via
On 05/11/24, Philippe Mathieu-Daudé wrote: > Rename the 'endian' property as 'little-endian' because the 'ENDI' > bit is set when the endianness is in little order, and unset in > big order. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/microblaze/petalogix_ml605_mmu.c | 2 +- > hw/microb

Re: [PATCH 02/19] hw/microblaze: Deprecate big-endian petalogix-ml605 & xlnx-zynqmp-pmu

2024-11-05 Thread Anton Johansson via
On 05/11/24, Philippe Mathieu-Daudé wrote: > The petalogix-ml605 machine was explicitly added as little-endian only > machine in commit 00914b7d970 ("microblaze: Add PetaLogix ml605 MMU > little-endian ref design"). Mark the big-endian version as deprecated. > > When the xlnx-zynqmp-pmu machine's

[RFC PATCH v5 0/2] Support RISC-V CSR read/write in Qtest environment

2024-11-05 Thread Ivan Klokov
These patches add functionality for unit testing RISC-V-specific registers. The first patch adds a Qtest backend, and the second implements a simple test. --- v5: - Move code from target/riscv to hw/riscv --- Ivan Klokov (2): target/riscv: Add RISC-V CSR qtest support tests/qtest: QTest ex

[RFC PATCH v5 2/2] tests/qtest: QTest example for RISC-V CSR register

2024-11-05 Thread Ivan Klokov
Added demo for reading CSR register from qtest environment. Signed-off-by: Ivan Klokov --- tests/qtest/meson.build | 2 +- tests/qtest/riscv-csr-test.c | 56 2 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/riscv-csr-test

Re: [PATCH] test/functional: Fix Aspeed buildroot tests

2024-11-05 Thread Peter Maydell
On Tue, 5 Nov 2024 at 13:23, Cédric Le Goater wrote: > > Since commit 786bc2255256, cached asset files are read-only. Adjust > the QEMU command line for buildroot tests to reflect the new > constraint on the flash drive. > > Fixes: f04cb2d00d5c ("tests/functional: Convert most Aspeed machine tests

Re: [PATCH 1/8] gdbstub: Allow the %d placeholder in the socket path

2024-11-05 Thread Richard Henderson
On 10/24/24 20:59, Ilya Leoshkevich wrote: Just like for QEMU_LOG_FILENAME, replace %d with PID in the GDB socket path. This allows running multi-process applications with, e.g., export QEMU_GDB=/tmp/qemu-%d.sock. Currently this is not possible, since the first process will cause the subsequent o

Re: [PATCH] test/functional: Fix Aspeed buildroot tests

2024-11-05 Thread Thomas Huth
On 05/11/2024 15.38, Peter Maydell wrote: On Tue, 5 Nov 2024 at 13:23, Cédric Le Goater wrote: Since commit 786bc2255256, cached asset files are read-only. Adjust the QEMU command line for buildroot tests to reflect the new constraint on the flash drive. Fixes: f04cb2d00d5c ("tests/functional

Re: [PATCH 3/8] user: Introduce user/signal.h

2024-11-05 Thread Richard Henderson
On 10/24/24 20:59, Ilya Leoshkevich wrote: gdbstub needs target_to_host_signal(), so move its declaration to a public header. Signed-off-by: Ilya Leoshkevich --- bsd-user/signal-common.h | 1 - bsd-user/signal.c | 1 + include/user/signal.h | 23 +++ li

[PULL 3/4] linux-user: Allow custom rt signal mappings

2024-11-05 Thread Richard Henderson
From: Ilya Leoshkevich Some applications want to use low priority realtime signals (e.g., SIGRTMAX). Currently QEMU cannot map all target realtime signals to host realtime signals, and chooses to sacrifice the end of the target realtime signal range. Allow users to choose how to map target realt

[PULL 1/4] tests/tcg: Replace -mpower8-vector with -mcpu=power8

2024-11-05 Thread Richard Henderson
From: Ilya Leoshkevich [1] deprecated -mpower8-vector, resulting in: powerpc64-linux-gnu-gcc: warning: switch '-mpower8-vector' is no longer supported qemu/tests/tcg/ppc64/vsx_f2i_nan.c:4:15: error: expected ';' before 'float' 4 | typedef vector float vsx_float32_vec_t;

[PATCH] meson: explain more verbosely why we forbid Clang on Windows

2024-11-05 Thread Daniel P . Berrangé
Contributors are repeatedly sending patches to remove the blockage of clang on Windows, ignoring that we need 'gcc_struct' support. Put some more explicit comments in the code to discourage people from doing this. Signed-off-by: Daniel P. Berrangé --- include/qemu/compiler.h | 7 +++ meson.

[PULL 0/4] linux-user patch queue

2024-11-05 Thread Richard Henderson
The following changes since commit 11b8920ed2093848f79f93d106afe8a69a61a523: Merge tag 'pull-request-2024-11-04' of https://gitlab.com/thuth/qemu into staging (2024-11-04 17:37:59 +) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-lu-202

[PULL 4/4] tests/tcg: Add SIGRTMIN/SIGRTMAX test

2024-11-05 Thread Richard Henderson
From: Ilya Leoshkevich Test the lowest and the highest real-time signals. This requires configuring the real-time signal mapping, and therefore some knowledge about the host. To this end, pass the emulator path in the QEMU environment variable to all tests (this should not disturb the existing on

[PULL 2/4] linux-user: Fix GDB complaining about system-supplied DSO string table index

2024-11-05 Thread Richard Henderson
From: Ilya Leoshkevich When debugging qemu-user processes using gdbstub, the following warning appears every time: warning: BFD: warning: system-supplied DSO at 0x7f8253cc3000 has a corrupt string table index The reason is that QEMU does not map the VDSO's section headers. The VDSO's ELF h

Re: [PATCH 3/8] user: Introduce user/signal.h

2024-11-05 Thread Warner Losh
On Thu, Oct 24, 2024 at 2:00 PM Ilya Leoshkevich wrote: > gdbstub needs target_to_host_signal(), so move its declaration to a > public header. > > Signed-off-by: Ilya Leoshkevich > --- > bsd-user/signal-common.h | 1 - > bsd-user/signal.c | 1 + > include/user/signal.h | 23 ++

Re: [PATCH] crypto: purge 'loaded' property that was documented as already removed

2024-11-05 Thread Daniel P . Berrangé
On Mon, Nov 04, 2024 at 09:09:40AM +0100, Markus Armbruster wrote: > Daniel P. Berrangé writes: > > > The 'loaded' property on TLS creds and secret objects was marked as > > deprected in 6.0.0 and then marked as removed in 7.1.0. > > deprecated > > Regarding "marked as removed": not quite. Its

Re: [PATCH] test/functional: Fix Aspeed buildroot tests

2024-11-05 Thread Cédric Le Goater
On 11/5/24 15:38, Peter Maydell wrote: On Tue, 5 Nov 2024 at 13:23, Cédric Le Goater wrote: Since commit 786bc2255256, cached asset files are read-only. Adjust the QEMU command line for buildroot tests to reflect the new constraint on the flash drive. Fixes: f04cb2d00d5c ("tests/functional: C

[PATCH v7 11/15] hw/vmapple/bdif: Introduce vmapple backdoor interface

2024-11-05 Thread Phil Dennis-Jordan
From: Alexander Graf The VMApple machine exposes AUX and ROOT block devices (as well as USB OTG emulation) via virtio-pci as well as a special, simple backdoor platform device. This patch implements this backdoor platform device to the best of my understanding. I left out any USB OTG parts; they

[PATCH v7 07/15] hw/misc/pvpanic: Add MMIO interface

2024-11-05 Thread Phil Dennis-Jordan
From: Alexander Graf In addition to the ISA and PCI variants of pvpanic, let's add an MMIO platform device that we can use in embedded arm environments. Signed-off-by: Alexander Graf Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Phil Dennis-Jordan Revie

Re: [PULL 02/67] target/ppc: Make divd[u] handler method decodetree compatible

2024-11-05 Thread Michael Tokarev
04.11.2024 03:17, Nicholas Piggin wrote: From: Ilya Leoshkevich This is like commit 86e6202a57b1 ("target/ppc: Make divw[u] handler method decodetree compatible."), but for gen_op_arith_divd(). 86e6202a57b1 is v9.0.0-880-g86e6202a57b1, ie, it is in 9.1 only. So I wonder what should we do for

[PATCH v7 03/15] hw/display/apple-gfx: Adds PCI implementation

2024-11-05 Thread Phil Dennis-Jordan
This change wires up the PCI variant of the paravirtualised graphics device, mainly useful for x86-64 macOS guests, implemented by macOS's ParavirtualizedGraphics.framework. It builds on code shared with the vmapple/mmio variant of the PVG device. Signed-off-by: Phil Dennis-Jordan --- v4: * Th

Re: [PATCH v4 05/15] MAINTAINERS: Add myself as maintainer for apple-gfx, reviewer for HVF

2024-11-05 Thread Roman Bolshakov
On Thu, Oct 24, 2024 at 12:28:03PM +0200, Phil Dennis-Jordan wrote: > I'm happy to take responsibility for the macOS PV graphics code. As > HVF patches don't seem to get much attention at the moment, I'm also > adding myself as designated reviewer for HVF and x86 HVF to try and > improve that. > >

Re: [PULL 23/49] hw/core: Add Enclave Image Format (EIF) related helpers

2024-11-05 Thread Alexander Graf
Hi Dorjoy, On 05.11.24 14:56, Dorjoy Chowdhury wrote: On Tue, Nov 5, 2024 at 6:51 PM Paolo Bonzini wrote: On Tue, Nov 5, 2024 at 12:44 PM Peter Maydell wrote: Hi; Coverity raises a couple of potential issues with the read_eif_file() function in this commit, which are both "Coverity assumes

[PATCH v7 15/15] hw/vmapple/vmapple: Add vmapple machine type

2024-11-05 Thread Phil Dennis-Jordan
From: Alexander Graf Apple defines a new "vmapple" machine type as part of its proprietary macOS Virtualization.Framework vmm. This machine type is similar to the virt one, but with subtle differences in base devices, a few special vmapple device additions and a vastly different boot chain. This

[PATCH v7 12/15] hw/vmapple/cfg: Introduce vmapple cfg region

2024-11-05 Thread Phil Dennis-Jordan
From: Alexander Graf Instead of device tree or other more standardized means, VMApple passes platform configuration to the first stage boot loader in a binary encoded format that resides at a dedicated RAM region in physical address space. This patch models this configuration space as a qdev dev

[PATCH v7 14/15] hw/block/virtio-blk: Replaces request free function with g_free

2024-11-05 Thread Phil Dennis-Jordan
The virtio_blk_free_request() function has been a 1-liner forwarding to g_free() for a while now. We may as well call g_free on the request pointer directly. Signed-off-by: Phil Dennis-Jordan Reviewed-by: Akihiko Odaki --- hw/block/virtio-blk.c | 43 +++---

[PATCH v7 08/15] hvf: arm: Ignore writes to CNTP_CTL_EL0

2024-11-05 Thread Phil Dennis-Jordan
From: Alexander Graf MacOS unconditionally disables interrupts of the physical timer on boot and then continues to use the virtual one. We don't really want to support a full physical timer emulation, so let's just ignore those writes. Signed-off-by: Alexander Graf Signed-off-by: Phil Dennis-Jo

[PATCH v7 10/15] hw/vmapple/aes: Introduce aes engine

2024-11-05 Thread Phil Dennis-Jordan
From: Alexander Graf VMApple contains an "aes" engine device that it uses to encrypt and decrypt its nvram. It has trivial hard coded keys it uses for that purpose. Add device emulation for this device model. Signed-off-by: Alexander Graf Signed-off-by: Phil Dennis-Jordan --- v3: * Rebased

[PATCH v7 05/15] MAINTAINERS: Add myself as maintainer for apple-gfx, reviewer for HVF

2024-11-05 Thread Phil Dennis-Jordan
I'm happy to take responsibility for the macOS PV graphics code. As HVF patches don't seem to get much attention at the moment, I'm also adding myself as designated reviewer for HVF and x86 HVF to try and improve that. I anticipate that the resulting workload should be covered by the funding I'm r

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