On Mon, 4 Nov 2024, Philippe Mathieu-Daudé wrote:
Hi,
TL;DR: I will repost the PR will the typo fixed.
On 1/11/24 13:44, Peter Maydell wrote:
On Thu, 31 Oct 2024 at 04:22, Philippe Mathieu-Daudé
wrote:
The following changes since commit
58d49b5895f2e0b5cfe4b2901bf24f3320b74f29:
Merge
On 10/29/24 23:29, Ilya Leoshkevich wrote:
On Thu, 2024-10-10 at 11:20 +0200, Paolo Bonzini wrote:
On 10/10/24 10:58, Ilya Leoshkevich wrote:
make check-tcg fails on Fedora with the following error message:
alpha-linux-gnu-gcc [...]
qemu/tests/tcg/multiarch/system/memory.c -o memory [...
On Mon, Nov 04, 2024 at 10:04:49AM +, Daniel P. Berrangé wrote:
> On Fri, Nov 01, 2024 at 08:11:05PM +, Mark Cave-Ayland wrote:
> > Convert the next-kbd device from the legacy UI qemu_add_kbd_event_handler()
> > function to use qemu_input_handler_register().
> >
> > Signed-off-by: Mark Cav
Hi Igor,
I've fixed most of the x86 problems you had commented in the V1 patch-set in the
recently floated V3 ACPI patch-set. This includes removing the
`is_{enabled,present}`
ACPI CPU States for which you expressed apprehensions. Sorry, there was a miss
from my side in the V2 related to the CPU
>-Original Message-
>From: Liu, Yi L
>Sent: Monday, November 4, 2024 4:45 PM
>Subject: Re: [PATCH v4 04/17] intel_iommu: Flush stage-2 cache in PASID-
>selective PASID-based iotlb invalidation
>
>On 2024/11/4 15:37, CLEMENT MATHIEU--DRIF wrote:
>>
>>
>> On 04/11/2024 03:49, Yi Liu wrote:
On Mon, Nov 04, 2024 at 07:14:42PM +0800, Yong-Xuan Wang wrote:
> Hi Daniel and Andrew,
>
> When handling an external interrupt via IMSIC, we need to use the stopei CSR
> to claim the top interrupt. Even though the QEMU can emulate the IMSIC devices
> without the in-kernel irqchip, we still need t
On 28/10/2024 18.14, Peter Maydell wrote:
Trying a "make check-functional" I find that the func-arm-arm_aspeed
test seems to hit a timeout:
18/18 qemu:func-thorough+func-arm-thorough+thorough /
func-arm-arm_aspeed TIMEOUT600.08s killed by
signal 15 SIGTERM
This is with co
On 11/4/24 8:14 AM, Yong-Xuan Wang wrote:
Hi Daniel and Andrew,
When handling an external interrupt via IMSIC, we need to use the stopei CSR
to claim the top interrupt. Even though the QEMU can emulate the IMSIC devices
without the in-kernel irqchip, we still need to trap and emulate the stop
On 11/4/24 13:12, Thomas Huth wrote:
On 28/10/2024 18.14, Peter Maydell wrote:
Trying a "make check-functional" I find that the func-arm-arm_aspeed
test seems to hit a timeout:
18/18 qemu:func-thorough+func-arm-thorough+thorough /
func-arm-arm_aspeed TIMEOUT 600.08s killed
On Fri, 1 Nov 2024 at 20:06, Peter Xu wrote:
> > -return s->capabilities[MIGRATION_CAPABILITY_MULTIFD];
> > +return s->capabilities[MIGRATION_CAPABILITY_MULTIFD]
> > +&& !migration_in_postcopy();
> > }
>
> We need to keep this as-is.. I'm afraid.
> You can always do proper che
On Thu, 31 Oct 2024 at 17:48, Thomas Huth wrote:
>
> The following changes since commit 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29:
>
> Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into
> staging (2024-10-29 14:00:43 +)
>
> are available in the Git repository at:
>
> htt
On Fri, Nov 01, 2024 at 08:11:05PM +, Mark Cave-Ayland wrote:
> Convert the next-kbd device from the legacy UI qemu_add_kbd_event_handler()
> function to use qemu_input_handler_register().
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/m68k/next-kbd.c | 166 ++
On 2/11/24 12:06, Cédric Le Goater wrote:
Philippe,
I can take this patch through the aspeed branch.
I missed this patch because it was deeply buried in a long thread.
Since you mentioned this feature will be reworked in the next cycle:
Acked-by: Philippe Mathieu-Daudé
Thanks,
C.
On 10
On 04/11/2024 13.46, Daniel P. Berrangé wrote:
On Mon, Nov 04, 2024 at 01:12:16PM +0100, Thomas Huth wrote:
On 28/10/2024 18.14, Peter Maydell wrote:
Trying a "make check-functional" I find that the func-arm-arm_aspeed
test seems to hit a timeout:
18/18 qemu:func-thorough+func-arm-thorough+tho
Coverity reports an unsigned overflow when doing:
for (; depth-- > 0; ) {
When depth = 0 inside riscv_iommu_ctx_fetch().
Building it with a recent GCC the code doesn't actually break with depth
= 0, i.e. the comparison "0-- > 0" will exit the loop instead of
proceeding, but 'depth' will ret
On 04/11/2024 13.31, Peter Maydell wrote:
On Thu, 31 Oct 2024 at 17:48, Thomas Huth wrote:
The following changes since commit 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29:
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into
staging (2024-10-29 14:00:43 +)
are available
On 11/4/24 13:19, Cédric Le Goater wrote:
On 11/4/24 13:12, Thomas Huth wrote:
On 28/10/2024 18.14, Peter Maydell wrote:
Trying a "make check-functional" I find that the func-arm-arm_aspeed
test seems to hit a timeout:
18/18 qemu:func-thorough+func-arm-thorough+thorough /
func-arm-arm_aspeed
On Mon, Nov 04 2024, Daniel P. Berrangé wrote:
> On Mon, Nov 04, 2024 at 03:45:13PM +0100, Eric Auger wrote:
>> Hi
>>
>> On 10/28/24 17:09, Daniel P. Berrangé wrote:
>> > On Mon, Oct 28, 2024 at 05:05:44PM +0100, Cornelia Huck wrote:
>> >> On Fri, Oct 25 2024, Daniel P. Berrangé wrote:
>> >>
>>
On 11/4/24 1:43 AM, dan tan wrote:
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Although the implementation is endian neutral, the SPI
bus mast
On 11/4/24 1:43 AM, dan tan wrote:
Add qtest cases to exercise main TPM functionality
The TPM device emulation is provided by swtpm, which is TCG
TPM 2.0, and TCG TPM TIS compliant. See
https://trustedcomputinggroup.org/wp-content/uploads/TCG_PC_Client_Platform_TPM_Profile_PTP_2.0_r1.03_v22.pd
Hi Stefan,
What's the best way to catch these in my own local testing without
submitting it to Travis CI?
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2024-11-04 09:20, Stefan Berger wrote:
On 11/4/24 1:43 AM, dan tan wrote:
Add qtest cases to
On Sat, Nov 02, 2024 at 01:57:22PM +0100, Bernhard Beschow wrote:
> Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and
> fixes the MSB of selector field to be zero, as specified in the datasheet.
>
> Fixes: 2a424990170b "LAN9118 emulation"
> Signed-off-by: Bernhard Bescho
On Mon, Nov 04, 2024 at 04:10:12PM +0100, Cornelia Huck wrote:
> On Mon, Nov 04 2024, Daniel P. Berrangé wrote:
>
> >
> > FYI, in x86 target the -cpu command has had a "migratable=bool" property
> > for a long time , which defaults to 'true' for 'host' model. This causes
> > QEMU to explicitly dr
HI Miguel,
> From: Miguel Luis
> Sent: Monday, November 4, 2024 12:55 PM
> To: Salil Mehta
>
> Hi Salil,
>
> > On 3 Nov 2024, at 09:24, Salil Mehta via
> wrote:
> >
> > Change Log
> > ==
> >
> > Patch V2 -> V3:
> > 1. Addressed left over issues of x86 suggested by Igor M
On 10/28/24 16:50, Peter Xu wrote:
On Fri, Oct 25, 2024 at 02:50:36PM +0200, Cédric Le Goater wrote:
On 10/24/24 23:30, Peter Xu wrote:
Introduce migration_mutex, protecting concurrent updates to
current_migration.
In reality, most of the exported migration functions are safe to access
migrati
On 2024-11-04 09:14, Stefan Berger wrote:
On 11/4/24 1:43 AM, dan tan wrote:
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Although the implementa
On 4/11/24 11:38, Thomas Huth wrote:
On 31/10/2024 04.52, Alistair Francis wrote:
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped characters [1].
Let's update the SiFive UART to use a async sifive_uart_xmit() function
to transmit the character
On Mon, 4 Nov 2024 at 13:16, Cédric Le Goater wrote:
>
> On 11/4/24 13:19, Cédric Le Goater wrote:
> > On 11/4/24 13:12, Thomas Huth wrote:
> >> On 28/10/2024 18.14, Peter Maydell wrote:
> >>> Trying a "make check-functional" I find that the func-arm-arm_aspeed
> >>> test seems to hit a timeout:
>
Hi Kashyap,
On 10/28/24 22:17, Kashyap Chamarthy wrote:
> On Fri, Oct 25, 2024 at 12:17:40PM +0200, Eric Auger wrote:
>> From: Cornelia Huck
>>
>> Add some documentation for the custom model.
>>
>> Signed-off-by: Eric Auger
>> Signed-off-by: Cornelia Huck
>> ---
>> docs/system/arm/cpu-features
On Sat, Nov 02, 2024 at 01:57:21PM +0100, Bernhard Beschow wrote:
> imx_fec models the same PHY as lan9118_phy. The code is almost the same with
> imx_fec having more logging and tracing. Merge these improvements into
> lan9118_phy and reuse in imx_fec to fix the code duplication.
>
> Some migrati
On Sat, Nov 02, 2024 at 01:57:20PM +0100, Bernhard Beschow wrote:
> A very similar implementation of the same device exists in imx_fec. Prepare
> for
> a common implementation by extracting a device model into its own files.
>
> Some migration state has been moved into the new device model which
On Sat, Nov 02, 2024 at 01:57:23PM +0100, Bernhard Beschow wrote:
> Prefer named constants over magic values for better readability.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Bernhard Beschow
Tested-by: Guenter Roeck
On Sat, Nov 02, 2024 at 01:57:24PM +0100, Bernhard Beschow wrote:
> The real device advertises this mode and the device model already advertises
> 100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
> make the model more realistic.
>
> Reviewed-by: Peter Maydell
> Signed-
On Mon, Nov 04 2024, Daniel P. Berrangé wrote:
> On Mon, Nov 04, 2024 at 04:10:12PM +0100, Cornelia Huck wrote:
>> On Mon, Nov 04 2024, Daniel P. Berrangé wrote:
>>
>> >
>> > FYI, in x86 target the -cpu command has had a "migratable=bool" property
>> > for a long time , which defaults to 'true'
Hi Kashyap,
On 10/25/24 16:51, Kashyap Chamarthy wrote:
> On Fri, Oct 25, 2024 at 12:17:19PM +0200, Eric Auger wrote:
>
> Hi Eric,
>
> I'm new to Arm, so please bear with my questions :)
>
>> This RFC series introduces a KVM host "custom" model.
> (a) On terminology: as we know, in the x86 world, Q
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Gerd,
Thanks for your response. So, on X86, I need to add a new type in qemu and
firmware. Is my understanding correct?
Regards,
Zhigang
-Original Message-
From: Gerd Hoffmann
Sent: Monday, November 4, 2024 4:53 AM
To: Luo, Z
On Thu, 31 Oct 2024 at 04:07, Pierrick Bouvier
wrote:
>
> MacOS and Linux are straightforward, but Windows needs a bit more
> details.
>
> Signed-off-by: Pierrick Bouvier
We have documentation on the wiki currently about how to
build on various platforms:
https://wiki.qemu.org/Hosts/Linux
https
On Fri, 1 Nov 2024 at 13:46, Peter Xu wrote:
>
> The following changes since commit ea8ae47bdd2024dc2596f16b27f27fd4dcc08776:
>
> Merge tag 'pull-target-arm-20241029' of
> https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-10-31
> 13:28:57 +)
>
> are available in the Git re
On 11/3/24 10:54, Junjie Mao wrote:
Paolo Bonzini writes:
From: Junjie Mao
offset_of! was stabilized in Rust 1.77.0. Use an alternative implemenation
that was found on the Rust forums, and whose author agreed to license as
MIT for use in QEMU.
The alternative allows only one level of fiel
On Mon, Sep 16, 2024 at 06:44:49PM +0100, Jonathan Cameron wrote:
> Add a test with 6 nodes to exercise most interesting corner cases of SRAT
> and HMAT generation including the new Generic Initiator and Generic Port
> Affinity structures. More details of the set up in the following patch
> adding
On 11/3/24 10:54, Junjie Mao wrote:
Paolo Bonzini writes:
From: Junjie Mao
offset_of! was stabilized in Rust 1.77.0. Use an alternative implemenation
that was found on the Rust forums, and whose author agreed to license as
MIT for use in QEMU.
The alternative allows only one level of fiel
On 11/3/24 10:54, Junjie Mao wrote:
Paolo Bonzini writes:
From: Junjie Mao
offset_of! was stabilized in Rust 1.77.0. Use an alternative implemenation
that was found on the Rust forums, and whose author agreed to license as
MIT for use in QEMU.
The alternative allows only one level of fiel
On Mon, Nov 04, 2024 at 03:58:19PM +, Peter Maydell wrote:
> On Thu, 31 Oct 2024 at 04:07, Pierrick Bouvier
> wrote:
> >
> > MacOS and Linux are straightforward, but Windows needs a bit more
> > details.
> >
> > Signed-off-by: Pierrick Bouvier
>
> We have documentation on the wiki currently
Coverity reports (CID 1564769, 1564770) that we potentially overflow
by doing some 32x32 multiplies for something that ends up in a 64 bit
value. Fix this by casting the first input to uint64_t to ensure a 64
bit multiply is used.
While we are at it note why we split the calculation into stride
On Mon, Nov 04, 2024 at 05:53:22PM +0530, Prasad Pandit wrote:
> On Fri, 1 Nov 2024 at 20:06, Peter Xu wrote:
> > > -return s->capabilities[MIGRATION_CAPABILITY_MULTIFD];
> > > +return s->capabilities[MIGRATION_CAPABILITY_MULTIFD]
> > > +&& !migration_in_postcopy();
> > > }
>
There are two identical sequences of a code doing the same thing that
raise warnings with Coverity. Before fixing those issues lets factor
out the common code into a helper function we can share.
Signed-off-by: Alex Bennée
Cc: Dmitry Osipenko
---
include/hw/virtio/virtio-gpu.h | 15 +
h
From: Manos Pitsidianakis
Patch was applied with invalid authorship by accident, which confuses
git tooling that look at git blame for contributors etc.
Patch will be re-applied with correct authorship right after this
commit.
This reverts commit d0f0cd5b1f7e9780753344548e17ad4df9fcf5d8.
Signe
Because Ubuntu 22.04 has a very old version of bindgen, that
does not have the important option --allowlist-file, it will
not be able to use --enable-rust out of the box. Instead,
install the latest version of bindgen-cli via "cargo install"
in the container, following QEMU's own documentation.
R
Signed-off-by: Paolo Bonzini
---
meson.build | 11 +++
1 file changed, 11 insertions(+)
diff --git a/meson.build b/meson.build
index fffdeef8c80..a0ae56c9625 100644
--- a/meson.build
+++ b/meson.build
@@ -115,6 +115,10 @@ if not bindgen.found() or
bindgen.version().version_compare('<0.6
This allows CStr constants to be defined easily on Rust 1.63.0, while
checking that there are no embedded NULs. c"" literals were only
stabilized in Rust 1.77.0.
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 5 ++-
rust/hw/char/pl011/src/devic
rustc_args is needed to smooth the difference in warnings between the various
versions of rustc. Always include those arguments.
Reviewed-by: Junjie Mao
Reviewed-by: Kevin Wolf
Signed-off-by: Paolo Bonzini
---
meson.build | 20 +---
rust/qemu-api/meson.bu
From: Manos Pitsidianakis
This commit adds a re-implementation of hw/char/pl011.c in Rust.
How to build:
1. Configure a QEMU build with:
--enable-system --target-list=aarch64-softmmu --enable-rust
2. Launching a VM with qemu-system-aarch64 should use the Rust version
of the pl011 device
Hi Cédric,
On 4.11.2024 18:11, Cédric Le Goater wrote:
Hello Maciej,
On 11/4/24 15:58, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This way both the start and end points of migrating a particular VFIO
device are known.
Add also a vfio_precopy_empty_hit trace event so it is known
All constructs introduced by newer versions of Rust have been removed.
Apart from Debian 12, all other supported Linux distributions have
rustc 1.75.0 or newer. This means that they only lack c"" literals
and stable offset_of!.
Tested-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
meson.build
MaybeUninit::zeroed() is handy but is not available as a "const" function
until Rust 1.75.0.
Remove the default implementation of Zeroable::ZERO, and write by hand
the definitions for those types that need it. It may be possible to
add automatic implementation of the trait, via a procedural macro
Workspaces allows tracking dependencies for multiple crates at once,
by having a single Cargo.lock file at the top of the rust/ tree.
Because QEMU's Cargo.lock files have to be synchronized with the versions
of crates in subprojects/, using a workspace avoids the need to copy
over the Cargo.lock fi
From: Manos Pitsidianakis
This code juxtaposed what should be happening according to the C device
model but is not needed now that this has been reviewed (I hope) and its
validity checked against what the C device does (I hope, again).
No functional change.
Signed-off-by: Manos Pitsidianakis
S
The next commit will introduce a new build.rs dependency for rust/qemu-api,
version_check. Before adding it, ensure that all dependencies are
synchronized between the Meson- and cargo-based build systems.
Note that it's not clear whether in the long term we'll use Cargo for
anything; it seems tha
Remove the duplicate code by using the module_init! macro; at the same time,
simplify how module_init! is used, by taking inspiration from the implementation
of #[derive(Object)].
Reviewed-by: Junjie Mao
Reviewed-by: Kevin Wolf
Signed-off-by: Paolo Bonzini
---
rust/qemu-api-macros/src/lib.rs
From: Manos Pitsidianakis
Declare the vmstate description of the PL011 device.
Based on a patch by Manos Pitsidianakis
(https://lore.kernel.org/qemu-devel/20241024-rust-round-2-v1-4-051e7a25b...@linaro.org/).
Signed-off-by: Manos Pitsidianakis
Signed-off-by: Paolo Bonzini
Link:
https://lore.
Now that device_class_set_props() takes a const pointer, the only part of
"define_property!" that needs to be non-const is the call to try_into().
This in turn will only break if offset_of returns a value with the most
significant bit set (i.e. a struct size that is >=2^31 or >= 2^63,
respectively
The following changes since commit 15195de6a93438be99fdf9a90992c4228527130d:
ci: enable rust in the Fedora system build job (2024-10-30 16:30:56 +0100)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream-rust
for you to fetch changes up to d20feaa9a
We have fixed all incompatibilities with older versions of rustc
and bindgen. Enable Rust on Debian to check that the minimum
supported version of Rust is indeed 1.63.0, and 0.60.x for bindgen.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Paolo Bonzini
---
.gitlab-ci.d/buildtest.yml | 4 ++--
From: Manos Pitsidianakis
Add a device specialization for the Luminary UART device.
This commit adds a DeviceId enum that utilizes the Index trait to return
different bytes depending on what device id the UART has (Arm -default-
or Luminary)
Signed-off-by: Manos Pitsidianakis
Signed-off-by: Pa
On 11/4/24 2:35 PM, Andrew Jones wrote:
Free the temporary register list.
Fixes: 608bdebb6075 ("target/riscv/kvm: support KVM_GET_REG_LIST")
Signed-off-by: Andrew Jones
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/kvm/kvm-cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff -
*** BLURB HERE ***
Version 6 summary:
1/3 tpm/tpm_tis_spi: Support TPM for SPI
- amend commit description
- amend hw/tpm/tpm_tis_spi.c prolog to reflect the generic nature
of the implementation
- remove irrelevant define of IBM_PONQ
- correct the functi
On 11/4/2024 5:39 AM, David Hildenbrand wrote:
On 01.11.24 14:47, Steve Sistare wrote:
Allocate anonymous memory using mmap MAP_ANON or memfd_create depending
on the value of the anon-alloc machine property. This option applies to
memory allocated as a side effect of creating various devices. I
On Sun, 3 Nov 2024 at 19:59, wrote:
>
> From: Helge Deller
>
> The following changes since commit 92ec7805190313c9e628f8fc4eb4f932c15247bd:
>
> Merge tag 'pull-riscv-to-apply-20241031-1' of
> https://github.com/alistair23/qemu into staging (2024-10-31 16:34:25 +)
>
> are available in the G
On Sat, 2 Nov 2024 at 08:06, Song Gao wrote:
>
> The following changes since commit 92ec7805190313c9e628f8fc4eb4f932c15247bd:
>
> Merge tag 'pull-riscv-to-apply-20241031-1' of
> https://github.com/alistair23/qemu into staging (2024-10-31 16:34:25 +)
>
> are available in the Git repository a
Hi Alistair,
Thanks for the review, I will send a v3 as follow-up.
Regards,
Sai Pavan
>-Original Message-
>From: Alistair Francis
>Sent: Thursday, October 31, 2024 10:01 AM
>To: Philippe Mathieu-Daudé
>Cc: Simek, Michal ; Boddu, Sai Pavan
>; qemu-devel@nongnu.org; qemu-ri...@nongnu.org;
Thanks Phil, I will send a v3 for follow-up.
Regards,
Sai Pavan
>-Original Message-
>From: Philippe Mathieu-Daudé
>Sent: Thursday, October 31, 2024 9:30 PM
>To: Simek, Michal ; Alistair Francis
>; Boddu, Sai Pavan
>Cc: qemu-devel@nongnu.org; qemu-ri...@nongnu.org; Paolo Bonzini
>; Palme
Add a basic board with interrupt controller (intc), timer, serial
(uartlite), small memory called LMB@0 (128kB) and DDR@0x8000
(configured via command line eg. -m 2g).
This is basic configuration which matches HW generated out of AMD Vivado
(design tools). But initial configuration is going bey
All Hexagon debugging is now done with QEMU mechanisms
(e.g., -d in_asm) or with a connected debugger (lldb).
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h | 8 +--
target/hexagon/helper.h| 5 +-
target/hexagon/internal.h | 13 +
target/hexagon/translate.h | 2 -
t
On Tue, Oct 29, 2024 at 08:39:08PM +0530, Prasad Pandit wrote:
> From: Prasad Pandit
>
> Enable Multifd and Postcopy migration together.
> The migration_ioc_process_incoming() routine
> checks magic value sent on each channel and
> helps to properly setup multifd and postcopy
> channels.
>
> Ide
On Mon, Nov 04, 2024 at 08:47:53PM +0800, Yong-Xuan Wang wrote:
> Hi Daniel and Andrew,
>
> Sorry I found that I forgot a situation. Host kernel doesn't support
> in-kernel AIA is not equal to host machine doesn't support AIA extension.
>
> If user specifies aia=aplic-imsic when using KVM acceler
On 11/1/24 10:39 AM, Michael Tokarev wrote:
31.10.2024 06:52, Alistair Francis wrote:
RISC-V PR for 9.2
* Fix an access to VXSAT
* Expose RV32 cpu to RV64 QEMU
* Don't clear PLIC pending bits on IRQ lowering
* Make PLIC zeroth
core::ffi::c_* types were introduced in Rust 1.64.0. Use the older types
in std::os::raw, which are now aliases of the types in core::ffi. There is
no need to compile QEMU as no_std, so this is acceptable as long as we support
a version of Debian with Rust 1.63.0.
Reviewed-by: Zhao Liu
Signed-o
Hi Roque,
On 1/11/24 18:41, Roque Arcudia Hernandez wrote:
This contains a series of small compiler fixes to enable the compilation
of qemu using clang-cl.
It mainly involves adding some missing header files and updating #ifdefs
to handle clang-cl specific things.
Signed-off-by: Erwin Jansen
On 01.11.24 14:47, Steve Sistare wrote:
Allocate anonymous memory using mmap MAP_ANON or memfd_create depending
on the value of the anon-alloc machine property. This option applies to
memory allocated as a side effect of creating various devices. It does
not apply to memory-backend-objects, whet
https://github.com/legoater/qemu/ tags/pull-aspeed-20241104
for you to fetch changes up to 8df5fd815e841bf33fb51e1e6e5be9c31d529b94:
aspeed: Don't set always boot properties of the emmc device (2024-11-04
10:12:02 +0100)
--
'mode' will never be RISCV_IOMMU_CAP_SV32. We are erroring out in the
'switch' right before it if 'mode' isn't 0, 8, 9 or 10.
'mode' should be check with RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32.
Reported by Coverity via a "DEADCODE" ticket.
Resolves: Coverity CID 1564781
Fixes: 0c54acb8243 ("hw/risc
On Fri, 1 Nov 2024 at 20:04, Peter Xu wrote:
> As we discussed internally, we can't do this unconditionally. We at least
> some compat properties.
* ie. we define a new compat property to check if postcopy sends a
magic value or not?
> Or we need to see whether Fabiano's handshake can
> simpli
On 10/25/24 12:41, Richard Henderson wrote:
On 10/23/24 21:27, Ilya Leoshkevich wrote:
When debugging qemu-user processes using gdbstub, the following warning
appears every time:
warning: BFD: warning: system-supplied DSO at 0x7f8253cc3000 has a corrupt string
table index
The reason is
On Sun, Nov 03, 2024 at 02:34:08PM +0100, Bernhard Beschow wrote:
> Reviewed-by: Cédric Le Goater
> Signed-off-by: Bernhard Beschow
Yeah, I think this is best.
Acked-by: Corey Minyard
> ---
> hw/i2c/smbus_eeprom.c | 19 ---
> 1 file changed, 8 insertions(+), 11 deletions(-)
>
Hi,
This series fixes two issues detected by Coverity in the riscv-iommu
code that just went upstream.
Peter,
I'm fixing only 2 CIDs because the third one is a false positive:
*** CID 1564781: Integer handling issues (INTEGER_OVERFLOW)
/builds/qemu-project/qemu/hw/riscv/riscv-iommu-pci.c: 97
On Mon, Nov 04, 2024 at 01:12:16PM +0100, Thomas Huth wrote:
> On 28/10/2024 18.14, Peter Maydell wrote:
> > Trying a "make check-functional" I find that the func-arm-arm_aspeed
> > test seems to hit a timeout:
> >
> > 18/18 qemu:func-thorough+func-arm-thorough+thorough /
> > func-arm-arm_aspeed
Hi Daniel and Andrew,
Sorry I found that I forgot a situation. Host kernel doesn't support
in-kernel AIA is not equal to host machine doesn't support AIA extension.
If user specifies aia=aplic-imsic when using KVM acceleration, we have 3
possibilities:
1. host doesn't support AIA extension -> rep
On 10/30/24 15:25, Paolo Savini wrote:
Thanks for the review Richard.
On 10/30/24 11:40, Richard Henderson wrote:
On 10/29/24 19:43, Paolo Savini wrote:
This patch optimizes the emulation of unit-stride load/store RVV instructions
when the data being loaded/stored per iteration amounts to 16 b
On Sun, Nov 03, 2024 at 02:33:58PM +0100, Bernhard Beschow wrote:
> Reviewed-by: Cédric Le Goater
> Signed-off-by: Bernhard Beschow
Acked-by: Corey Minyard
> ---
> hw/i2c/mpc_i2c.c | 20
> 1 file changed, 8 insertions(+), 12 deletions(-)
>
> diff --git a/hw/i2c/mpc_i2c.c
Hi Richard,
On 11/4/24 07:59, Richard Henderson wrote:
On 11/1/24 01:35, Gustavo Romero wrote:
FEAT_CMOW introduces support for controlling cache maintenance
instructions executed in EL0/1 and is mandatory from Armv8.8.
On real hardware, the main use for this feature is to prevent processes
fr
On 31/10/2024 04.52, Alistair Francis wrote:
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped characters [1].
Let's update the SiFive UART to use a async sifive_uart_xmit() function
to transmit the characters and apply back pressure to the guest
On Mon, Nov 04, 2024 at 02:32:53PM +, CLEMENT MATHIEU--DRIF wrote:
> Hi everyone,
>
> It seems that https://github.com/Zeex/subhook (EDK2 submodule) is not
> longer available on github (which makes recursive pull of submodules
> fail for a lot of people).
> Do you think we should do somethin
Hi
On 10/28/24 17:09, Daniel P. Berrangé wrote:
> On Mon, Oct 28, 2024 at 05:05:44PM +0100, Cornelia Huck wrote:
>> On Fri, Oct 25 2024, Daniel P. Berrangé wrote:
>>
>>> On Fri, Oct 25, 2024 at 03:28:35PM +0200, Eric Auger wrote:
Hi Daniel,
On 10/25/24 15:13, Daniel P. Berrangé wro
On Mon, Nov 04, 2024 at 08:55:35PM +0800, Zhenzhong Duan wrote:
> According to VTD spec, a 256-bit descriptor will result in an invalid
> descriptor error if submitted in an IQ that is setup to provide hardware
> with 128-bit descriptors (IQA_REG.DW=0). Meanwhile, there are old inv desc
> types (e.
On Mon, Nov 04, 2024 at 03:45:13PM +0100, Eric Auger wrote:
> Hi
>
> On 10/28/24 17:09, Daniel P. Berrangé wrote:
> > On Mon, Oct 28, 2024 at 05:05:44PM +0100, Cornelia Huck wrote:
> >> On Fri, Oct 25 2024, Daniel P. Berrangé wrote:
> >>
> >>> On Fri, Oct 25, 2024 at 03:28:35PM +0200, Eric Auger
From: "Maciej S. Szmigiero"
This way both the start and end points of migrating a particular VFIO
device are known.
Add also a vfio_precopy_empty_hit trace event so it is known when
there's no more data to send for that device.
Signed-off-by: Maciej S. Szmigiero
---
This is just the lone rema
>-Original Message-
>From: Michael S. Tsirkin
>Sent: Monday, November 4, 2024 7:51 PM
>Subject: Re: [PATCH v4 04/17] intel_iommu: Flush stage-2 cache in PASID-
>selective PASID-based iotlb invalidation
>
>On Mon, Nov 04, 2024 at 11:46:00AM +, Duan, Zhenzhong wrote:
>>
>>
>> >-Or
On Mon, Nov 04, 2024 at 11:46:00AM +, Duan, Zhenzhong wrote:
>
>
> >-Original Message-
> >From: Liu, Yi L
> >Sent: Monday, November 4, 2024 4:45 PM
> >Subject: Re: [PATCH v4 04/17] intel_iommu: Flush stage-2 cache in PASID-
> >selective PASID-based iotlb invalidation
> >
> >On 2024/1
On Fri, 1 Nov 2024 at 20:09, Peter Xu wrote:
> > +if (migrate_multifd()) {
> > +RAMBlock *block = pss->block;
> > +/*
> > + * While using multifd live migration, we still need to handle zero
> > + * page checking on the migration main thread.
> > + */
>
On Mon, Nov 04, 2024 at 11:55:39AM +, Duan, Zhenzhong wrote:
>
>
> >-Original Message-
> >From: Michael S. Tsirkin
> >Sent: Monday, November 4, 2024 7:51 PM
> >Subject: Re: [PATCH v4 04/17] intel_iommu: Flush stage-2 cache in PASID-
> >selective PASID-based iotlb invalidation
> >
> >
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