Re: [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for scalable modern mode

2024-11-03 Thread Yi Liu
On 2024/9/30 17:26, Zhenzhong Duan wrote: Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities related to scalable mode translation, thus there are multiple combinations. This vIOMMU implementation wants to simplify it with a new property "x-fls". When enabled in scalable

RE: [PATCH v4 10/17] intel_iommu: Process PASID-based iotlb invalidation

2024-11-03 Thread Duan, Zhenzhong
>-Original Message- >From: Liu, Yi L >Sent: Monday, November 4, 2024 10:51 AM >Subject: Re: [PATCH v4 10/17] intel_iommu: Process PASID-based iotlb >invalidation > >On 2024/9/30 17:26, Zhenzhong Duan wrote: >> PASID-based iotlb (piotlb) is used during walking Intel >> VT-d stage-1 page

RE: [PATCH v4 11/17] intel_iommu: Add an internal API to find an address space with PASID

2024-11-03 Thread Duan, Zhenzhong
>-Original Message- >From: Liu, Yi L >Sent: Monday, November 4, 2024 10:51 AM >Subject: Re: [PATCH v4 11/17] intel_iommu: Add an internal API to find an >address >space with PASID > >On 2024/9/30 17:26, Zhenzhong Duan wrote: >> From: Clément Mathieu--Drif >> >> This will be used to imp

Re: [PATCH-for-9.1 v2 0/4] hw/ssi/pnv_spi: Fixes Coverity CID 1558831

2024-11-03 Thread Nicholas Piggin
On Thu Aug 8, 2024 at 6:28 AM AEST, Philippe Mathieu-Daudé wrote: > v2: > - Cover PowerNV SSI in MAINTAINERS > - Use GLib API in pnv_spi_xfer_buffer_free() > - Simplify returning early > > Supersedes: <20240806134829.351703-3-chalapath...@linux.ibm.com> > > Chalapathi V (1): > hw/ssi/pnv_spi: Fix

Re: [PATCH v4] hw/ppc: Implement -dtb support for PowerNV

2024-11-03 Thread Aditya Gupta
On 03/11/24 17:04, Nicholas Piggin wrote: On Tue Aug 20, 2024 at 8:30 PM AEST, Aditya Gupta wrote: Currently any device tree passed with -dtb option in QEMU, was ignored by the PowerNV code. Read and pass the passed -dtb to the kernel, thus enabling easier debugging with custom DTBs. The exis

[PULL 21/67] ppc/spapr: remove deprecated machine pseries-2.5

2024-11-03 Thread Nicholas Piggin
From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.5 specific code with this patch for now. Also drop sPAPRMachineClass::use_ohci_by_default which is now useless. Suggested-by: Cédri

[PULL 65/67] MAINTAINERS: Remove myself from the PowerNV machines

2024-11-03 Thread Nicholas Piggin
From: Cédric Le Goater It's been an amazing experience working on PowerNV systems all these years. Now it's time for IBM to take the lead on the QEMU machine and shape its future. I'm stepping back as the maintainer of PowerNV. Cc: Nicholas Piggin Cc: Frédéric Barrat Signed-off-by: Cédric Le G

[PULL 12/67] hw/ssi/pnv_spi: Match _xfer_buffer_free() with _xfer_buffer_new()

2024-11-03 Thread Nicholas Piggin
From: Philippe Mathieu-Daudé pnv_spi_xfer_buffer_new() allocates %payload using g_malloc0(), and pnv_spi_xfer_buffer_write_ptr() allocates %payload->data using g_realloc(). Use the API equivalent g_free() to release the buffers. Cc: qemu-sta...@nongnu.org Signed-off-by: Philippe Mathieu-Daudé R

[PULL 46/67] hw/ppc: Implement -dtb support for PowerNV

2024-11-03 Thread Nicholas Piggin
From: Aditya Gupta Currently any device tree passed with -dtb option in QEMU, was ignored by the PowerNV code. Read and pass the passed -dtb to the kernel, thus enabling easier debugging with custom DTBs. The existing behaviour when -dtb is 'not' passed, is preserved as-is. But when a '-dtb' i

[PULL 35/67] target/ppc: use locally stored msr and avoid indirect access

2024-11-03 Thread Nicholas Piggin
From: Harsh Prateek Bora hreg_compute_hflags_value already stores msr locally to be used in most of the logic in the routine however some instances are still using env->msr which is unnecessary. Use locally stored value as available. Reviewed-by: Nicholas Piggin Reviewed-by: BALATON Zoltan Sig

[PULL 24/67] ppc/spapr: remove deprecated machine pseries-2.8

2024-11-03 Thread Nicholas Piggin
From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.8 specific code with this patch for now. Suggested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Harsh Prateek

RE: [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode

2024-11-03 Thread Duan, Zhenzhong
>-Original Message- >From: Liu, Yi L >Sent: Monday, November 4, 2024 11:16 AM >Subject: Re: [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in >scalable >modern mode > >On 2024/9/30 17:26, Zhenzhong Duan wrote: >> According to VTD spec, stage-1 page table could support 4-level a

Re: [PATCH v3 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose scalable modern mode

2024-11-03 Thread Yi Liu
On 2024/9/29 10:44, Duan, Zhenzhong wrote A question here: Are there any other major features that are still lacking for scalable mode? If not, maybe we can get rid of the "x" prefix? We don't support stage-1 and stage-2 coexist emulation and nested translation emulation through stage-1 and

[PATCH v2 2/3] hw/sd/sdhci: Introduce a new Write Protected pin inverted property

2024-11-03 Thread Jamin Lin via
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). However, some boards are design Write Protected pin active high. In other words, write enable

[PATCH v2 3/3] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 and AST2500 EVBs

2024-11-03 Thread Jamin Lin via
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2500 and AST2600 EVBs, the Write Protected pin is active high b

[PATCH v2 1/3] hw/sd/sdhci: Fix coding style

2024-11-03 Thread Jamin Lin via
Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- hw/sd/sdhci.c | 64 +-- 1 file changed, 42 insertions(+), 22 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index ed01499391..db7d54715

[PATCH v2 0/3] Introduce a new Write Protected pin inverted property

2024-11-03 Thread Jamin Lin via
change from v1: 1. Support RTC for AST2700. 2. Support SDHCI write protected pin inverted for AST2500 and AST2600. 3. Introduce Capabilities Register 2 for SD slot 0 and 1. 4. Support create flash devices via command line for AST1030. change from v2: replace wp-invert with wp-inverted and fix revi

Re: [PATCH] UI/GTK: full-screen after wait for hiding of tabs and menu_bar

2024-11-03 Thread Marc-André Lureau
Hi On Sat, Nov 2, 2024 at 8:05 AM Edmund Raile via wrote: > Wait for hiding of GTK notebook tabs and GTK menu_bar before entering > full-screen due to asynchronous nature of GTK. > > prevent: > * full-screen window overlap onto monitor below > * black bar on top of full-screen guest display >

Re: [PATCH 0/2] chardev/char-mux: tweak mux bitset operations

2024-11-03 Thread CLEMENT MATHIEU--DRIF
Hi Roman, Reviewed-by Clément Mathieu--Drif Thanks! On 02/11/2024 12:07, Roman Penyaev wrote: Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. Patchset twe

[PATCH v2 0/4] Trivial ARM changes

2024-11-03 Thread Bernhard Beschow
This series improves the tracing experience in three devices used in ARM context. It also removes a duplicate statement in an IMX watchdog. v2: * Fix format strings in trace events for imx_gpt (Phil) * Add patch for tmp105 which improves tracing Bernhard Beschow (4): hw/rtc/ds1338: Trace send a

[PATCH v6 03/15] hw/display/apple-gfx: Adds PCI implementation

2024-11-03 Thread Phil Dennis-Jordan
This change wires up the PCI variant of the paravirtualised graphics device, mainly useful for x86-64 macOS guests, implemented by macOS's ParavirtualizedGraphics.framework. It builds on code shared with the vmapple/mmio variant of the PVG device. Signed-off-by: Phil Dennis-Jordan --- v4: * Th

[PATCH v6 01/15] ui & main loop: Redesign of system-specific main thread event handling

2024-11-03 Thread Phil Dennis-Jordan
macOS's Cocoa event handling must be done on the initial (main) thread of the process. Furthermore, if library or application code uses libdispatch, the main dispatch queue must be handling events on the main thread as well. So far, this has affected Qemu in both the Cocoa and SDL UIs, although in

[PATCH v6 08/15] hvf: arm: Ignore writes to CNTP_CTL_EL0

2024-11-03 Thread Phil Dennis-Jordan
From: Alexander Graf MacOS unconditionally disables interrupts of the physical timer on boot and then continues to use the virtual one. We don't really want to support a full physical timer emulation, so let's just ignore those writes. Signed-off-by: Alexander Graf Signed-off-by: Phil Dennis-Jo

[PATCH v6 15/15] hw/vmapple/vmapple: Add vmapple machine type

2024-11-03 Thread Phil Dennis-Jordan
From: Alexander Graf Apple defines a new "vmapple" machine type as part of its proprietary macOS Virtualization.Framework vmm. This machine type is similar to the virt one, but with subtle differences in base devices, a few special vmapple device additions and a vastly different boot chain. This

[PATCH v6 14/15] hw/block/virtio-blk: Replaces request free function with g_free

2024-11-03 Thread Phil Dennis-Jordan
The virtio_blk_free_request() function has been a 1-liner forwarding to g_free() for a while now. We may as well call g_free on the request pointer directly. Signed-off-by: Phil Dennis-Jordan Reviewed-by: Akihiko Odaki --- hw/block/virtio-blk.c | 43 +++---

[PATCH v6 05/15] MAINTAINERS: Add myself as maintainer for apple-gfx, reviewer for HVF

2024-11-03 Thread Phil Dennis-Jordan
I'm happy to take responsibility for the macOS PV graphics code. As HVF patches don't seem to get much attention at the moment, I'm also adding myself as designated reviewer for HVF and x86 HVF to try and improve that. I anticipate that the resulting workload should be covered by the funding I'm r

[PATCH] hw/arm/virt: Move common vCPU properties in a function

2024-11-03 Thread Salil Mehta via
Refactor vCPU properties code from the `machvirt_init()` main loop with the following goals: 1. Enable code reuse in future patch sets. 2. Improve code readability. 3. Separate out the one-time initialization of (secure-)Tagged memory, handling potential failures early. Note: This is a cosmeti

Re: [PATCH v4 1/3] tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)

2024-11-03 Thread dan tan
On 2024-11-02 09:19, Stefan Berger wrote: On 11/1/24 4:27 PM, dan tan wrote: Implement support for TPM via SPI interface. The SPI bus master is provided by PowerNV SPI device which is an SSI peripheral. It can uses the tpm_emulator driver backend with the external swtpm. Although the implementa

Re: [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode

2024-11-03 Thread Yi Liu
On 2024/9/30 17:26, Zhenzhong Duan wrote: According to VTD spec, stage-1 page table could support 4-level and 5-level paging. However, 5-level paging translation emulation is unsupported yet. That means the only supported value for aw_bits is 48. So default aw_bits to 48 in scalable modern mode

Re: [PATCH v4 13/17] intel_iommu: piotlb invalidation should notify unmap

2024-11-03 Thread Yi Liu
On 2024/9/30 17:26, Zhenzhong Duan wrote: This is used by some emulated devices which caches address translation result. When piotlb invalidation issued in guest, those caches should be refreshed. For device that does not implement ATS capability or disable it but still caches the translation re

RE: [PATCH v4 06/17] intel_iommu: Implement stage-1 translation

2024-11-03 Thread Duan, Zhenzhong
>-Original Message- >From: Liu, Yi L >Sent: Sunday, November 3, 2024 10:22 PM >Subject: Re: [PATCH v4 06/17] intel_iommu: Implement stage-1 translation > >On 2024/9/30 17:26, Zhenzhong Duan wrote: >> From: Yi Liu >> >> This adds stage-1 page table walking to support stage-1 only >> tran

RE: [SPAM] [PATCH v1 0/8] Support RTC for AST2700

2024-11-03 Thread Jamin Lin
Hi Cedric, > Subject: Re: [SPAM] [PATCH v1 0/8] Support RTC for AST2700 > > On 10/29/24 10:17, Jamin Lin wrote: > > change from v1: > > 1. Support RTC for AST2700. > > 2. Support SDHCI write protected pin inverted for AST2500 and AST2600. > > 3. Introduce Capabilities Register 2 for SD slot 0 and

Re: [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode

2024-11-03 Thread Yi Liu
On 2024/11/4 11:19, Duan, Zhenzhong wrote: -Original Message- From: Liu, Yi L Sent: Monday, November 4, 2024 11:16 AM Subject: Re: [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode On 2024/9/30 17:26, Zhenzhong Duan wrote: According to VTD spec, stage-1

Re: [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for scalable modern mode

2024-11-03 Thread Yi Liu
On 2024/11/4 14:25, Duan, Zhenzhong wrote: -Original Message- From: Liu, Yi L Sent: Monday, November 4, 2024 12:25 PM Subject: Re: [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for scalable modern mode On 2024/9/30 17:26, Zhenzhong Duan wrote: Intel VT-d 3.0 introduces sc

Re: [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation

2024-11-03 Thread Yi Liu
On 2024/11/4 11:38, Duan, Zhenzhong wrote: -Original Message- From: Liu, Yi L Sent: Monday, November 4, 2024 10:51 AM Subject: Re: [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation On 2024/9/30 17:26, Zhenzhong Duan wrote: According to spec, Page-Selective-with

Re: [PATCH v4 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

2024-11-03 Thread CLEMENT MATHIEU--DRIF
On 04/11/2024 03:49, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, unless > this email comes from a known sender and you know the content is safe. > > > On 2024/9/30 17:26, Zhenzhong Duan wrote: >> Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidat

Re: [PATCH] hw/usb: Use __attribute__((packed)) vs __packed

2024-11-03 Thread Thomas Huth
On 01/11/2024 22.17, Roque Arcudia Hernandez wrote: __packed is non standard and is not present in clang-cl. __attribute__((packed)) has the same semantics. Signed-off-by: Erwin Jansen Signed-off-by: Roque Arcudia Hernandez --- include/hw/usb/dwc2-regs.h | 2 +- 1 file changed, 1 insertion(

Re: [PATCH 0/2] chardev/char-mux: tweak mux bitset operations

2024-11-03 Thread Marc-André Lureau
Hi On Sat, Nov 2, 2024 at 3:11 PM Roman Penyaev wrote: > Patchset tweaks bitset operations by changing a constant to unsigned > long, introduces a static compile check and simplifies bitset operations. > > Roman Penyaev (2): > chardev/char-mux: shift unsigned long to avoid 32-bit overflow >

[PATCH] arm/virt: Extract common code to wire GICC<->vCPU IRQs for reuse

2024-11-03 Thread Salil Mehta via
Extract common GIC and CPU interrupt wiring code to improve code readability and modularity, supporting reuse in future patch sets. This refactor is benign and introduces *no* functional changes. Note: This patch has been isolated from a larger patch set to facilitate early merging and reduce the

Re: [PATCH v17 02/14] hw/ppc/spapr_pci: Do not create DT for disabled PCI device

2024-11-03 Thread Shivaprasad G Bhat
On 10/28/24 11:28 AM, Akihiko Odaki wrote: On 2024/10/28 12:08, Shivaprasad G Bhat wrote: On 10/22/24 2:06 PM, Akihiko Odaki wrote: Disabled means it is a disabled SR-IOV VF and hidden from the guest. Do not create DT when starting the system and also keep the disabled PCI device not linke

Re: [QEMU PATCH v9] xen/passthrough: use gsi to map pirq when dom0 is PVH

2024-11-03 Thread Chen, Jiqian
On 2024/11/1 21:09, Stewart Hildebrand wrote: > On 10/24/24 05:06, Jiqian Chen wrote: >> diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c >> index 3635d1b39f79..5b10d501d566 100644 >> --- a/hw/xen/xen_pt.c >> +++ b/hw/xen/xen_pt.c >> @@ -766,6 +766,50 @@ static void xen_pt_destroy(PCIDevice *d) { >>

RE: [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for scalable modern mode

2024-11-03 Thread Duan, Zhenzhong
>-Original Message- >From: Liu, Yi L >Sent: Monday, November 4, 2024 12:25 PM >Subject: Re: [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for >scalable modern mode > >On 2024/9/30 17:26, Zhenzhong Duan wrote: >> Intel VT-d 3.0 introduces scalable mode, and it has a bunch of ca

[PATCH v3 3/5] hw/loongarch/virt: Add generic function to init interrupt pin of CPU

2024-11-03 Thread Bibo Mao
Here generic function virt_init_cpu_irq() is added to init interrupt pin of CPU object, IPI and extioi interrupt controllers are connected to interrupt pin of CPU object. The generic function can be used to both cold-plug and hot-plug CPUs. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 76 +

[PATCH v3 2/5] hw/loongarch/virt: Implement cpu plug interface

2024-11-03 Thread Bibo Mao
Add cpu hotplug interface, however cpu hotplug feature is still disabled for the machine. When machine is on, all created vCPUs go through hotplug interface, and there is no remaining vCPU which can be hot-added after power on. Co-developed-by: Xianglai Li Signed-off-by: Bibo Mao --- hw/loongar

[PATCH v3 0/5] hw/loongarch/virt: Add cpu hotplug support

2024-11-03 Thread Bibo Mao
LoongArch cpu hotplug is based on ACPI GED device, there is a little change about ipi and extioi device, the value of num-cpu property is maximum cpu number rather than present cpu number. It can be verified with qemu command: qemu-system-loongarch64 -smp 2,maxcpus=16,sockets=4,cores=4,threads=1

[PATCH v3 5/5] hw/loongarch/virt: Enable cpu hotplug feature on virt machine

2024-11-03 Thread Bibo Mao
On virt machine, enable CPU hotplug feature has_hotpluggable_cpus. For hot-added CPUs after power on, interrupt pin of extioi and ipi interrupt controller need connect to pins of new CPU. Also change num-cpu property of extioi and ipi from smp.cpus to smp.max_cpus Co-developed-by: Xianglai Li Si

[PATCH v3 1/5] hw/loongarch/virt: Add CPU topology support

2024-11-03 Thread Bibo Mao
Add topological relationship for Loongarch VCPU and initialize topology member variables, the topo information includes socket-id, core-id and thread-id. For cold-plug CPUs, its topo information is calculated from physical cpuid, and for hot-cpu CPUs its physical cpuid is calculated from topo infor

[PATCH v3 4/5] hw/loongarch/virt: Update the ACPI table for hotplug cpu

2024-11-03 Thread Bibo Mao
On LoongArch virt machine, ACPI GED hardware is used for CPU hotplug handler, here CPU hotplug support feature is added based on GED handler, also CPU scan and reject method is added about CPU device in DSDT table. Co-developed-by: Xianglai Li Signed-off-by: Bibo Mao --- hw/loongarch/Kconfig

[PATCH v5 3/3] tests/qtest/tpm: add unit test to tis-spi

2024-11-03 Thread dan tan
Add qtest cases to exercise main TPM functionality The TPM device emulation is provided by swtpm, which is TCG TPM 2.0, and TCG TPM TIS compliant. See https://trustedcomputinggroup.org/wp-content/uploads/TCG_PC_Client_Platform_TPM_Profile_PTP_2.0_r1.03_v22.pdf https://trustedcomputinggroup.org/wp-c

[PATCH v5 1/3] tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)

2024-11-03 Thread dan tan
Implement support for TPM via SPI interface. The SPI bus master is provided by PowerNV SPI device which is an SSI peripheral. It can uses the tpm_emulator driver backend with the external swtpm. Although the implementation is endian neutral, the SPI bus master provider, pnv_spi.c is only supported

[PATCH v5 0/3] TPM TIS SPI Support

2024-11-03 Thread dan tan
*** BLURB HERE *** Version 5 summary: 1/3 tpm/tpm_tis_spi: Support TPM for SPI - removed DEFINE_PROP_UINT32("irq", TPMStateSPI, tpm_state.irq_num, 0) from tpm_tis_spi_properties - In tpm.rst document, under section 'The QEMU TPM emulator device', moved the 'P

[PATCH v5 2/3] tpm/tpm_tis_spi: activation for the PowerNV machines

2024-11-03 Thread dan tan
The addition to ppc/Kconfig is for building this into the qemu-system-ppc64 binary. The enablement requires the following command line argument: -device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4 Signed-off-by: dan tan --- hw/ppc/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/pp

[PULL 25/67] ppc/spapr: remove deprecated machine pseries-2.9

2024-11-03 Thread Nicholas Piggin
From: Harsh Prateek Bora Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as deprecated with reasons mentioned in its commit log. Removing pseries-2.9 specific code with this patch for now. While at it, also remove the pre-2.10 migration hacks which now become obsolete. Suggested

[PULL 60/67] pnv/xive2: TIMA support for 8-byte OS context push for PHYP

2024-11-03 Thread Nicholas Piggin
From: Glenn Miles PHYP uses 8-byte writes to the 2nd doubleword of the OS context line when dispatching an OS level virtual processor. This support was not used by OPAL/Linux and so was never added. Without this support, the XIVE code doesn't notice that a new context is being pushed and fails

[PULL 44/67] spapr: nested: Add support for DPDES SPR in GSB for TCG L0

2024-11-03 Thread Nicholas Piggin
From: Amit Machhiwal The DPDES support for doorbell emulation and handling for KVM on PAPR guests was added in Linux via [1]. Subsequently, a new GSB (Guest State Buffer) element for DPDES was added in Linux; the same has been missing in TCG L0 implementation. Add support for DPDES register's API

[PULL 39/67] target/ppc: optimize p8 exception handling routines

2024-11-03 Thread Nicholas Piggin
From: Harsh Prateek Bora Most of the p8 exception handling accesses env->pending_interrupts and env->spr[SPR_LPCR] at multiple places. Passing it directly as local variables simplifies the code and avoids multiple indirect accesses. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora

[PULL 16/67] hw/ppc: fix decrementer with BookE timers

2024-11-03 Thread Nicholas Piggin
From: Clément Chigot The BookE decrementer stops at 0, meaning that it won't decremented towards "negative" values. However, the current logic is inverted: decr is updated solely when the resulting value would be negative. Signed-off-by: Clément Chigot Fixes: 8e0a5ac87800 ("hw/ppc: Avoid decrem

[PULL 64/67] hw/ppc: Consolidate ppc440 initial mapping creation functions

2024-11-03 Thread Nicholas Piggin
From: BALATON Zoltan Add a utility function and use it to replace very similar create_initial_mapping functions in 440 based machines. Signed-off-by: BALATON Zoltan Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Signed-off-by: Nicholas Piggin --- hw/ppc/ppc440_bamboo.c | 28 +++

Re: [PATCH v4 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

2024-11-03 Thread Yi Liu
On 2024/9/30 17:26, Zhenzhong Duan wrote: Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb entries with matching domain id and pasid. Also, call out it's per table Table 21. PASID-based-IOTLB Invalidation of VT-d spec 4.1. With scalable modern mode int

Re: [PATCH v4 08/17] intel_iommu: Set accessed and dirty bits during first stage translation

2024-11-03 Thread Yi Liu
On 2024/9/30 17:26, Zhenzhong Duan wrote: From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 25 - 2 files changed, 27 insertions(+), 1 deletio

Re: [PATCH v4 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation

2024-11-03 Thread Yi Liu
On 2024/9/30 17:26, Zhenzhong Duan wrote: From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 11 hw/i386/intel_iommu.c | 50 ++ 2 files changed, 61 insertions

Re: [PATCH v4 10/17] intel_iommu: Process PASID-based iotlb invalidation

2024-11-03 Thread Yi Liu
On 2024/9/30 17:26, Zhenzhong Duan wrote: PASID-based iotlb (piotlb) is used during walking Intel VT-d stage-1 page table. This emulates the stage-1 page table iotlb invalidation requested by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB). Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Du

Re: [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation

2024-11-03 Thread Yi Liu
On 2024/9/30 17:26, Zhenzhong Duan wrote: According to spec, Page-Selective-within-Domain Invalidation (11b): 1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through (PGTT=100b) mappings associated with the specified domain-id and the input-address range are invalidated. 2. IO

Re: [PATCH v4 11/17] intel_iommu: Add an internal API to find an address space with PASID

2024-11-03 Thread Yi Liu
On 2024/9/30 17:26, Zhenzhong Duan wrote: From: Clément Mathieu--Drif This will be used to implement the device IOTLB invalidation Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang --- hw/i386/intel_iommu.c | 39 ---

RE: [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation

2024-11-03 Thread Duan, Zhenzhong
>-Original Message- >From: Liu, Yi L >Sent: Monday, November 4, 2024 10:51 AM >Subject: Re: [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb >invalidation > >On 2024/9/30 17:26, Zhenzhong Duan wrote: >> According to spec, Page-Selective-within-Domain Invalidation (11b): >> >> 1

Re: [PATCH v4 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting

2024-11-03 Thread Yi Liu
On 2024/9/30 17:26, Zhenzhong Duan wrote: This gives user flexibility to turn off FS1GP for debug purpose. It is also useful for future nesting feature. When host IOMMU doesn't support FS1GP but vIOMMU does, nested page table on host side works after turn FS1GP off in vIOMMU. s/turn/turning R

Re: [PATCH v4 06/17] intel_iommu: Implement stage-1 translation

2024-11-03 Thread Yi Liu
On 2024/11/4 11:05, Duan, Zhenzhong wrote: -Original Message- From: Liu, Yi L Sent: Sunday, November 3, 2024 10:22 PM Subject: Re: [PATCH v4 06/17] intel_iommu: Implement stage-1 translation On 2024/9/30 17:26, Zhenzhong Duan wrote: From: Yi Liu This adds stage-1 page table walkin

Re: [PATCH v4 10/17] intel_iommu: Process PASID-based iotlb invalidation

2024-11-03 Thread Yi Liu
On 2024/11/4 13:40, Duan, Zhenzhong wrote: -Original Message- From: Liu, Yi L Sent: Monday, November 4, 2024 10:51 AM Subject: Re: [PATCH v4 10/17] intel_iommu: Process PASID-based iotlb invalidation On 2024/9/30 17:26, Zhenzhong Duan wrote: PASID-based iotlb (piotlb) is used during

Re: [PATCH v3 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose scalable modern mode

2024-11-03 Thread CLEMENT MATHIEU--DRIF
On 04/11/2024 04:24, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/9/29 10:44, Duan, Zhenzhong wrote >>> >>> A question here: >>> >>> Are there any other major featu

Re: [PATCH 15/23] rust: introduce alternative implementation of offset_of!

2024-11-03 Thread Junjie Mao
Paolo Bonzini writes: > From: Junjie Mao > > offset_of! was stabilized in Rust 1.77.0. Use an alternative implemenation > that was found on the Rust forums, and whose author agreed to license as > MIT for use in QEMU. > > The alternative allows only one level of field access, but apart > from

Re: [PATCH] target/arm: Fix SVE SDOT/UDOT/USDOT (4-way, indexed)

2024-11-03 Thread Richard Henderson
On 11/1/24 18:55, Peter Maydell wrote: Our implementation of the indexed version of SVE SDOT/UDOT/USDOT got the calculation of the inner loop terminator wrong. Although we correctly account for the element size when we calculate the terminator for the first iteration: intptr_t segend = MIN(1

[PATCH V3 0/5] Arch agnostic ACPI changes to support vCPU Hotplug (on Archs like ARM)

2024-11-03 Thread Salil Mehta via
Change Log == Patch V2 -> V3: 1. Addressed left over issues of x86 suggested by Igor Mammedov (Redhat): - Removed the `ACPICPUstatus::is_enabled` State as well as it was breaking the x86 migration - Above is in addition to `is_present` state which was removed in V2 - Dropped

[PATCH V3 3/5] hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states

2024-11-03 Thread Salil Mehta via
Reflect the QOM vCPUs ACPI CPU hotplug states in the `_STA.Present` and and `_STA.Enabled` bits when the guest kernel evaluates the ACPI `_STA` method during initialization, as well as when vCPUs are hot-plugged or hot-unplugged. If the CPU is present then the its `enabled` status can be fetched us

[PATCH V3 4/5] tests/qtest/bios-tables-test: Update DSDT golden masters for x86/{pc, q35}

2024-11-03 Thread Salil Mehta via
Update DSDT golden master files for x86/pc and x86/q35 platforms to accommodate changes made in the architecture-agnostic CPU AML. These updates notify the guest OS of vCPU hot-plug and hot-unplug status using the ACPI `_STA.Enabled` bit. The following is a diff of the changes in the .dsl file gen

[PATCH V3 1/5] hw/acpi: Make CPUs ACPI `presence` conditional during vCPU hot-unplug

2024-11-03 Thread Salil Mehta via
On most architectures, during vCPU hot-plug and hot-unplug actions, the firmware or VMM/QEMU can update the OS on vCPU status by toggling the ACPI method `_STA.Present` bit. However, certain CPU architectures prohibit [1] modifications to a CPU’s `presence` status after the kernel has booted. This

[PATCH V3 5/5] hw/acpi: Update GED with vCPU Hotplug VMSD for migration

2024-11-03 Thread Salil Mehta via
The ACPI CPU hotplug states must be migrated along with other vCPU hotplug states to the destination VM. Update the GED's VM State Description (VMSD) table subsection to conditionally include the CPU Hotplug VM State Description (VMSD). Excerpt of GED VMSD State Dump at Source: "acpi-ged (16)

[PATCH V3 2/5] qtest: allow ACPI DSDT Table changes

2024-11-03 Thread Salil Mehta via
list changed files in tests/qtest/bios-tables-test-allowed-diff.h Reported-by: Zhao Liu Signed-off-by: Salil Mehta --- tests/qtest/bios-tables-test-allowed-diff.h | 41 + 1 file changed, 41 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtes

RE: [PATCH V2 0/6] Arch agnostic ACPI changes to support vCPU Hotplug (on Archs like ARM)

2024-11-03 Thread Salil Mehta via
Hello, Please ignore this patch-set as there was some issue w.r.t x86. Details are in the V3 patch-set sent for review today. V3 has fixed almost all of the issues identified by Igor in the V1 patch-set in relation to x86. Please have a look at the below V3 patch-set: [PATCH V3 0/5] Arch agnost

Re: [PATCH 21/36] next-cube: use qemu_irq to drive int_status in next_scr2_rtc_update()

2024-11-03 Thread Thomas Huth
Am Wed, 23 Oct 2024 09:58:37 +0100 schrieb Mark Cave-Ayland : > Rather than directly clear bit 3 in int_status in next_scr2_rtc_update(), use > a qemu_irq to drive the equivalent NEXT_PWR_I signal. > > Signed-off-by: Mark Cave-Ayland > --- > hw/m68k/next-cube.c | 5 - > 1 file changed, 4 in

Re: [PATCH 22/36] next-cube: separate rtc read and write shift logic

2024-11-03 Thread Thomas Huth
Am Wed, 23 Oct 2024 09:58:38 +0100 schrieb Mark Cave-Ayland : > Introduce a new next_rtc_cmd_is_write() function to determine if an rtc > command > is a read or write, and start by using it to avoid shifting the rtc input > value > if a rtc read command is executed. > > Signed-off-by: Mark Cave

Re: [PATCH] hw/pci: Add parenthesis to PCI_BUILD_BDF macro

2024-11-03 Thread Philippe Mathieu-Daudé
On 1/11/24 18:59, Roque Arcudia Hernandez wrote: The bus parameter in the macro PCI_BUILD_BDF is not surrounded by parenthesis. This can create a compile error when warnings are treated as errors or can potentially create runtime errors due to the operator precedence. For instance: file.c:x:3

[PULL 0/1] Seabios hppa v17 patches

2024-11-03 Thread deller
From: Helge Deller The following changes since commit 92ec7805190313c9e628f8fc4eb4f932c15247bd: Merge tag 'pull-riscv-to-apply-20241031-1' of https://github.com/alistair23/qemu into staging (2024-10-31 16:34:25 +) are available in the Git repository at: https://github.com/hdeller/qemu

Re: [PATCH v3 2/2] ui/input-legacy.c: remove unused legacy qemu_add_kbd_event_handler() function

2024-11-03 Thread Philippe Mathieu-Daudé
On 1/11/24 17:11, Mark Cave-Ayland wrote: Since the last keyboard device has now been converted over to use qemu_input_handler_register(), the legacy qemu_add_kbd_event_handler() function is now unused and can be removed. Signed-off-by: Mark Cave-Ayland Reviewed-by: Alex Bennée --- include/u

[PATCH v4 01/26] hw/ppc/e500: Do not leak struct boot_info

2024-11-03 Thread Bernhard Beschow
The struct is allocated once with g_new0() but never free()'d. Fix the leakage by adding an attribute to struct PPCE500MachineState which avoids the allocation. While at it remove the obsolete /*< private >*/ markers. Signed-off-by: Bernhard Beschow --- hw/ppc/e500.h | 9 +++-- hw/ppc/e500

[PATCH v4 20/26] hw/sd/sdhci: Prefer DEFINE_TYPES() macro

2024-11-03 Thread Bernhard Beschow
Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow --- hw/sd/sdhci.c | 62 +-- 1 file changed, 26 insertions(+), 36 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index ed01499391..dbe5c2340c 100644 --- a/hw/sd/sdhci.c +++ b/hw

[PATCH v4 26/26] MAINTAINERS: Add hw/gpio/gpio_pwr.c

2024-11-03 Thread Bernhard Beschow
The device is only used in the ARM virt machine and designed to be used on top of pl061 for use cases such as ARM Trusted Firmware. Add it to the same section as hw/gpio/pl061.c. Signed-off-by: Bernhard Beschow --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAI

[PATCH v6 12/15] hw/vmapple/cfg: Introduce vmapple cfg region

2024-11-03 Thread Phil Dennis-Jordan
From: Alexander Graf Instead of device tree or other more standardized means, VMApple passes platform configuration to the first stage boot loader in a binary encoded format that resides at a dedicated RAM region in physical address space. This patch models this configuration space as a qdev dev

[PATCH v6 09/15] gpex: Allow more than 4 legacy IRQs

2024-11-03 Thread Phil Dennis-Jordan
From: Alexander Graf Some boards such as vmapple don't do real legacy PCI IRQ swizzling. Instead, they just keep allocating more board IRQ lines for each new legacy IRQ. Let's support that mode by giving instantiators a new "nr_irqs" property they can use to support more than 4 legacy IRQ lines.

[PATCH v6 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

2024-11-03 Thread Phil Dennis-Jordan
MacOS provides a framework (library) that allows any vmm to implement a paravirtualized 3d graphics passthrough to the host metal stack called ParavirtualizedGraphics.Framework (PVG). The library abstracts away almost every aspect of the paravirtualized device model and only provides and receives c

[PATCH v6 11/15] hw/vmapple/bdif: Introduce vmapple backdoor interface

2024-11-03 Thread Phil Dennis-Jordan
From: Alexander Graf The VMApple machine exposes AUX and ROOT block devices (as well as USB OTG emulation) via virtio-pci as well as a special, simple backdoor platform device. This patch implements this backdoor platform device to the best of my understanding. I left out any USB OTG parts; they

[PATCH v6 00/15] macOS PV Graphics and new vmapple machine type

2024-11-03 Thread Phil Dennis-Jordan
This patch set introduces a new ARM and macOS HVF specific machine type called "vmapple", as well as a family of display devices based on the ParavirtualizedGraphics.framework in macOS. One of the display adapter variants, apple-gfx-mmio, is required for the new machine type, while apple-gfx-pci ca

[PATCH v6 04/15] hw/display/apple-gfx: Adds configurable mode list

2024-11-03 Thread Phil Dennis-Jordan
This change adds a property 'display_modes' on the graphics device which permits specifying a list of display modes. (screen resolution and refresh rate) The property is an array of a custom type to make the syntax slightly less awkward to use, for example: -device '{"driver":"apple-gfx-pci", "di

[PATCH v6 10/15] hw/vmapple/aes: Introduce aes engine

2024-11-03 Thread Phil Dennis-Jordan
From: Alexander Graf VMApple contains an "aes" engine device that it uses to encrypt and decrypt its nvram. It has trivial hard coded keys it uses for that purpose. Add device emulation for this device model. Signed-off-by: Alexander Graf Signed-off-by: Phil Dennis-Jordan --- v3: * Rebased

[PATCH v6 07/15] hw/misc/pvpanic: Add MMIO interface

2024-11-03 Thread Phil Dennis-Jordan
From: Alexander Graf In addition to the ISA and PCI variants of pvpanic, let's add an MMIO platform device that we can use in embedded arm environments. Signed-off-by: Alexander Graf Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Phil Dennis-Jordan Revie

Re: [PATCH v4 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

2024-11-03 Thread Phil Dennis-Jordan
On Thu, 31 Oct 2024 at 07:52, Akihiko Odaki wrote: > On 2024/10/30 6:16, Phil Dennis-Jordan wrote: > > > > > > On Tue, 29 Oct 2024 at 08:42, Akihiko Odaki > > wrote: > > > > On 2024/10/29 6:06, Phil Dennis-Jordan wrote: > > > > > > > > > On Mon

[PATCH v6 06/15] hw: Add vmapple subdir

2024-11-03 Thread Phil Dennis-Jordan
From: Alexander Graf We will introduce a number of devices that are specific to the vmapple target machine. To keep them all tidily together, let's put them into a single target directory. Signed-off-by: Alexander Graf Signed-off-by: Phil Dennis-Jordan Reviewed-by: Akihiko Odaki --- MAINTAIN

[PATCH v6 13/15] hw/vmapple/virtio-blk: Add support for apple virtio-blk

2024-11-03 Thread Phil Dennis-Jordan
From: Alexander Graf Apple has its own virtio-blk PCI device ID where it deviates from the official virtio-pci spec slightly: It puts a new "apple type" field at a static offset in config space and introduces a new barrier command. This patch first creates a mechanism for virtio-blk downstream c

[PATCH] hw/intc/arm-gicv3*: Refactor GICv3 CPU reginfo to have common invocation

2024-11-03 Thread Salil Mehta via
Refactor GICv3 code for TCG and KVM to initialize the GIC CPU interface register information by introducing a new common hook `ARMGICv3CommonClass::init_cpu_reginfo`. This hook can be assigned to the respective TCG or KVM variants during the GICv3 initialization phase and invoked during the GICv3 r

Re: [PATCH v2 4/4] hw/sensor/tmp105: Convert printf() to trace event, add tracing for read/write access

2024-11-03 Thread Philippe Mathieu-Daudé
On 3/11/24 11:33, Bernhard Beschow wrote: printf() unconditionally prints to the console which disturbs `-serial stdio`. Fix that by converting into a trace event. While at it, add some tracing for read and write access. Fixes: 7e7c5e4c1ba5 "Nokia N800 machine support (ARM)." Signed-off-by: Bern

[PATCH v2] aspeed: Don't set always boot properties of the emmc device

2024-11-03 Thread Cédric Le Goater
Commit e554e45b4478 ("aspeed: Tune eMMC device properties to reflect HW strapping") added support to boot from an eMMC device by setting the boot properties of the eMMC device. This change made the assumption that the device always has boot areas. However, if the machine boots from the flash devic

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