Re: [PATCH v3 07/11] hw/sh4/r2d: Realize IDE controller before accessing it

On 13/10/2024 06.53, Guenter Roeck wrote: On 10/12/24 07:06, Bernhard Beschow wrote: Am 12. Oktober 2024 09:40:27 UTC schrieb Thomas Huth : On 12/10/2024 00.48, Philippe Mathieu-Daudé wrote: On 11/10/24 05:23, Thomas Huth wrote: On 03/05/2024 23.34, Guenter Roeck wrote: Hi, On Thu, Feb 08

Re: [PATCH v3 07/11] hw/sh4/r2d: Realize IDE controller before accessing it

On 10/12/24 07:06, Bernhard Beschow wrote: Am 12. Oktober 2024 09:40:27 UTC schrieb Thomas Huth : On 12/10/2024 00.48, Philippe Mathieu-Daudé wrote: On 11/10/24 05:23, Thomas Huth wrote: On 03/05/2024 23.34, Guenter Roeck wrote: Hi, On Thu, Feb 08, 2024 at 07:12:40PM +0100, Philippe Mathie

Re: [PATCH] tests/vm: update openbsd image to 7.6

On 2024-10-13 2:06 a.m., Thomas Huth wrote: On 13/10/2024 05.36, Brad Smith wrote: tests/vm: update openbsd image to 7.6 Maybe change the patch description to something more meaningful, e.g. a comment about the removed py3-tomli package ? Ok, I will post an updated diff. Signed-off-by: Br

[PATCH v2] tests/vm: update openbsd image to 7.6

tests/vm: update openbsd image to 7.6 Remove tomli as Python has been updated to 3.11. Signed-off-by: Brad Smith --- tests/vm/openbsd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/vm/openbsd b/tests/vm/openbsd index 49cab08782..dfd11c93f0 100755 --- a/tests/vm/

[PATCH] tests/vm: update openbsd image to 7.6

tests/vm: update openbsd image to 7.6 Signed-off-by: Brad Smith --- tests/vm/openbsd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/vm/openbsd b/tests/vm/openbsd index 49cab08782..dfd11c93f0 100755 --- a/tests/vm/openbsd +++ b/tests/vm/openbsd @@ -22,8 +22,8 @@ c

Re: [PATCH] tests/vm: update openbsd image to 7.6

On 13/10/2024 05.36, Brad Smith wrote: tests/vm: update openbsd image to 7.6 Maybe change the patch description to something more meaningful, e.g. a comment about the removed py3-tomli package ? Signed-off-by: Brad Smith --- tests/vm/openbsd | 6 +++--- 1 file changed, 3 insertions(+),

Re: [PULL v3 00/18] Rust initial PoC + meson changes for 2024-10-07

On Fri, 11 Oct 2024 at 18:13, Paolo Bonzini wrote: > > The following changes since commit b5ab62b3c0050612c7f9b0b4baeb44ebab42775a: > > Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging > (2024-10-04 19:28:37 +0100) > > are available in the Git repository at: > > https:

Re: [PATCH v16 04/13] s390x/pci: Avoid creating zpci for VFs

On 2024/10/11 0:44, Cédric Le Goater wrote: Hello Akihiko, Sorry for the late reply. On 9/18/24 17:32, Akihiko Odaki wrote: On 2024/09/18 17:02, Cédric Le Goater wrote: Hello, On 9/13/24 05:44, Akihiko Odaki wrote: VFs are automatically created by PF, and creating zpci for them will result

Re: [PATCH v16 03/13] hw/ppc/spapr_pci: Do not reject VFs created after a PF

On 2024/10/12 2:22, Shivaprasad G Bhat wrote: On 9/18/24 7:57 PM, Cédric Le Goater wrote: Adding :   Harsh for QEMU/PPC pseries machine,   Shivaprasad for KVM/PPC VFIO and IOMMU support. Thanks, C. On 9/13/24 05:44, Akihiko Odaki wrote: A PF may automatically create VFs and the PF may be f

Re: [PATCH v2 00/19] UI-related fixes & shareable 2d memory with -display dbus

On 2024/10/08 21:50, marcandre.lur...@redhat.com wrote: From: Marc-André Lureau Hi, This series adds Listener.Unix.Map interface to -display dbus, to allow shared memory for the display (similar to Listener.Win32.Map interface). While working on it, I collected a few fixes. I can re-send them

Re: [PATCH v6] i386/cpu: fixup number of addressable IDs for logical processors in the physical package

On 10/9/2024 11:56 AM, Chuang Xu wrote: When QEMU is started with: -cpu host,migratable=on,host-cache-info=on,l3-cache=off -smp 180,sockets=2,dies=1,cores=45,threads=2 On Intel platform: CPUID.01H.EBX[23:16] is defined as "max number of addressable IDs for logical processors in the physical pack

Re: [PULL v3 00/18] Rust initial PoC + meson changes for 2024-10-07

On Sat, 12 Oct 2024 at 11:54, Peter Maydell wrote: > > On Fri, 11 Oct 2024 at 18:13, Paolo Bonzini wrote: > > > > The following changes since commit b5ab62b3c0050612c7f9b0b4baeb44ebab42775a: > > > > Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging > > (2024-10-04 19:28:

Re: [PATCH v3 07/11] hw/sh4/r2d: Realize IDE controller before accessing it

Am 12. Oktober 2024 09:40:27 UTC schrieb Thomas Huth : >On 12/10/2024 00.48, Philippe Mathieu-Daudé wrote: >> On 11/10/24 05:23, Thomas Huth wrote: >>> On 03/05/2024 23.34, Guenter Roeck wrote: Hi, On Thu, Feb 08, 2024 at 07:12:40PM +0100, Philippe Mathieu-Daudé wrote: > We s

Re: [PATCH 0/4] Consolidate lan9118 phy implementations

Am 5. Oktober 2024 20:57:44 UTC schrieb Bernhard Beschow : >hw/net/imx_fec and hw/net/lan9118 implement the same Ethernet PHY with similar > >but not quite the same code. This series consolidates the implementations into > >one to fix code duplication. It then continues to make the code more rea

What is the status of the performance of D-Bus? Should it be used?

Hi, I have a few questions regarding the status of D-Bus. Normally, D-Bus should be used for direct input/output with QEMU (if only local access is needed). The driver is not in a good state and needs to be replaced though, correct? Should I still use D-Bus, or is there an alternative that is b

Re: [PATCH v3 1/2] exec/tswap: Massage target_needs_bswap() definition

On 10/10/24 10:52, Philippe Mathieu-Daudé wrote: Invert target_needs_bswap() comparison to match the COMPILING_PER_TARGET definition (2 lines upper). Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20241004162118.84570-2-phi...@linaro.org> --- include/exec/tswap.h | 2 +- 1 file changed,

Re: [PATCH v3 2/2] gdbstub/helpers: Introduce ldtul_$endian_p() helpers

On 10/10/24 10:52, Philippe Mathieu-Daudé wrote: Introduce ldtul_le_p() and ldtul_be_p() to use directly in place of ldtul_p() when a target endianness is fixed. Signed-off-by: Philippe Mathieu-Daudé --- include/gdbstub/helpers.h | 4 1 file changed, 4 insertions(+) Reviewed-by: Richar

Re: [PATCH v2 2/2] hw/ppc/e500: Reuse TYPE_GPIO_PWR

Am 7. Oktober 2024 21:13:22 UTC schrieb "Philippe Mathieu-Daudé" : >On 5/10/24 07:02, Bernhard Beschow wrote: >> Taking inspiration from the ARM virt machine, port away from >> qemu_allocate_irq() by reusing TYPE_GPIO_PWR. >> >> Signed-off-by: Bernhard Beschow >> --- >> hw/ppc/e500.c | 16

Re: [PATCH v2 08/23] hw/ppc/ppce500_ccsr: Log access to unimplemented registers

Am 6. Oktober 2024 17:12:16 UTC schrieb BALATON Zoltan : >On Sat, 5 Oct 2024, Bernhard Beschow wrote: >> The CCSR space is just a container which is meant to be covered by platform >> device memory regions. However, QEMU only implements a subset of these >> devices. >> Add some logging to see w

Re: [PATCH] migration: Put thread names together with macros

On Sat, Oct 12, 2024 at 1:29 AM Fabiano Rosas wrote: > Peter Xu writes: > > > Keep migration thread names together, so it's easier to see a list of all > > possible migration threads. > > > > Still two functional changes below besides the macro defintions: > > > > - There's one dirty rate thre

Re: [PATCH v6] i386/cpu: fixup number of addressable IDs for logical processors in the physical package

On 10/12/2024 4:10 PM, Chuang Xu wrote: Hi, Xiaoyao On 10/12/24 下午3:13, Xiaoyao Li wrote: On 10/9/2024 11:56 AM, Chuang Xu wrote: When QEMU is started with: -cpu host,migratable=on,host-cache-info=on,l3-cache=off -smp 180,sockets=2,dies=1,cores=45,threads=2 On Intel platform: CPUID.01H.EBX[23

Re: [PATCH v6] i386/cpu: fixup number of addressable IDs for logical processors in the physical package

> > > > +    if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { > > > > +    *ebx |= threads_per_pkg << 16; > > > > +    } else { > > > > +    *ebx |= 1 << apicid_pkg_offset(&topo_info) << 16; > > > > +    } > > > > > > you need to handle the overflow

Re: [PATCH v6] i386/cpu: fixup number of addressable IDs for logical processors in the physical package

On 10/9/2024 11:56 AM, Chuang Xu wrote: When QEMU is started with: -cpu host,migratable=on,host-cache-info=on,l3-cache=off -smp 180,sockets=2,dies=1,cores=45,threads=2 On Intel platform: CPUID.01H.EBX[23:16] is defined as "max number of addressable IDs for logical processors in the physical pack

Re: [PATCH v3 2/6] i386/cpu: add IsDefined flag to smp-cache property

Hi Alireze, On Thu, Oct 10, 2024 at 12:18:18PM +0100, Alireza Sanaee wrote: > Date: Thu, 10 Oct 2024 12:18:18 +0100 > From: Alireza Sanaee > Subject: [PATCH v3 2/6] i386/cpu: add IsDefined flag to smp-cache property > X-Mailer: git-send-email 2.34.1 > > This commit adds IsDefined flag to the obj

Re: [PATCH v6] i386/cpu: fixup number of addressable IDs for logical processors in the physical package

On 10/12/24 下午4:21, Xiaoyao Li wrote: On 10/9/2024 11:56 AM, Chuang Xu wrote: When QEMU is started with: -cpu host,migratable=on,host-cache-info=on,l3-cache=off -smp 180,sockets=2,dies=1,cores=45,threads=2 On Intel platform: CPUID.01H.EBX[23:16] is defined as "max number of addressable IDs fo

Re: [PATCH v3 07/11] hw/sh4/r2d: Realize IDE controller before accessing it

On 12/10/2024 00.48, Philippe Mathieu-Daudé wrote: On 11/10/24 05:23, Thomas Huth wrote: On 03/05/2024 23.34, Guenter Roeck wrote: Hi, On Thu, Feb 08, 2024 at 07:12:40PM +0100, Philippe Mathieu-Daudé wrote: We should not wire IRQs on unrealized device. Signed-off-by: Philippe Mathieu-Daudé

Re: [PATCH] docs/devel: Prohibit calling object_unparent() for memory region

On 2024/10/08 22:33, Peter Maydell wrote: On Thu, 29 Aug 2024 at 06:46, Akihiko Odaki wrote: Hi; sorry it's taken me so long to get back to this patch, but I've now re-read some of the discussion in the other threads. I generally agree with your reasoning and think we do need to update the docs

Re: [PATCH v6] i386/cpu: fixup number of addressable IDs for logical processors in the physical package

Hi, Xiaoyao On 10/12/24 下午3:13, Xiaoyao Li wrote: On 10/9/2024 11:56 AM, Chuang Xu wrote: When QEMU is started with: -cpu host,migratable=on,host-cache-info=on,l3-cache=off -smp 180,sockets=2,dies=1,cores=45,threads=2 On Intel platform: CPUID.01H.EBX[23:16] is defined as "max number of address

Re: [PATCH] tap-linux: Open ipvtap and macvtap

On 2024/10/09 16:41, Jason Wang wrote: On Tue, Oct 8, 2024 at 2:52 PM Akihiko Odaki wrote: ipvtap and macvtap create a file for each interface unlike tuntap, which creates one file shared by all interfaces. Try to open a file dedicated to the interface first for ipvtap and macvtap. Manageme

Re: [PATCH v6] i386/cpu: fixup number of addressable IDs for logical processors in the physical package

> This also is consistency with the SDM, where the comment for bit 23-16 of > CPUID.1:EBX is: > > The nearest power-of-2 integer that is not smaller than EBX[23:16] is > the number of unique initial APIC IDs reserved for addressing > different logical processors in a physical package. > > W

[PATCH v3 6/7] i386/pc: Support cache topology in -machine for PC machine

Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC machine. Additionally, add the document of "-machine smp-cache" in qemu-options.hx. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v2: * Polished the document. (Jonathan)

[PATCH v3 4/7] i386/cpu: Support thread and module level cache topology

Allow cache to be defined at the thread and module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- target/i386/cpu.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(

[PATCH v3 2/7] qapi/qom: Define cache enumeration and properties for machine

The x86 and ARM need to allow user to configure cache properties (current only topology): * For x86, the default cache topology model (of max/host CPU) does not always match the Host's real physical cache topology. Performance can increase when the configured virtual topology is closer to th

[PATCH v3 3/7] hw/core: Check smp cache topology support for machine

Add cache_supported flags in SMPCompatProps to allow machines to configure various caches support. And check the compatibility of the cache properties with the machine support in machine_parse_smp_cache(). Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes

[PATCH v3 1/7] hw/core: Make CPU topology enumeration arch-agnostic

Cache topology needs to be defined based on CPU topology levels. Thus, define CPU topology enumeration in qapi/machine.json to make it generic for all architectures. To match the general topology naming style, rename CPU_TOPO_LEVEL_* to CPU_TOPOLOGY_LEVEL_*, and rename SMT and package levels to th

[PATCH v3 7/7] i386/cpu: add has_caches flag to check smp_cache configuration

From: Alireza Sanaee Add has_caches flag to SMPCompatProps, which helps in avoiding extra checks for every single layer of caches in x86 (and ARM in future). Signed-off-by: Alireza Sanaee Signed-off-by: Zhao Liu --- Note: Picked from Alireza's series with the changes: * Moved the flag to SMPC

[PATCH v3 5/7] i386/cpu: Update cache topology with machine's configuration

User will configure smp cache topology via -machine smp-cache. For this case, update the x86 CPUs' cache topology with user's configuration in MachineState. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since RFC v2: * Used smp_cache array to override

[PATCH v3 0/7] Introduce SMP Cache Topology

Hi all, Compared with v2 [1], the changes in v3 are quite minor, and most of patches (except for patch 1 and 7) have received Jonathan’s R/b (thanks Jonathan!). Meanwhile, ARM side has also worked a lot on the smp-cache based on this series [2], so I think we are very close to the final merge, to

Re: [PATCH v3 12/14] hw/vmapple/cfg: Introduce vmapple cfg region

On 2024/10/09 22:08, Phil Dennis-Jordan wrote: On Mon, 7 Oct 2024 at 20:04, Akihiko Odaki > wrote: On 2024/10/07 23:10, Phil Dennis-Jordan wrote: > > > On Sat, 5 Oct 2024 at 07:35, Akihiko Odaki mailto:akihiko.od...@daynix.com> >