On 10/8/24 12:47 AM, Peter Maydell wrote:
In commit b88cfee90268cad we defined masks for the IBRD and FBRD
integer and fractional baud rate divider registers, to prevent the
guest from writing invalid values which could cause division-by-zero.
Unfortunately we got the mask values the wrong way ar
On 10/9/24 4:58 PM, Denis V. Lunev wrote:
> RW permissions could not be lifted from the preallocation filter if
> truncate operation has not been finished. In the other case this would
> mean WRITE operation (image truncate) called after the return from
> inactivate call. This is definitely a contr
On Wed, 9 Oct 2024, Richard Henderson wrote:
Based-on: 20241009000453.315652-1-richard.hender...@linaro.org
("[PATCH v3 00/20] accel/tcg: Introduce tlb_fill_align hook")
The initial idea was: how much can we do with an intelligent data
structure for the same cost as a linear search through an ar
This patch implements multiplexing capability of several backend
devices, which opens up an opportunity to use a single frontend
device on the guest, which can be manipulated from several
backend devices.
The idea of the change is trivial: keep list of backend devices
(up to 4), init them on deman
This adds a few lines describing `mux-be` multiplexer configuration
for multiplexing several backend devices with a single frontend
device.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
qemu-options.hx | 46 ++
1 f
In the following patches `MuxChardev` struct will suport backend
multiplexing, the `mux_cnt` struct member has very common name
and does not reflect the actual meaning: number of frontends
attached to a mux. This patch renames the `mux_cnt` to `fe_cnt`.
No other functional changes made.
Signed-off
Patch introduces `mux-be-id=ID` option for all chardev devices
and TYPE_CHARDEV_MUX_BE type for distinction different types
of multiplexers: frontend (current "mux" type) and backend
(new "mux-be" type). Actual attach of the chardev to the
multiplexer and mux-be implementation will follow.
Signed-
The test is trivial: several backends, 1 `mux-be`, 1 frontend
do the buffer write and read. Pipe is used for EAGAIN verification.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
tests/unit/test-char.c | 217 -
1 file cha
Mux is a character backend (host side) device, which multiplexes
multiple frontends with one backend device. The following is a
few lines from the QEMU manpage [1]:
A multiplexer is a "1:N" device, and here the "1" end is your
specified chardev backend, and the "N" end is the various parts
o
On Tue, 2024-10-08 at 11:17 -0700, Richard Henderson wrote:
> On 10/5/24 13:35, Ilya Leoshkevich wrote:
> > > How can we handle the long-running syscalls?
> > > Just waiting sounds unsatisfying.
> > > Sending a reserved host signal may alter the guest's behaviour if
> > > a
> > > syscall like pause
Peter Xu writes:
> On Wed, Oct 09, 2024 at 04:18:31PM -0400, Steven Sistare wrote:
>> Yes, I am also brainstorming along these lines, looking for more gotcha's,
>> but its a big design change. I don't love it so far.
>>
>> These issues all creep in because of transfer mode. Exec mode did not ha
On 9/25/24 13:48, Pierrick Bouvier wrote:
Contrib plugins have been built out of tree so far, thanks to a Makefile.
However, it is quite inconvenient for maintenance, as we may break them,
especially for specific architectures.
First patches are fixing warnings for existing plugins, then we add
Hi Roman
On Wed, Oct 9, 2024 at 9:47 PM Roman Penyaev wrote:
> Mux is a character backend (host side) device, which multiplexes
> multiple frontends with one backend device. The following is a
> few lines from the QEMU manpage [1]:
>
> A multiplexer is a "1:N" device, and here the "1" end is y
On 10/8/2024 3:48 PM, Peter Xu wrote:
On Tue, Oct 08, 2024 at 04:11:38PM -0300, Fabiano Rosas wrote:
As of half an hour ago =) We could put a feature branch up and work
together, if you have more concrete thoughts on how this would look like
let me know.
[I'll hijack this thread with one more
Remove force_mmio and place the expression into the IF
expression, behind the short-circuit logic expressions
that might eliminate its computation.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/c
This has been functionally replaced by the IntervalTree.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 8 --
accel/tcg/cputlb.c| 64 ---
2 files changed, 72 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
in
Change from a linear search on the victim tlb
to a balanced binary tree search on the interval tree.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 62 +++---
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/accel/tcg/cputlb.c b/a
Update the addr_write copy within an interval tree node.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 95f78afee6..ec989f1290 100644
--- a/accel/tcg/cput
The INVALID bit should only be auto-cleared when we have
just called tlb_fill, not along the victim_tlb_hit path.
In atomic_mmu_lookup, rename tlb_addr to flags, as that
is what we're actually carrying around.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 33 ++--
Often we already have the CPUTLBDescFast structure pointer.
Allows future code simplification.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index c1838412e8..e
Provide a general-purpose release-all-nodes operation, that allows
for the IntervalTreeNode to be embeded within a larger structure.
Signed-off-by: Richard Henderson
---
include/qemu/interval-tree.h | 11 +++
util/interval-tree.c | 20
util/selfmap.c
Update the addr_write copy within each interval tree node.
Tidy the iteration within the other two loops as well.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb
Add the data structures for tracking softmmu pages via
a balanced interval tree. So far, only initialize and
destroy the data structure.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 3 +++
accel/tcg/cputlb.c| 11 +++
2 files changed, 14 insertions(+)
diff --git a/i
We expect masked address spaces to be quite large, e.g. 56 bits
for AArch64 top-byte-ignore mode. We do not expect addr+len to
wrap around, but it is possible with AArch64 guest flush range
instructions.
Convert this unlikely case to a full tlb flush. This can simplify
the subroutines actually p
On Wed, Oct 09, 2024 at 02:43:44PM -0400, Steven Sistare wrote:
> On 10/8/2024 3:48 PM, Peter Xu wrote:
> > On Tue, Oct 08, 2024 at 04:11:38PM -0300, Fabiano Rosas wrote:
> > > As of half an hour ago =) We could put a feature branch up and work
> > > together, if you have more concrete thoughts on
On Wed, 9 Oct 2024 at 09:39, wrote:
>
> From: Marc-André Lureau
>
> The following changes since commit 2af37e791906cfda42cb9604a16d218e56994bb1:
>
> Merge tag 'pull-request-2024-10-07' of https://gitlab.com/thuth/qemu into
> staging (2024-10-07 12:55:02 +0100)
>
> are available in the Git repo
On Tue, 8 Oct 2024 at 15:16, Thomas Huth wrote:
>
> On 08/10/2024 16.13, Peter Maydell wrote:
> > The qmp-cmd-test test takes typically about 15s on my local machine.
> > On the k8s runners it takes usually 20s but sometimes about 60s,
> > because the k8s runners have wildly variable execution tim
On Tue, 8 Oct 2024 at 19:51, Richard Henderson
wrote:
>
> The following changes since commit 2af37e791906cfda42cb9604a16d218e56994bb1:
>
> Merge tag 'pull-request-2024-10-07' of https://gitlab.com/thuth/qemu into
> staging (2024-10-07 12:55:02 +0100)
>
> are available in the Git repository at:
Hi All,
We have stumbled upon this bug in our production systems on QEMU 7.2.x.
This is a pretty nasty bug because it has the effect of causing the root
filesystem in the guest to switch into read only mode if our block
storage products change attachments to running virtual machines.
Could w
Looks like the stm32l4x5 is quite similar to my implementation. It didn’t exist
when I started with my implementation . I will take a closer look and work on
improving/extending the stm32l4x5 GPIO with my proposal. Is it OK if I rename
it to stm32_gpio? so it is clearer that the implementation i
This array is now write-only, and may be remove.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 1 -
accel/tcg/cputlb.c| 39 ---
2 files changed, 8 insertions(+), 32 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
in
While this may at present be overly complicated for use
by single page flushes, do so with the expectation that
this will eventually allow simplification of large pages.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 61 +-
1 file changed, 3
Now that all targets have been converted to tlb_fill_align,
remove the tlb_fill hook.
Signed-off-by: Richard Henderson
---
include/hw/core/tcg-cpu-ops.h | 10 --
accel/tcg/cputlb.c| 19 ---
2 files changed, 4 insertions(+), 25 deletions(-)
diff --git a/includ
Vladimir Sementsov-Ogievskiy writes:
> On 30.09.24 17:07, Andrey Drobyshev wrote:
>> On 9/30/24 12:25 PM, Vladimir Sementsov-Ogievskiy wrote:
>>> [add migration maintainers]
>>>
>>> On 24.09.24 15:56, Andrey Drobyshev wrote:
[...]
>>>
>>> I doubt that this a correct way to go.
>>>
>>> As far
On Wed, Oct 09, 2024 at 04:18:31PM -0400, Steven Sistare wrote:
> Yes, I am also brainstorming along these lines, looking for more gotcha's,
> but its a big design change. I don't love it so far.
>
> These issues all creep in because of transfer mode. Exec mode did not have
> this
> problem, as
Thanks for your help.
- Michael
On 10/9/24 11:28, Paolo Bonzini wrote:
!---|
This Message Is From an External Sender
This message came from outside your organization.
|-
On Wed, Oct 09, 2024 at 03:06:53PM -0400, Peter Xu wrote:
> On Wed, Oct 09, 2024 at 02:43:44PM -0400, Steven Sistare wrote:
> > On 10/8/2024 3:48 PM, Peter Xu wrote:
> > > On Tue, Oct 08, 2024 at 04:11:38PM -0300, Fabiano Rosas wrote:
> > > > As of half an hour ago =) We could put a feature branch
On 10/9/2024 3:06 PM, Peter Xu wrote:
On Wed, Oct 09, 2024 at 02:43:44PM -0400, Steven Sistare wrote:
On 10/8/2024 3:48 PM, Peter Xu wrote:
On Tue, Oct 08, 2024 at 04:11:38PM -0300, Fabiano Rosas wrote:
As of half an hour ago =) We could put a feature branch up and work
together, if you have m
On 10/9/2024 3:59 PM, Peter Xu wrote:
On Wed, Oct 09, 2024 at 03:06:53PM -0400, Peter Xu wrote:
On Wed, Oct 09, 2024 at 02:43:44PM -0400, Steven Sistare wrote:
On 10/8/2024 3:48 PM, Peter Xu wrote:
On Tue, Oct 08, 2024 at 04:11:38PM -0300, Fabiano Rosas wrote:
As of half an hour ago =) We cou
On 10/9/24 09:27, BALATON Zoltan wrote:
On Wed, 9 Oct 2024, Richard Henderson wrote:
Based-on: 20241009000453.315652-1-richard.hender...@linaro.org
("[PATCH v3 00/20] accel/tcg: Introduce tlb_fill_align hook")
The initial idea was: how much can we do with an intelligent data
structure for the s
On 10/9/24 02:04, Richard Henderson wrote:
When we have a tlb miss, defer the alignment check to
the new tlb_fill_align hook. Move the existing alignment
check so that we only perform it with a tlb hit.
Signed-off-by: Richard Henderson
Reviewed-by: Helge Deller
On 10/9/24 02:04, Richard Henderson wrote:
Convert hppa_cpu_tlb_fill to hppa_cpu_tlb_fill_align so that we
can recognize alignment exceptions in the correct priority order.
Resolves: https://bugzilla.kernel.org/show_bug.cgi?id=219339
Signed-off-by: Richard Henderson
Reviewed-by: Helge Deller
On Mon, 7 Oct 2024 at 10:25, Akihiko Odaki wrote:
>
> > Theoretically, It should be safe to assume the callee creates
> > autoreleasepool by themselves as needed in general. We have bunch of
> > code to call Objective-C APIs without creating autoreleasepool in the
> > caller. Prac
On Wed, Oct 09, 2024 at 04:09:45PM -0400, Steven Sistare wrote:
> On 10/9/2024 3:06 PM, Peter Xu wrote:
> > On Wed, Oct 09, 2024 at 02:43:44PM -0400, Steven Sistare wrote:
> > > On 10/8/2024 3:48 PM, Peter Xu wrote:
> > > > On Tue, Oct 08, 2024 at 04:11:38PM -0300, Fabiano Rosas wrote:
> > > > > As
Peter Xu writes:
> The cleanup function can in many cases needs cleanup on its own.
>
> The major thing we want to do here is not referencing to_dst_file when
> without the file mutex. When at it, touch things elsewhere too to make it
> look slightly better in general.
>
> One thing to mention i
Recent QEMU changes around preallocate_set_perm mandates that it is not
possible to poll on aio_context inside this function anymore. Thus
truncate operation has been moved inside bottom half. This bottom half
is scheduled from preallocate_set_perm() and that is all.
This approach proven to be pro
RW permissions could not be lifted from the preallocation filter if
truncate operation has not been finished. In the other case this would
mean WRITE operation (image truncate) called after the return from
inactivate call. This is definitely a contract violation.
Signed-off-by: Denis V. Lunev
Rev
Recent QEMU changes around preallocate_set_perm mandates that it is not
possible to poll on aio_context inside this function anymore. Thus
truncate operation has been moved inside bottom half. This bottom half
is scheduled from preallocate_set_perm() and that is all.
This approach proven to be pro
On 10/9/24 4:58 PM, Denis V. Lunev wrote:
> Recent QEMU changes around preallocate_set_perm mandates that it is not
> possible to poll on aio_context inside this function anymore. Thus
> truncate operation has been moved inside bottom half. This bottom half
> is scheduled from preallocate_set_perm(
On 10/9/24 16:54, Andrey Drobyshev wrote:
On 10/9/24 4:58 PM, Denis V. Lunev wrote:
Recent QEMU changes around preallocate_set_perm mandates that it is not
possible to poll on aio_context inside this function anymore. Thus
truncate operation has been moved inside bottom half. This bottom half
is
On 9/30/24 5:24 PM, Andrey Drobyshev wrote:
> On 9/13/24 7:39 PM, Andrey Drobyshev wrote:
>> v2: https://lists.nongnu.org/archive/html/qemu-devel/2024-05/msg02396.html
>>
>> v2 -> v3:
>> * Added patch 12/12 "qcow2: add discard-subclusters option" which
>> makes subcluster-based discards optio
On Thu, Sep 19, 2024 at 06:52:37PM +0200, William Roche wrote:
> Hello David,
>
> I hope my last week email answered your interrogations about:
> - retrieving the valid data from the lost hugepage
> - the need of smaller pages to replace a failed large page
> - the interaction of memor
Yes, it looks like an easy backport. Adding Michael Tokarev and qemu-stable.
Paolo
On Wed, Oct 9, 2024 at 6:03 PM Michael Galaxy wrote:
>
> Hi All,
>
> We have stumbled upon this bug in our production systems on QEMU 7.2.x.
> This is a pretty nasty bug because it has the effect of causing the r
On 10/9/24 02:04, Richard Henderson wrote:
Add a new callback to handle softmmu paging. Return the page
details directly, instead of passing them indirectly to
tlb_set_page. Handle alignment simultaneously with paging so
that faults are handled with target-specific priority.
Route all calls th
Based-on: 20241009000453.315652-1-richard.hender...@linaro.org
("[PATCH v3 00/20] accel/tcg: Introduce tlb_fill_align hook")
The initial idea was: how much can we do with an intelligent data
structure for the same cost as a linear search through an array?
This is an initial installment along thes
The new tlb_fill_align hook returns page data via structure
rather than by function call, so we can make tlb_set_page_full
be local to cputlb.c. There are no users of tlb_set_page
or tlb_set_page_with_attrs, so those can be eliminated.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.
Because translation is special, we don't need the speed
of the direct-mapped softmmu tlb. We cache a lookups in
DisasContextBase within the translator loop anyway.
Drop the addr_code comparator from CPUTLBEntry.
Go directly to the IntervalTree for MMU_INST_FETCH.
Derive exec flags from read flags
CPUTLBEntryFull structures are no longer directly included within
the CPUState structure. Move the structure definition out of cpu.h
to reduce visibility.
Signed-off-by: Richard Henderson
---
include/exec/tlb-common.h | 63 +++
include/hw/core/cpu.h | 63
Link from the fast tlb entry to the interval tree node.
Signed-off-by: Richard Henderson
---
include/exec/tlb-common.h | 2 ++
accel/tcg/cputlb.c| 59 ++-
2 files changed, 23 insertions(+), 38 deletions(-)
diff --git a/include/exec/tlb-common.h b/inc
Probably never happens, but next patches will assume non-zero length.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index fd8da8586f..93b42d18ee 100644
--- a/accel/tcg/cputlb.c
+++ b/accel
We will have a need to flush only the "fast" portion
of the tlb, allowing re-fill from the "full" portion.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index b76a4eac4e
Add or replace an entry in the IntervalTree for each
page installed into softmmu. We do not yet use the
tree for anything else.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 34 --
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/accel/t
Ensure a common entry point for all code lookups.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 59ee766d51..61daa89e06 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/t
Flush a masked range of pages from the IntervalTree cache.
When the mask is not used there is a redundant comparison,
but that is better than duplicating code at this point.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 25 +
1 file changed, 25 insertions(+)
Flush a page from the IntervalTree cache.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index d964e1b2e8..772656c7f8 100644
--- a/accel/tcg/cputlb.c
+++ b/accel
On 9/10/24 12:08, Richard Henderson wrote:
Ensure a common entry point for all code lookups.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/10/24 12:08, Richard Henderson wrote:
Probably never happens, but next patches will assume non-zero length.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index fd8da8586f..93b42d1
On 9/10/24 12:08, Richard Henderson wrote:
We will have a need to flush only the "fast" portion
of the tlb, allowing re-fill from the "full" portion.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
Reviewed-by: Philippe
On 8/10/24 21:04, Richard Henderson wrote:
Split out of mmu_lookup.
Reviewed-by: Helge Deller
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/memop.h | 24
accel/tcg/cputlb.c | 16 ++--
2 files changed, 26 insertions(+),
On 10/9/24 08:08, Richard Henderson wrote:
Provide a general-purpose release-all-nodes operation, that allows
for the IntervalTreeNode to be embeded within a larger structure.
Signed-off-by: Richard Henderson
---
include/qemu/interval-tree.h | 11 +++
util/interval-tree.c | 2
On 10/9/24 08:08, Richard Henderson wrote:
We will have a need to flush only the "fast" portion
of the tlb, allowing re-fill from the "full" portion.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/accel/tcg
On 10/9/24 08:08, Richard Henderson wrote:
Often we already have the CPUTLBDescFast structure pointer.
Allows future code simplification.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cp
Hello,
Michael Tokarev, le sam. 05 oct. 2024 10:07:53 +0300, a ecrit:
> libslirp introduced new typedef after 4.8.0, slirp_os_socket, which
> is defined to SOCKET on windows, which, in turn, is a 64bit number.
> qemu uses int, so callback function prorotypes changed.
I have fixed the code in upst
On 10/9/24 08:08, Richard Henderson wrote:
While this may at present be overly complicated for use
by single page flushes, do so with the expectation that
this will eventually allow simplification of large pages.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 61 +++
The virt PMU related implemention should belong to virt
machine file rather than common pmu.c which can be used
for other implementations.
Make pmu.c generic by moving all the virt PMU event related
structures to it's appropriate place.
Signed-off-by: Atish Patra
---
hw/riscv/virt.c| 81 +++
We have TLB related event call back available now. Invoke
them from generic cpu helper code so that other machines can
implement those as well in the future. The virt machine is
the only user for now though.
Signed-off-by: Atish Patra
---
target/riscv/cpu_helper.c | 21 +++--
tar
The event ID can be a upto 56 bit value when sscofpmf is implemented.
Change the event to counter hashtable to store the keys as 64 bit value
instead of uint.
Signed-off-by: Atish Patra
---
target/riscv/pmu.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/targ
Richard Henderson writes:
> The probe_access_full_mmu function was designed for this purpose,
> and does not report the memory operation event to plugins.
I note the kdoc for probe_access_full_mmu has the wrong title. It might
be worth referencing the fault and instrumentation behaviour in the
p
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 85ef7452c0..18ba958f46 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -1148,8 +1148,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
>> [FEAT_7_2_EDX] = {
>> .type = CPUID_FEATURE_WORD,
>>
On Mon, Sep 30, 2024 at 12:01 AM Cindy Lu wrote:
>
> When using a VDPA device, it is important to ensure that the MAC
> address is correctly set. The MAC address in the hardware should
> match the MAC address from the QEMU command line. This is a recommended
> configuration and will allow the syst
On Mon, Sep 30, 2024 at 12:01 AM Cindy Lu wrote:
>
> When using a VDPA device, the following situations are
> also acceptable: the hardware MAC address is not 0,
> and the MAC address in the QEMU command line is 0.
>
> Signed-off-by: Cindy Lu
> ---
> hw/net/virtio-net.c | 12
> 1 fi
On Mon, Sep 30, 2024 at 12:01 AM Cindy Lu wrote:
>
> While the hardware MAC address is 0 and the MAC address in
> the QEMU command line is also 0, this configuration is
> acceptable.
>
> Signed-off-by: Cindy Lu
> ---
> hw/net/virtio-net.c | 11 +++
> 1 file changed, 11 insertions(+)
>
>
On 9 Oct 2024, at 12:10 AM, Fabiano Rosas wrote:
!---|
CAUTION: External Email
|---!
Peter Xu mailto:pet...@redhat.com>> writes:
On Tue, Oct 08, 2024 at 11:20:03AM
As shown below, if a virtio PCI device is attached under a pci-bridge, the MR
of VirtIOPCIRegion does not belong to any address space. So memory_region_find
cannot be used to search for this MR.
Introduce the virtio-pci and pci_bridge address spaces to solve this problem.
Before:
memory-region: p
On Tue, 8 Oct 2024 at 18:32, Richard Henderson
wrote:
>
> On 10/8/24 07:45, Peter Maydell wrote:
> > On Sat, 5 Oct 2024 at 21:06, Richard Henderson
> > wrote:
> >>
> >> Zero is the safe do-nothing value for callers to use.
> >>
> >> Signed-off-by: Richard Henderson
> >> ---
> >> target/arm/int
On Fri, 4 Oct 2024 at 06:17, Akihiko Odaki wrote:
> On 2024/09/28 17:57, Phil Dennis-Jordan wrote:
> > This change adds a property 'display_modes' on the graphics device
> > which permits specifying a list of display modes. (screen resolution
> > and refresh rate)
> >
> > PCI variant of apple-gfx
Recent QEMU changes around preallocate_set_perm mandates that it is not
possible to poll on aio_context inside this function anymore. Thus
truncate operation has been moved inside bottom half. This bottom half
is scheduled from preallocate_set_perm() and that is all.
This approach proven to be pro
On Sat, 5 Oct 2024 at 07:12, Akihiko Odaki wrote:
> On 2024/09/28 17:57, Phil Dennis-Jordan wrote:
> > From: Alexander Graf
> >
> > The VMApple machine exposes AUX and ROOT block devices (as well as USB
> OTG
> > emulation) via virtio-pci as well as a special, simple backdoor platform
> > device
Recent QEMU changes around preallocate_set_perm mandates that it is not
possible to poll on aio_context inside this function anymore. Thus
truncate operation has been moved inside bottom half. This bottom half
is scheduled from preallocate_set_perm() and that is all.
This approach proven to be pro
RW permissions could not be lifted from the preallocation filter if
truncate operation has not been finished. In the other case this would
mean WRITE operation (image truncate) called after the return from
inactivate call. This is definitely a contract violation.
Signed-off-by: Denis V. Lunev
CC:
From: Daniil Tatianin
The 'reconnect' option only allows to specify the time in seconds,
which is way too long for certain workflows.
We have a lightweight disk backend server, which takes about 20ms to
live update, but due to this limitation in QEMU, previously the guest
disk controller would h
From: Marc-André Lureau
The following changes since commit 2af37e791906cfda42cb9604a16d218e56994bb1:
Merge tag 'pull-request-2024-10-07' of https://gitlab.com/thuth/qemu into
staging (2024-10-07 12:55:02 +0100)
are available in the Git repository at:
https://gitlab.com/marcandre.lureau/qe
From: Octavian Purdila
Add path option to the pty char backend which will create a symbolic
link to the given path that points to the allocated PTY.
This avoids having to make QMP or HMP monitor queries to find out what
the new PTY device path is.
Based on patch from Paulo Neves:
https://patch
On 08/10/2024 18:25, Octavian Purdila wrote:
On Tue, Oct 8, 2024 at 4:27 AM Mark Cave-Ayland
wrote:
On 08/10/2024 02:18, Octavian Purdila wrote:
Add fifo32_peek() that returns the first element from the queue
without popping it.
Signed-off-by: Octavian Purdila
---
include/qemu/fifo32.h
From: Manos Pitsidianakis
This commit adds a re-implementation of hw/char/pl011.c in Rust.
How to build:
1. Configure a QEMU build with:
--enable-system --target-list=aarch64-softmmu --enable-rust
2. Launching a VM with qemu-system-aarch64 should use the Rust version
of the pl011 device
This will be useful in order to test QEMU's Rust code with nightly
clippy. It can also be used to check that the code builds, until the
minimum supported Rust version is lowered enough to allow enabling Rust
in other Dockerfiles too.
Use a separate container, instead of the Fedora one, to avoid t
KVM commit 191c8137a939 ("x86/kvm: Implement HWCR support")
introduced support for emulating HWCR MSR.
Add support for QEMU to save/load this MSR for migration purposes.
Signed-off-by: Gao Shiyuan
Signed-off-by: Wang Liang
---
target/i386/cpu.h | 5 +
target/i386/kvm/kvm.c | 12 ++
From: Pierrick Bouvier
s/mbmi1/mbmi/
When configuring with -Dx86_version >= 3, meson step works, but
compilation fails because option -mbmi1 is unknown.
Signed-off-by: Pierrick Bouvier
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
Link:
https://lore.kernel.org/r/20241004223715.1275428-1-p
Create a separate variable for compiler flags that enable
specific instruction set extensions, so that they can be used with
cc.compiles/cc.links.
Note that -mfpmath=sse is a code generation option but it does not
enable new instructions, therefore I did not make it part of
qemu_isa_flags.
Sugges
From: Manos Pitsidianakis
Set rust source code to diff=rust (built-in with new git versions)
and merge=binary for Cargo.lock files (they should not be merged but
auto-generated by cargo)
Reviewed-by: Alex Bennée
Reviewed-by: Zhao Liu
Signed-off-by: Manos Pitsidianakis
Link:
https://lore.kern
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