On 27/09/2024 02.51, jro...@linux.ibm.com wrote:
From: Jared Rossi
Remove panic-on-error from IPL functions such that a return code is propagated
back to the main IPL calling function (rather than terminating immediately),
which facilitates possible error recovery in the future.
A select few p
On 30/09/2024 09.48, Thomas Huth wrote:
On 27/09/2024 02.51, jro...@linux.ibm.com wrote:
From: Jared Rossi
Remove panic-on-error from virtio-scsi IPL specific functions so that error
recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Sign
Stefan Hajnoczi writes:
> On Thu, 26 Sept 2024 at 10:24, Alex Bennée wrote:
>> Another potential area for conversion was the VirtIO device and
>> vhost-user code which could expect to re-use a lot of the crates from
>> the rust-vmm project. However this did bring up the point of maintainer
>> b
Move code evaluation from preprocessor to compiler so
the if() ladder is always processed. Mostly to unify
style in not using TARGET_BIG_ENDIAN #ifdef anymore.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/mips
Since all code creating vCPUs now set the 'cpu-big-endian' property,
we can remove the target-specific #ifdef'ry in mips_cpu_reset_hold():
the CP0C0_BE bit is set using the property cpu->is_big_endian value.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.c | 3 ---
1 file changed, 3 d
Replace compile-time MO_TE evaluation by runtime mo_endian() one,
which expand target endianness from DisasContext.
Mechanical change using:
$ sed -i -e 's/MO_TE/mo_endian(ctx)/' \
$(git grep -l MO_TE target/mips)
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_helper.c
In order to re-use cpu_is_bigendian(), declare it on "internal.h"
after renaming it as cpu_is_bigendian_env().
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h| 6 ++
target/mips/tcg/ldst_helper.c | 15 +--
2 files changed, 11 insertions(+), 10 deletions(
Functions are easier to rework than macros. Besides,
there is no gain here in inlining these.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/mips16e_translate.c.inc | 101 +---
1 file changed, 53 insertions(+), 48 deletions(-)
diff --git a/target/mips/tcg/mips16e_
On 9/30/24 10:52, Jamin Lin wrote:
The register set of GPIO have a significant change since AST2700.
Each GPIO pin has their own individual control register and users are able to
set one GPIO pin’s direction, interrupt enable, input mask and so on in the
same one control register.
AST2700 does n
Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 3 +++
target/mips/cpu.c | 9 -
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 3e906a175a..070e
Introduce mo_endian_env() which returns the endian
MemOp corresponding to the vCPU env.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 1ce2bbf62d..5fe1af22ff 100644
--
Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/mips); \
done
Signed-off-by: Philippe Mat
Replace compile-time MO_TE evaluation by runtime mo_endian_env()
one, which expand target endianness from vCPU env.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/sysemu/tlb_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/tcg/sysemu/tlb_helper.
mips_cpu_create_with_clock() creates a vCPU. Pass it the vCPU
endianness requested by argument. Update the board call sites.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h| 4 +++-
hw/mips/fuloong2e.c | 2 +-
hw/mips/jazz.c | 2 +-
hw/mips/loongson3_virt.c | 2
Get vCPU endianness from CP0::BE bit.
Propagate endianness at the board level, using QOM property.
Remove target-specific endianness knowledge from target/.
Philippe Mathieu-Daudé (12):
target/mips: Declare cpu_is_bigendian_env() in 'internal.h'
target/mips: Introduce mo_endian_env() helper
Introduce mo_endian() which returns the endian MemOp
corresponding to the vCPU DisasContext.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 2b6646b339..
Have the CPS expose a 'cpu-big-endian' property so it can
set it to the vCPUs it creates.
Note, since the number of vCPUs created is dynamic, we can
not use QOM aliases.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/cps.h | 1 +
hw/mips/cps.c | 4
hw/mips/malta.c |
LGTM
Thanks
cmd
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> VT-d spec removed Transient Mapping (TM) field from second-level page-tables
> and treat the field as Reserved(0) since revis
On 9/30/24 10:52, Jamin Lin wrote:
Add GPIO model for AST2700 GPIO support. The GPIO controller registers base
address is start at 0x14C0_B000 and its address space is 0x1000.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/aspeed_ast27x0.c | 13 +
On 9/10/24 14:35, Manos Pitsidianakis wrote:
+unsafe impl GlobalAlloc for QemuAllocator {
+unsafe fn alloc(&self, layout: Layout) -> *mut u8 {
+if matches!(Self::DEFAULT_ALIGNMENT_BYTES, Some(default) if
default.checked_rem(layout.align()) == Some(0))
+{
+g_malloc
[add migration maintainers]
On 24.09.24 15:56, Andrey Drobyshev wrote:
Instead of throwing an assert let's just ignore that flag is already set
and return. We assume that it's going to be safe to ignore. Otherwise
this assert fails when migrating a paused VM back and forth.
Ideally we'd like
On Monday, September 30, 2024 10:14:57 AM CEST Marc-André Lureau wrote:
> From: Marc-André Lureau
>
> ../fsdev/9p-iov-marshal.c:93:23: error: ‘val’ may be used uninitialized
> [-Werror=maybe-uninitialized]
> and similar
>
> Signed-off-by: Marc-André Lureau
> ---
> fsdev/9p-iov-marshal.c | 6 +
From: Clément Mathieu--Drif
This will be used to implement the device IOTLB invalidation
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
Acked-by: Jason Wang
---
hw/i386/intel_iommu.c | 39 ---
1 file changed, 24 insertions(+), 15 deleti
When guest configures Nested Translation(011b) or First-stage Translation only
(001b), type check passed unaccurately.
Fails the type check in those cases as their simulation isn't supported yet.
Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation")
Suggested-by: Yi Liu
Signed-off-by: Zhen
From: Yi Liu
This adds stage-1 page table walking to support stage-1 only
translation in scalable modern mode.
Signed-off-by: Yi Liu
Co-developed-by: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
Acked-by: Jason Wang
---
hw/
According to VTD spec, stage-1 page table could support 4-level and
5-level paging.
However, 5-level paging translation emulation is unsupported yet.
That means the only supported value for aw_bits is 48.
So default aw_bits to 48 in scalable modern mode. In other cases,
it is still default to 39
This is used by some emulated devices which caches address
translation result. When piotlb invalidation issued in guest,
those caches should be refreshed.
For device that does not implement ATS capability or disable
it but still caches the translation result, it is better to
implement ATS cap or e
From: Yu Zhang
Spec revision 3.0 or above defines more detailed fault reasons for
scalable mode. So introduce them into emulation code, see spec
section 7.1.2 for details.
Note spec revision has no relation with VERSION register, Guest
kernel should not use that register to judge what features a
From: Yi Liu
Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translation,
rename variable and functions from slpte to pte whenever possible.
But some are SST only, they are renamed with sl_ prefix.
Signed-off-by: Yi Liu
Co-developed-by: Clément Mathieu--Drif
Signed-off-by: Cl
Add an new element scalable_mode in IntelIOMMUState to mark scalable
modern mode, this element will be exposed as an intel_iommu property
finally.
For now, it's only a placehholder and used for address width
compatibility check and block host device passthrough until nesting
is supported.
Signed-
This gives user flexibility to turn off FS1GP for debug purpose.
It is also useful for future nesting feature. When host IOMMU doesn't
support FS1GP but vIOMMU does, nested page table on host side works
after turn FS1GP off in vIOMMU.
This property has no effect when vIOMMU isn't in scalable mode
Add the framework to test the intel-iommu device.
Currently only tested cap/ecap bits correctness in scalable
modern mode. Also tested cap/ecap bits consistency before
and after system reset.
Signed-off-by: Zhenzhong Duan
Acked-by: Thomas Huth
Reviewed-by: Clément Mathieu--Drif
Acked-by: Jason
Hi,
Per Jason Wang's suggestion, iommufd nesting series[1] is split into
"Enable stage-1 translation for emulated device" series and
"Enable stage-1 translation for passthrough device" series.
This series enables stage-1 translation support for emulated device
in intel iommu which we called "mode
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 3 +++
hw/i386/intel_iommu.c | 25 -
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu_internal
PASID-based iotlb (piotlb) is used during walking Intel
VT-d stage-1 page table.
This emulates the stage-1 page table iotlb invalidation requested
by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB).
Signed-off-by: Yi Liu
Signed-off-by: Zhenzhong Duan
Reviewed-by: Clément Mathieu--Drif
Acked
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 11
hw/i386/intel_iommu.c | 50 ++
2 files changed, 61 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.
Thomas Huth writes:
> On 23/09/2024 10.15, Alex Bennée wrote:
>> The mips64el cross setup is very broken for bullseye which has now
>> entered LTS support so is unlikely to be fixed. While we still can't
>> build the container for bookworm due to a single missing dependency
>> that will hopefully
According to spec, Page-Selective-within-Domain Invalidation (11b):
1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through
(PGTT=100b) mappings associated with the specified domain-id and the
input-address range are invalidated.
2. IOTLB entries caching first-stage (PGTT=001b)
Hi Christian
On Mon, Sep 30, 2024 at 1:27 PM Christian Schoenebeck via <
qemu-devel@nongnu.org> wrote:
> On Monday, September 30, 2024 10:14:57 AM CEST Marc-André Lureau wrote:
> > From: Marc-André Lureau
> >
> > ../fsdev/9p-iov-marshal.c:93:23: error: ‘val’ may be used uninitialized
> [-Werror=
From: Fiona Ebner
Allow overlapping request by removing the assert that made it
impossible. There are only two callers:
1. block_copy_task_create()
It already asserts the very same condition before calling
reqlist_init_req().
2. cbw_snapshot_read_lock()
There is no need to have read requests
The following changes since commit 3b14a767eaca3df5534a162851f04787b363670e:
Merge tag 'qemu-openbios-20240924' of https://github.com/mcayland/qemu into
staging (2024-09-28 12:34:44 +0100)
are available in the Git repository at:
https://gitlab.com/vsementsov/qemu.git tags/pull-block-jobs-20
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 6 +++---
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
inde
According to the datasheet of ASPEED SOCs, a GPIO controller owns 4KB of
register space for AST2700, AST2500, AST2400 and AST1030; owns 2KB of
register space for AST2600 1.8v and owns 2KB of register space for
AST2600 3.3v.
It set the memory region size 2KB by default and it does not compatible
re
The register set of GPIO have a significant change since AST2700.
Each GPIO pin has their own individual control register and users are able to
set one GPIO pin’s direction, interrupt enable, input mask and so on in the
same one control register.
AST2700 does not have GPIO18_XXX registers for GPIO
From: Fiona Ebner
In the context of backup fleecing, discarding the source will not work
when the fleecing image has a larger granularity than the one used for
block-copy operations (can happen if the backup target has smaller
cluster size), because cbw_co_pdiscard_snapshot() will align down the
From: Fiona Ebner
In the context of backup fleecing, discarding the source will not work
when the fleecing image has a larger granularity than the one used for
block-copy operations (can happen if the backup target has smaller
cluster size), because cbw_co_pdiscard_snapshot() will align down the
From: "Dr. David Alan Gilbert"
aio_task_pool_empty has been unused since it was added in
6e9b225f73 ("block: introduce aio task pool")
Remove it.
Signed-off-by: Dr. David Alan Gilbert
Message-Id: <20240917002007.330689-1-d...@treblig.org>
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
blo
From: "Dr. David Alan Gilbert"
co_try_get_from_shres hasn't been used since it was added in
55fa54a789 ("co-shared-resource: protect with a mutex")
(Everyone uses the _locked version)
Remove it.
Signed-off-by: Dr. David Alan Gilbert
Message-Id: <20240918124220.27871-1-d...@treblig.org>
Signe
On 30.09.24 11:14, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
../block/block-copy.c:591:12: error: ‘ret’ may be used uninitialized
[-Werror=maybe-uninitialized]
Signed-off-by: Marc-André Lureau
Reviewed-by: Vladimir Sementsov-Ogievskiy
--
Best regards,
Vladimir
On 30.09.24 11:14, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
../block/mirror.c:404:5: error: ‘ret’ may be used uninitialized
[-Werror=maybe-uninitialized]
../block/mirror.c:895:12: error: ‘ret’ may be used uninitialized
[-Werror=maybe-uninitialized]
../block/mirror.c:578:12: e
AST2700 integrates two set of Parallel GPIO Controller with maximum 212
control pins, which are 27 groups. (H, exclude pin: H7 H6 H5 H4)
In the previous design of ASPEED SOCs, one register is used for setting
one function for one set which are 32 pins and 4 groups.
ex: GPIO000 is used for setting
It set "aspeed_gpio_ops" struct which containing read and write callbacks
to be used when I/O is performed on the GPIO region.
Besides, in the previous design of ASPEED SOCs, one register is used for
setting one function for 32 GPIO pins.
ex: GPIO000 is used for setting data value for GPIO A, B, C
The interrupt status field is W1C, where a set bit on read indicates an
interrupt is pending. If the bit extracted from data is set it should
clear the corresponding bit in reg_value. However, if the extracted
bit is clear then the value of the corresponding bit in reg_value
should be unchanged.
S
v1: Support GPIO for AST2700
v2: Fix clear incorrect interrupt status and adds reviewer suggestions
v3: remove nested conditionals and adds reviewer suggestions
v4: add test cases to test GPIO for AST2700 and update commit messages
v5: fix aspeed_gpio-test test failed if arch is arm
v6: add to test
On 30.09.24 11:14, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
../tests/unit/test-block-iothread.c:773:17: error: ‘job’ may be used
uninitialized [-Werror=maybe-uninitialized]
/usr/include/glib-2.0/glib/gtestutils.h:73:53: error: ‘ret’ may be used
uninitialized [-Werror=maybe-un
Add GPIO model for AST2700 GPIO support. The GPIO controller registers base
address is start at 0x14C0_B000 and its address space is 0x1000.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/as
Add test case to test GPIO output and input pins from A0 to D7 for AST2700.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed_gpio-test.c | 77 --
tests/qtest/meson.build| 3 ++
2 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/tests/qtest/asp
VT-d spec removed Transient Mapping (TM) field from second-level page-tables
and treat the field as Reserved(0) since revision 3.2. Update code to match
spec.
This doesn't impact function of vIOMMU as there was no logic to emulate
Transient Mapping.
Suggested-by: Yi Liu
Signed-off-by: Zhenzhong
Nothing in fw_cfg.c requires target-specific knowledge,
build it once for the 4 MIPS variants.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mips/meson.build b/hw/mips/meson.build
index ca37c42d90..fcbee53bb3
In preparation to pass endianness and target word size to
the bootloader API, introduce an empty BlCpuCfg structure
and propagate it to the MIPS bootloader methods.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 17 +++--
hw/mips/bootloader.c | 142
Replace a pair of memcpy() + tswap32() by stl_endian_p(),
which also swap the value using target endianness.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/xtensa/xtfpga.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c
index 228f00
Introduce the ld/st_endian_pci_dma() API, which takes an extra
boolean argument to dispatch to ld/st_{be,le}_pci_dma() methods.
Signed-off-by: Philippe Mathieu-Daudé
---
TODO: Update docstring regexp
---
include/hw/pci/pci_device.h | 24 +++-
1 file changed, 23 insertions(+),
In preparation of heterogeneous machines, remove knowledge of the
target endianness in generic hw/ code. Move it to the machine level.
Philippe Mathieu-Daudé (13):
qemu/bswap: Introduce ld/st_endian_p() API
hw/virtio/virtio-access: Use the ld/st_endian_p() API
target/arm/ptw: Use the ld/st_e
Move code evaluation from preprocessor to compiler so
both if() ladders are processed. Mostly style change.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/xtensa/xtfpga.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c
index
On 30/09/2024 09.00, Philippe Mathieu-Daudé wrote:
Nothing in fw_cfg.c requires target-specific knowledge,
build it once for the 4 MIPS variants.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mips/meson.bu
On 27/09/2024 02.51, jro...@linux.ibm.com wrote:
From: Jared Rossi
Remove panic-on-error from virtio-scsi IPL specific functions so that error
recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
...
@@ -57
Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities
related to scalable mode translation, thus there are multiple combinations.
This vIOMMU implementation wants to simplify it with a new property "x-fls".
When enabled in scalable mode, first stage translation also known as
On 27/09/2024 02.51, jro...@linux.ibm.com wrote:
From: Jared Rossi
Remove panic-on-error from Netboot specific functions so that error recovery
may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
...
index bc6ad869
From: Clément Mathieu--Drif
First stage translation must fail if the address to translate is
not canonical.
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
Acked-by: Jason Wang
---
hw/i386/intel_iommu_internal.h | 2 ++
hw/i386/intel_iommu.c | 23
Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will
flush stage-2 iotlb entries with matching domain id and pasid.
With scalable modern mode introduced, guest could send PASID-selective
PASID-based iotlb invalidation to flush both stage-1 and stage-2 entries.
By this chance, rem
Add the framework to test the intel-iommu device.
Currently only tested cap/ecap bits correctness in scalable
modern mode. Also tested cap/ecap bits consistency before
and after system reset.
Signed-off-by: Zhenzhong Duan
Acked-by: Thomas Huth
Reviewed-by: Clément Mathieu--Drif
Acked-by: Jason
Sorry, forgot to update to new parameter "x-scalable-mode=on,x-fls=on", will
resend this patch only.
Thanks
Zhenzhong
>-Original Message-
>From: Duan, Zhenzhong
>Subject: [PATCH v4 17/17] tests/qtest: Add intel-iommu test
>
>Add the framework to test the intel-iommu device.
>
>Currently
From: Marc-André Lureau
../hw/block/virtio-blk.c:1212:12: error: ‘rq’ may be used uninitialized
[-Werror=maybe-uninitialized]
Signed-off-by: Marc-André Lureau
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Stefano Garzarella
---
hw/block/virtio-blk.c | 2 +-
1 file changed, 1 insertion(+), 1 del
From: Marc-André Lureau
../linux-user/hppa/cpu_loop.c: In function ‘hppa_lws’:
../linux-user/hppa/cpu_loop.c:106:17: error: ‘ret’ may be used uninitialized
[-Werror=maybe-uninitialized]
106 | env->gr[28] = ret;
Signed-off-by: Marc-André Lureau
---
linux-user/hppa/cpu_loop.c | 10 +--
From: Marc-André Lureau
../tests/unit/test-block-iothread.c:773:17: error: ‘job’ may be used
uninitialized [-Werror=maybe-uninitialized]
/usr/include/glib-2.0/glib/gtestutils.h:73:53: error: ‘ret’ may be used
uninitialized [-Werror=maybe-uninitialized]
Signed-off-by: Marc-André Lureau
---
te
From: Marc-André Lureau
../hw/sd/sdhci.c:846:16: error: ‘res’ may be used uninitialized
[-Werror=maybe-uninitialized]
False-positive, because "length" is non-null.
Signed-off-by: Marc-André Lureau
---
hw/sd/sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/sd/sdh
From: Marc-André Lureau
../nbd/client-connection.c:419:8: error: ‘wait_co’ may be used uninitialized
[-Werror=maybe-uninitialized]
Signed-off-by: Marc-André Lureau
Reviewed-by: Eric Blake
---
nbd/client-connection.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/nbd/clie
From: Marc-André Lureau
../util/qemu-timer.c:198:24: error: ‘expire_time’ may be used uninitialized
[-Werror=maybe-uninitialized]
../util/qemu-timer.c:476:8: error: ‘rearm’ may be used uninitialized
[-Werror=maybe-uninitialized]
Signed-off-by: Marc-André Lureau
Reviewed-by: Manos Pitsidianaki
From: Marc-André Lureau
../fsdev/9p-iov-marshal.c:93:23: error: ‘val’ may be used uninitialized
[-Werror=maybe-uninitialized]
and similar
Signed-off-by: Marc-André Lureau
---
fsdev/9p-iov-marshal.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/fsdev/9p-iov-marshal.
On Mon, Sep 30, 2024 at 12:14:53PM GMT, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
../hw/virtio/vhost-shadow-virtqueue.c:545:13: error: ‘r’ may be used
uninitialized [-Werror=maybe-uninitialized]
Set `r` to 0 at every loop, since we don't check vhost_svq_get_buf()
return value
On Mon, Sep 30, 2024 at 10:11 AM Stefano Garzarella wrote:
>
> On Fri, Sep 27, 2024 at 3:08 PM Eugenio Perez Martin
> wrote:
> >
> > On Wed, Sep 25, 2024 at 10:08 AM Stefano Garzarella
> > wrote:
> > >
> > > On Tue, Sep 24, 2024 at 05:05:49PM GMT, marcandre.lur...@redhat.com wrote:
> > > >From:
On 27/09/2024 23.32, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/loongarch/virt.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index c373e48f27..9ba47793ef 100644
--- a/include/hw/loongarch/
On 27/09/2024 23.32, Philippe Mathieu-Daudé wrote:
Nothing in LoongArch fw_cfg.c requires target specific definitions.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/loongarch/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/loongarch/meson.build b/hw/loongarc
Refactor to use the recently introduced ld/st_endian_pci_dma()
API. No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/tulip.c | 32 ++--
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/hw/net/tulip.c b/hw/net/tulip.c
index 9d
Introduce the ld/st_endian_p() API, which takes an extra
boolean argument to dispatch to ld/st_{be,le}_p() methods.
Signed-off-by: Philippe Mathieu-Daudé
---
TODO: Update docstring regexp
---
include/qemu/bswap.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/qe
Refactor to use the recently introduced ld/st_endian_p() API
No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/ptw.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index defd6b84de..a1a6b
Introduce the ld/st_endian_phys() API, which takes an extra
boolean argument to dispatch to ld/st_{be,le}_phys() methods.
Signed-off-by: Philippe Mathieu-Daudé
---
TODO: Update docstring regexp
---
include/exec/memory_ldst_phys.h.inc | 66 +
1 file changed, 66 inserti
Refactor to use the recently introduced ld/st_endian_p() API
No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/virtio/virtio-access.h | 36 ++-
1 file changed, 6 insertions(+), 30 deletions(-)
diff --git a/include/hw/virtio/virtio-acces
Refactor to use the recently introduced ld/st_endian_p() API
No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/tcg/plugins/mem.c | 24 ++--
1 file changed, 6 insertions(+), 18 deletions(-)
diff --git a/tests/tcg/plugins/mem.c b/tests/tcg/plugins/mem
Add the BlCpuCfg::cpu_is_bigendian field, initialize it in
machine code. Bootloader API use the ld/st_endian_p() to
dispatch to target endianness.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 1 +
hw/mips/bootloader.c | 10 +-
hw/mips/boston.c
Refactor to use the recently introduced ld/st_endian_phys() API.
No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/virtio/virtio-access.h | 27 +--
1 file changed, 5 insertions(+), 22 deletions(-)
diff --git a/include/hw/virtio/virtio-acces
Define both endianness variants with a single macro.
Useful to add yet other endian specific definitions
in the next commit.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci/pci_device.h | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/include/hw/pci/pci_
On Fri, Sep 27, 2024 at 3:05 PM Eugenio Perez Martin
wrote:
>
> On Tue, Sep 24, 2024 at 3:07 PM wrote:
> >
> > From: Marc-André Lureau
> >
> > ../hw/virtio/vhost-shadow-virtqueue.c:545:13: error: ‘r’ may be used
> > uninitialized [-Werror=maybe-uninitialized]
> >
> > Signed-off-by: Marc-André L
On Fri, Sep 27, 2024 at 3:08 PM Eugenio Perez Martin
wrote:
>
> On Wed, Sep 25, 2024 at 10:08 AM Stefano Garzarella
> wrote:
> >
> > On Tue, Sep 24, 2024 at 05:05:49PM GMT, marcandre.lur...@redhat.com wrote:
> > >From: Marc-André Lureau
> >
> > For the title: I don't think it is a false positiv
From: Marc-André Lureau
../hw/display/qxl.c:1352:5: error: ‘pci_region’ may be used uninitialized
[-Werror=maybe-uninitialized]
../hw/display/qxl.c:1365:22: error: ‘pci_start’ may be used uninitialized
[-Werror=maybe-uninitialized]
Signed-off-by: Marc-André Lureau
Reviewed-by: Manos Pitsidian
On 27/09/2024 02.51, jro...@linux.ibm.com wrote:
From: Jared Rossi
Remove panic-on-error from DASD IPL specific functions so that error recovery
may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
Reviewed-by: Thomas Hut
From: Marc-André Lureau
../util/qemu-coroutine.c:150:8: error: ‘batch’ may be used uninitialized
[-Werror=maybe-uninitialized]
Signed-off-by: Marc-André Lureau
Reviewed-by: Stefan Hajnoczi
---
util/qemu-coroutine.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/qemu
From: Marc-André Lureau
Hi,
Depending on -Doptimization=, GCC (14.2.1 here) produces different
maybe-uninitialized warnings:
- g: produces -Werror=maybe-uninitialized errors
- 0: clean build
- 1: produces -Werror=maybe-uninitialized errors
- 2: clean build
- 3: produces few -Werror=maybe-uniniti
From: Marc-André Lureau
../migration/dirtyrate.c:186:5: error: ‘records’ may be used uninitialized
[-Werror=maybe-uninitialized]
../migration/dirtyrate.c:168:12: error: ‘gen_id’ may be used uninitialized
[-Werror=maybe-uninitialized]
../migration/migration.c:2273:5: error: ‘file’ may be used un
From: Marc-André Lureau
../migration/ram.c:1873:23: error: ‘dirty’ may be used uninitialized
[-Werror=maybe-uninitialized]
When 'block' != NULL, 'dirty' is initialized.
Signed-off-by: Marc-André Lureau
Acked-by: Peter Xu
---
migration/ram.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
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