>-Original Message-
>From: Jason Wang
>Subject: Re: [PATCH v3 16/17] intel_iommu: Introduce a property to control
>FS1GP cap bit setting
>
>On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan
> wrote:
>>
>> This gives user flexibility to turn off FS1GP for debug purpose.
>>
>> It is also usef
Thomas Huth writes:
> According to https://marc.info/?l=fedora-devel-list&m=171934833215726
> the GlusterFS development effectively ended. Thus mark it as deprecated
> in QEMU, so we can remove it in a future release if the project does
> not gain momentum again.
>
> Acked-by: Niels de Vos
> Sig
In order to correctly print executable name in various
error messages, pass argv[0] to error_exit() function.
This way, error messages will refer to actual executable
name, which may be different from 'qemu-img'.
For subcommands, pass original command name from the
qemu-img argv[0], plus the subco
From: Ard Biesheuvel
target_ulong is typedef'ed as a 32-bit integer when building the
qemu-system-arm target, and this is smaller than the size of an
intermediate physical address when LPAE is being used.
Given that Linux may place leaf level user page tables in high memory
when built for LPAE,
>-Original Message-
>From: Jason Wang
>Subject: Re: [PATCH v3 12/17] intel_iommu: Add support for PASID-based
>device IOTLB invalidation
>
>On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan
> wrote:
>>
>> From: Clément Mathieu--Drif
>>
>> Signed-off-by: Clément Mathieu--Drif
>> Signed-off
From: Ard Biesheuvel
The PVH entrypoint is entered in 32-bit mode, and is documented as being
a 32-bit field. Linux happens to widen the field in the ELF note to 64
bits so treating it as a 64-bit field works for booting the kernel.
However, Xen documents the ELF note with the following example
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 6 +++---
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
inde
The interrupt status field is W1C, where a set bit on read indicates an
interrupt is pending. If the bit extracted from data is set it should
clear the corresponding bit in reg_value. However, if the extracted
bit is clear then the value of the corresponding bit in reg_value
should be unchanged.
S
AST2700 integrates two set of Parallel GPIO Controller with maximum 212
control pins, which are 27 groups. (H, exclude pin: H7 H6 H5 H4)
In the previous design of ASPEED SOCs, one register is used for setting
one function for one set which are 32 pins and 4 groups.
ex: GPIO000 is used for setting
Add test case to test GPIO output and input pins from A0 to D7 for AST2700.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed_gpio-test.c | 64 ++
1 file changed, 64 insertions(+)
diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c
index d3
Daniel P. Berrangé writes:
> On Thu, Sep 26, 2024 at 03:23:11PM +0100, Alex Bennée wrote:
[...]
>> One issue that came up is how we handle adequately reviewing code when
>> most of the maintainers are experienced C coders but might not know much
>> about Rust. While we want to avoid the situati
It set "aspeed_gpio_ops" struct which containing read and write callbacks
to be used when I/O is performed on the GPIO region.
Besides, in the previous design of ASPEED SOCs, one register is used for
setting one function for 32 GPIO pins.
ex: GPIO000 is used for setting data value for GPIO A, B, C
v1: Support GPIO for AST2700
v2: Fix clear incorrect interrupt status and adds reviewer suggestions
v3: remove nested conditionals and adds reviewer suggestions
v4: add test cases to test GPIO for AST2700 and update commit messages
Jamin Lin (7):
hw/gpio/aspeed: Fix coding style
hw/gpio/aspeed
This is necessary to provide discernible error messages to the caller.
Signed-off-by: Julia Suvorova
Reviewed-by: Peter Xu
---
accel/kvm/kvm-all.c| 41 +-
include/sysemu/kvm.h | 4 ++--
target/arm/kvm.c | 4 ++--
target/i386/kvm/kvm.
On 9/27/24 08:29, Jamin Lin wrote:
Also, your emails have an invalid "From" field set to
"qemu-devel@nongnu.org" when retrieved with the b4 command.
I have been fixing them for a while. Could you please tell us how you send the
patchsets ?
hmm, curious. I wonder what's happening.
Thanks,
C.
On Fri, 27 Sept 2024 at 09:52, Chao Liu wrote:
>
> Hi, thank you for your prompt reply, it's a great encouragement to me!
>
> Based on your review suggestions, I have improved the v1 patch.
>
> By using create_unimplemented_device() during the initialization phase,
> I added a "znyq.umip" device e
From: Shiju Jose
CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
control feature.
ECS log capabilities field in following ECS tables, which is common for all
memory media FRUs in a CXL device.
Fix struct CXLMemECSReadAttrs and struct CXLMemECSWriteAttrs to make
log
On 9/21/2024 1:56 AM, Alejandro Jimenez wrote:
> Hi Santosh,
>
> On 9/16/24 10:31, Santosh Shukla wrote:
>> From: Suravee Suthikulpanit
>>
>> Introduce 'nodma' shared memory region to support PT mode
>> so that for each device, we only create an alias to shared memory
>> region when DMA-remapp
On Fri, Sep 27, 2024 at 06:29:22AM GMT, Jamin Lin wrote:
> > Also, your emails have an invalid "From" field set to
> > "qemu-devel@nongnu.org" when retrieved with the b4 command.
This is almost certainly done by the mailman list running on nongnu.org. It's
a very patch-hostile setting, so I'm surp
On Fri, 27 Sept 2024 at 15:03, Chao Liu wrote:
> On 2024/9/27 20:18, Peter Maydell wrote:
>> On Fri, 27 Sept 2024 at 09:52, Chao Liu wrote:
>> Even if our test set is not sufficiently comprehensive, we can create an
>> unimp_device for the maximum address space allowed by the board. This
>> prev
On Sat, 21 Sept 2024 at 11:48, Inès Varhol wrote:
>
> It has been a learning experience to contribute to QEMU for our
> end-of-studies project. For a few months now, Arnaud and I aren't
> actively involved anymore as we lack time and access to the hardware.
> Therefore it's high time to update the
在 2024/9/27 23:35, Peter Xu 写道:
On Fri, Sep 27, 2024 at 10:50:01AM +0800, Yong Huang wrote:
On Fri, Sep 27, 2024 at 3:55 AM Peter Xu wrote:
On Fri, Sep 27, 2024 at 02:13:47AM +0800, Yong Huang wrote:
On Thu, Sep 26, 2024 at 3:17 AM Peter Xu wrote:
On Fri, Sep 20, 2024 at 10:43:31AM +080
On 9/27/24 11:02 AM, Thomas Huth wrote:
On 27/09/2024 02.51, jro...@linux.ibm.com wrote:
From: Jared Rossi
Remove panic-on-error from IPL ISO El Torito specific functions so
that error
recovery may be possible in the future.
Functions that would previously panic now provide a return code
ldn/stn methods handle the access size, no need for the switch case.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/spapr_nvdimm.c | 47 ---
1 file changed, 4 insertions(+), 43 deletions(-)
diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c
inde
Directly call ldn_be_p once instead of ldl_be_p / ldq_be_p.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/spapr_vof.c | 27 +--
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/hw/ppc/spapr_vof.c b/hw/ppc/spapr_vof.c
index c02eaacfed..d238a44d88 100644
--
Directly call ldn_be_p once instead of be32_to_cpu / ldq_be_p.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/vof.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/hw/ppc/vof.c b/hw/ppc/vof.c
index b5b6514d79..fb152efbe0 100644
--- a/hw/ppc/vof.c
+++ b/hw/ppc/vof.c
@@
Use ldN / stN methods to access variable lengths.
Philippe Mathieu-Daudé (4):
hw/ppc/spapr_nvdimm: Simplify LD/ST API uses
hw/ppc/spapr_vof: Simplify LD/ST API uses
hw/ppc/vof: Simplify LD/ST API uses
net/l2tpv3: Simplify LD/ST API uses
hw/ppc/spapr_nvdimm.c | 47
Directly call ldn_be_p once instead of ldl_be_p / ldq_be_p.
Signed-off-by: Philippe Mathieu-Daudé
---
net/l2tpv3.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/net/l2tpv3.c b/net/l2tpv3.c
index b5547cb917..7a0d5dcfe9 100644
--- a/net/l2tpv3.c
+++ b/net/l2tpv3.c
@@ -31
Use ldN / stN methods to access variable lengths.
v2:
- Include unstaged change in vof.c
Philippe Mathieu-Daudé (4):
hw/ppc/spapr_nvdimm: Simplify LD/ST API uses
hw/ppc/spapr_vof: Simplify LD/ST API uses
hw/ppc/vof: Simplify LD/ST API uses
net/l2tpv3: Simplify LD/ST API uses
hw/ppc/spap
ldn/stn methods handle the access size, no need for the switch case.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/spapr_nvdimm.c | 47 ---
1 file changed, 4 insertions(+), 43 deletions(-)
diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c
inde
> > > I have met with the team from IONOS about their testing on actual IB
> > > hardware here at KVM Forum today and the requirements are starting
> > > to make more sense to me. I didn't say much in our previous thread
> > > because I misunderstood the requirements, so let me try to explain
> > >
Instead of be32_to_cpu (equivalent of ldl_be_p) and ldq_be_p,
use ldn_be_p(). Similarly instead of cpu_to_be32 (equiv. stl_be_p)
and cpu_to_be64 (equiv. stq_be_p), use stn_be_p().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/vof.c | 26 +-
1 file changed, 9 insertions
Directly call ldn_be_p once instead of ldl_be_p / ldq_be_p.
Signed-off-by: Philippe Mathieu-Daudé
---
net/l2tpv3.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/net/l2tpv3.c b/net/l2tpv3.c
index b5547cb917..7a0d5dcfe9 100644
--- a/net/l2tpv3.c
+++ b/net/l2tpv3.c
@@ -31
Directly call ldn_be_p once instead of ldl_be_p / ldq_be_p.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/spapr_vof.c | 27 +--
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/hw/ppc/spapr_vof.c b/hw/ppc/spapr_vof.c
index c02eaacfed..d238a44d88 100644
--
On 27.09.24 20:05, Halil Pasic wrote:
On Thu, 12 Sep 2024 10:19:00 +0200
Thomas Huth wrote:
diff --git a/hw/s390x/s390-hypercall.h b/hw/s390x/s390-hypercall.h
index b7ac29f444..f0ca62bcbb 100644
--- a/hw/s390x/s390-hypercall.h
+++ b/hw/s390x/s390-hypercall.h
@@ -18,6 +18,7 @@
#define DIAG50
On Wed, 25 Sept 2024 at 20:34, Kinsey Moore wrote:
>
> Hey,
> I just wanted to check on the status of this patch since it's been sitting
> for a bit now and I noticed it hasn't gone into any branches. Is this waiting
> on something from me?
No, I'm afraid I just hadn't noticed it to pick it up.
LoongArch fw_cfg.c doesn't use target specific declarations,
build it as common object.
Philippe Mathieu-Daudé (2):
hw/loongarch/virt: Remove unnecessary 'cpu.h' inclusion
hw/loongarch/fw_cfg: Build in common_ss[]
include/hw/loongarch/virt.h | 1 -
hw/loongarch/meson.build| 2 +-
2 files
Nothing in LoongArch fw_cfg.c requires target specific definitions.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/loongarch/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build
index bce7ebac97..005f017e21 100644
--- a
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/loongarch/virt.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index c373e48f27..9ba47793ef 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -8,7 +8,6 @
On 27/09/2024 10.12, Jamin Lin wrote:
Hi Cedric,
Subject: [PATCH v4 7/7] hw/gpio/aspeed: Add test case for AST2700
Add test case to test GPIO output and input pins from A0 to D7 for AST2700.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed_gpio-test.c | 64 ++
Hello Jamin,
On 9/27/24 10:33, Jamin Lin wrote:
The register set of GPIO have a significant change since AST2700.
Each GPIO pin has their own individual control register and users are able to
set one GPIO pin’s direction, interrupt enable, input mask and so on in the
same one control register.
On 27/09/2024 10.33, Jamin Lin wrote:
Add test case to test GPIO output and input pins from A0 to D7 for AST2700.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed_gpio-test.c | 68 ++
1 file changed, 68 insertions(+)
diff --git a/tests/qtest/aspeed_gpio-test.c
On Tue, 24 Sept 2024 at 11:03, David Hildenbrand wrote:
>
> Hi,
>
> due to reset changes this contains a bit of churn that touches various
> architectures, but it's all fairly minimal and straight-forward.
>
> The following changes since commit 01dc65a3bc262ab1bec8fe89775e9bbfa627becb:
>
> Merge
>-Original Message-
>From: Duan, Zhenzhong
>Subject: RE: [PATCH v3 12/17] intel_iommu: Add support for PASID-based
>device IOTLB invalidation
>
>
>
>>-Original Message-
>>From: Jason Wang
>>Subject: Re: [PATCH v3 12/17] intel_iommu: Add support for PASID-based
>>device IOTLB inva
To help debug and triage future failure reports (akin to [1,2]) that
may occur during kvm_arch_put/get_registers, the error path of each
action is accompanied by unique error message.
[1] https://issues.redhat.com/browse/RHEL-7558
[2] https://issues.redhat.com/browse/RHEL-21761
Signed-off-by: Jul
There were a few bugs with silent cpu failures during migrations [1].
The failures are no longer silent thanks to [2], but still
indistinguishable, making diagnostics difficult.
This patchset reworks kvm_arch_get/put_registers to handle Error** and
return a correct message, with x86_64 as a start.
On 2024/9/27 20:18, Peter Maydell wrote:
On Fri, 27 Sept 2024 at 09:52, Chao Liu wrote:
Hi, thank you for your prompt reply, it's a great encouragement to me!
Based on your review suggestions, I have improved the v1 patch.
By using create_unimplemented_device() during the initialization phase
On 9/27/24 11:29 AM, Thomas Huth wrote:
On 27/09/2024 02.51, jro...@linux.ibm.com wrote:
From: Jared Rossi
Remove panic-on-error from ECKD block device IPL specific functions
so that
error recovery may be possible in the future.
Functions that would previously panic now provide a return
From: Suravee Suthikulpanit
In order to support AMD IOMMU interrupt remapping emulation with PCI
pass-through devices, QEMU needs to notify VFIO when guest IOMMU driver
updates and invalidate the guest interrupt remapping table (IRT), and
communicate information so that the host IOMMU driver can
Series adds following feature support for emulated amd vIOMMU
1) Pass Through(PT) mode
2) Interrupt Remapping(IR) mode
1) PT mode
Introducing the shared 'nodma' memory region that can be aliased
by all the devices in the PT mode. Shared memory with aliasing
approach will help run VM faster when lo
Am 23. September 2024 10:28:35 UTC schrieb BALATON Zoltan :
>On Mon, 23 Sep 2024, Bernhard Beschow wrote:
>> Rather than accessing the attributes of TYPE_CCSR directly, use the
>> SysBusDevice
>> API which exists exactly for that purpose. Furthermore, registering the
>> memory
>> region with t
On 27.09.24 20:20, Halil Pasic wrote:
On Wed, 11 Sep 2024 21:09:27 +0200
David Hildenbrand wrote:
Anyway, if we want to proceed with the gitlab project, would it make
sense to create an org for it, so that it doesn't look like David's
personal project?
Frankly, I would prefer making Document
From: Miguel Luis
List changed files for FACP and DSDT table changes for the arm/virt.
Signed-off-by: Miguel Luis
---
tests/qtest/bios-tables-test-allowed-diff.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-tes
Signed-off-by: Annie Li
---
tests/qtest/bios-tables-test-allowed-diff.h | 41 +
1 file changed, 41 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..512d40665d 100644
--- a/tests/qtest/bios-
The ACPI sleep button can be implemented as a fixed hardware button
or Control Method Sleep button.
The patch of implementing a fixed hardware sleep button was posted
here 1). More discussions can be found here 2). Essentially, the
discussion mainly focuses on whether the sleep button is implement
From: Miguel Luis
[000h 4]Signature : "FACP"[Fixed ACPI
Description Table (FADT)]
[004h 0004 4] Table Length : 0114
[008h 0008 1] Revision : 06
-[009h 0009 1] Checksum : 12
+[009h 0009 1]
The GPE event is triggered to notify the guest to suppend or
wakeup itself.
Signed-off-by: Annie Li
---
hw/acpi/core.c | 17 +
hw/core/machine-qmp-cmds.c | 2 ++
include/hw/acpi/acpi.h | 1 +
include/hw/acpi/acpi_dev_interface.h |
From: Miguel Luis
Add support for ACPI GED sleep event on the ACPI device interface so that
HW-reduced systems can enable guests to sleep.
Signed-off-by: Miguel Luis
---
hw/acpi/generic_event_device.c | 9 +
include/hw/acpi/generic_event_device.h | 1 +
2 files changed, 10 inse
Adding Control Method Sleep button and its GPE event handler for
x86.
Signed-off-by: Annie Li
---
hw/i386/acpi-build.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 5d4bd2b710..ee62333a03 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/
On Fri, Sep 27, 2024 at 6:10 PM Kevin Wolf wrote:
> Am 01.07.2024 um 16:58 hat Paolo Bonzini geschrieben:
> > The qemu::util::foreign module provides:
> >
> > - A trait for structs that can be converted to a C ("foreign")
> > representation
> > (CloneToForeign)
> >
> > - A trait for structs tha
On Mon, 1 Jul 2024 at 11:02, Paolo Bonzini wrote:
> +/// A type for which there is a canonical representation as a C datum.
> +pub trait CloneToForeign {
> +/// The representation of `Self` as a C datum. Typically a
> +/// `struct`, though there are exceptions for example `c_char`
> +
On 18.09.24 15:42, d...@treblig.org wrote:
From: "Dr. David Alan Gilbert"
co_try_get_from_shres hasn't been used since it was added in
55fa54a789 ("co-shared-resource: protect with a mutex")
(Everyone uses the _locked version)
Remove it.
Signed-off-by: Dr. David Alan Gilbert
Thanks, appli
On 17.09.24 03:20, d...@treblig.org wrote:
From: "Dr. David Alan Gilbert"
aio_task_pool_empty has been unused since it was added in
6e9b225f73 ("block: introduce aio task pool")
Remove it.
Signed-off-by: Dr. David Alan Gilbert
Thanks, applied to my block branch.
--
Best regards,
Vladimir
From: Suravee Suthikulpanit
Rename the MMIO memory region variable 'mmio' to 'mr_mmio'
so to correctly name align with struct AMDVIState::variable type.
No functional change intended.
Reviewed-by: Alejandro Jimenez
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Santosh Shukla
---
hw/i3
From: Suravee Suthikulpanit
Use shared memory region for interrupt remapping which can be
aliased by all devices.
Reviewed-by: Alejandro Jimenez
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Santosh Shukla
---
hw/i386/amd_iommu.c | 22 ++
hw/i386/amd_iommu.h | 1 +
From: Suravee Suthikulpanit
The XTSup mode enables x2APIC support for AMD IOMMU, which is needed
to support vcpu w/ APIC ID > 255.
Reviewed-by: Alejandro Jimenez
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Santosh Shukla
---
v3:
- Fixed the typos: s/xt/xtsup at error_report()
hw/i38
On Wed, 11 Sep 2024 21:09:27 +0200
David Hildenbrand wrote:
> > Anyway, if we want to proceed with the gitlab project, would it make
> > sense to create an org for it, so that it doesn't look like David's
> > personal project?
Frankly, I would prefer making Documentation/virt/kvm/s390/s390-diag.
On Thu, 12 Sep 2024 10:19:00 +0200
Thomas Huth wrote:
> > diff --git a/hw/s390x/s390-hypercall.h b/hw/s390x/s390-hypercall.h
> > index b7ac29f444..f0ca62bcbb 100644
> > --- a/hw/s390x/s390-hypercall.h
> > +++ b/hw/s390x/s390-hypercall.h
> > @@ -18,6 +18,7 @@
> > #define DIAG500_VIRTIO_RESET
From: Suravee Suthikulpanit
Introduce 'nodma' shared memory region to support PT mode
so that for each device, we only create an alias to shared memory
region when DMA-remapping is disabled.
Reviewed-by: Alejandro Jimenez
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Santosh Shukla
---
The control method sleep button is added, as well as its GPE event
handler.
Co-developed-by: Miguel Luis
Signed-off-by: Annie Li
---
hw/acpi/control_method_device.c | 54 +
hw/acpi/meson.build | 1 +
include/hw/acpi/control_method_device.h |
Below is the sample iASL difference,
* Signature"DSDT"
- * Length 0x20A3 (8355)
+ * Length 0x2159 (8537)
* Revision 0x01 32-bit table (V1), no 64-bit math support
- * Checksum 0x37
+ * Checksum 0x40
*
From: Miguel Luis
For reference: qmp_system_sleep relies on wakeup support delegated
by qemu_wakeup_suspend_enabled() hence the need for calling
qemu_register_wakeup_support(). With this, we should be able to
issue QMP system_sleep command now.
Signed-off-by: Miguel Luis
---
hw/arm/virt.c | 1
Followng hmp/qmp commands are implemented for pressing virtual
sleep button,
hmp: system_sleep
qmp: { "execute": "system_sleep" }
These commands put the guest into suspend or other power states
depending on the power settings inside the guest.
Signed-off-by: Annie Li
---
hmp-commands.hx
From: Miguel Luis
Include the ACPI control method device into arm/virt ACPI tables and the
corresponding handling which enables triggering the event.
Signed-off-by: Miguel Luis
---
hw/arm/virt-acpi-build.c | 13 +
hw/arm/virt.c| 13 -
include/hw/arm/virt.h
On Fri, Sep 27, 2024 at 9:36 PM Stefan Hajnoczi wrote:
>
> On Mon, 1 Jul 2024 at 11:02, Paolo Bonzini wrote:
> > +/// A type for which there is a canonical representation as a C datum.
> > +pub trait CloneToForeign {
> > +/// The representation of `Self` as a C datum. Typically a
> > +//
Hi Gonglei,
On 9/22/24 20:04, Gonglei (Arei) wrote:
!---|
This Message Is From an External Sender
This message came from outside your organization.
|---!
Hi,
-
According to the datasheet of ASPEED SOCs, a GPIO controller owns 4KB of
register space for AST2700, AST2500, AST2400 and AST1030; owns 2KB of
register space for AST2600 1.8v and owns 2KB of register space for
AST2600 3.3v.
It set the memory region size 2KB by default and it does not compatible
re
On Tue, Sep 24, 2024 at 3:07 PM wrote:
>
> From: Marc-André Lureau
>
> ../hw/virtio/vhost-shadow-virtqueue.c:545:13: error: ‘r’ may be used
> uninitialized [-Werror=maybe-uninitialized]
>
> Signed-off-by: Marc-André Lureau
> ---
> hw/virtio/vhost-shadow-virtqueue.c | 2 +-
> 1 file changed, 1
On 9/27/24 09:19, Ard Biesheuvel wrote:
-
-pvh_start_addr = *(uint32_t *)elf_note_data_addr;
}
+pvh_start_addr = *(uint32_t *)elf_note_data_addr;
I think we even want ldl_le_p(elf_note_data_addr) here? It makes no
sense to read big-endian data.
Paolo
On Wed, Sep 25, 2024 at 10:08 AM Stefano Garzarella wrote:
>
> On Tue, Sep 24, 2024 at 05:05:49PM GMT, marcandre.lur...@redhat.com wrote:
> >From: Marc-André Lureau
>
> For the title: I don't think it is a false positive, but a real fix,
> indeed maybe not a complete one.
>
> >
> >../hw/virtio/vh
Hi Paolo,
as you asked me at KVM Forum to have a look at this, I'm going through
it now.
Am 01.07.2024 um 16:58 hat Paolo Bonzini geschrieben:
> The qemu::util::foreign module provides:
>
> - A trait for structs that can be converted to a C ("foreign") representation
> (CloneToForeign)
>
> -
The register set of GPIO have a significant change since AST2700.
Each GPIO pin has their own individual control register and users are able to
set one GPIO pin’s direction, interrupt enable, input mask and so on in the
same one control register.
AST2700 does not have GPIO18_XXX registers for GPIO
Hi Cedric,
> Subject: [PATCH v4 7/7] hw/gpio/aspeed: Add test case for AST2700
>
> Add test case to test GPIO output and input pins from A0 to D7 for AST2700.
>
> Signed-off-by: Jamin Lin
> ---
> tests/qtest/aspeed_gpio-test.c | 64 ++
> 1 file changed, 64 inser
Add test case to test GPIO output and input pins from A0 to D7 for AST2700.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed_gpio-test.c | 68 ++
1 file changed, 68 insertions(+)
diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c
index d3
AST2700 integrates two set of Parallel GPIO Controller with maximum 212
control pins, which are 27 groups. (H, exclude pin: H7 H6 H5 H4)
In the previous design of ASPEED SOCs, one register is used for setting
one function for one set which are 32 pins and 4 groups.
ex: GPIO000 is used for setting
v1: Support GPIO for AST2700
v2: Fix clear incorrect interrupt status and adds reviewer suggestions
v3: remove nested conditionals and adds reviewer suggestions
v4: add test cases to test GPIO for AST2700 and update commit messages
v5: fix aspeed_gpio-test test failed if arch is arm
Jamin Lin (7):
The register set of GPIO have a significant change since AST2700.
Each GPIO pin has their own individual control register and users are able to
set one GPIO pin’s direction, interrupt enable, input mask and so on in the
same one control register.
AST2700 does not have GPIO18_XXX registers for GPIO
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 6 +++---
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
inde
Add PMU, CAN, GPIO, I2C, and other as unimplemented devices.
Remove a ignore_memory_transaction_failures concurrently.
This allows operating systems such as Linux to run emulations such as
xilinx_zynq-7000
Signed-off-by: Chao Liu
---
hw/arm/xilinx_zynq.c | 46 +
Signed-off-by: Chao Liu
---
hw/dma/xlnx-zynq-devcfg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
index b8544d0731..7170353a62 100644
--- a/hw/dma/xlnx-zynq-devcfg.c
+++ b/hw/dma/xlnx-zynq-devcfg.c
@@ -372,7 +372,7 @@ s
Hi, thank you for your prompt reply, it's a great encouragement to me!
Based on your review suggestions, I have improved the v1 patch.
By using create_unimplemented_device() during the initialization phase,
I added a "znyq.umip" device early on, which covers the 32-bit address space
of GPA. This
On Fri, 27 Sept 2024 at 14:05, Paolo Bonzini wrote:
>
> On 9/27/24 09:19, Ard Biesheuvel wrote:
> > -
> > -pvh_start_addr = *(uint32_t *)elf_note_data_addr;
> > }
> >
> > +pvh_start_addr = *(uint32_t *)elf_note_data_addr;
>
> I think we even want ldl_le_p(elf_note_data_addr) here
This patch series introduces support for the MIPS64r6 target in QEMU,
bringing the latest architecture features and improvements to the MIPS
target. In addition to the new target, this series also includes
several bug fixes that have been in use internally for years within
the MIPS ecosystem.
The
This patch reverts the commit (with SHA
50290c002c045280f8defad911901e16bfb52884 from
https://github.com/MIPS/gnutools-qemu) that breaks for mingw builds,
where clock_gettime and CLOCK_MONOTONIC are not available.
Cherry-picked d57c735e1af1ca719dbd0c3a904ad70c9c31cbb7
from https://github.com/MIPS/
Skip NaN mode check for soft-float.
Cherry-picked 63492a56485f6b755fccf7ad623f7a189bfc79b6
from https://github.com/MIPS/gnutools-qemu
Signed-off-by: Faraz Shahbazker
Signed-off-by: Aleksandar Rakic
---
linux-user/mips/cpu_loop.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff
On 26-09-2024 09:41 pm, Gustavo Romero wrote:
Hi Cornelia and Ganapatrao,
On 9/25/24 14:54, Cornelia Huck wrote:
On Fri, Sep 20 2024, Ganapatrao Kulkarni
wrote:
Mostly nit-picking below, otherwise LGTM.
Extend the 'mte' property for the virt machine to cover KVM as
well. For KVM, we don
Applications sometimes only write the lower 32-bit payload bytes, this is used
in ACT tests. As a workaround, this refers to the solution of sail-riscv.
if the payload is written a few times with the same value, we process the whole
htif command anyway.
Signed-off-by: MingZhu Yan
---
hw/char/ris
The archive-source.sh script depends on realpath command, which was
introduced in coreutils-8.15. CentOS-6 build systems use coreutils-4.7,
which does not have realpath, so fix the script to use 'readlink -e' to
perform the same action.
Cherry-picked 5d1d5766f0219ce2bec4e41c2467317df920ec0a
and 80
Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions.
Reuse zlib crc32() and Linux crc32c().
Cherry-picked 4cc974938aee1588f852590509004e340c072940
from https://github.com/MIPS/gnutools-qemu
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Aleksandar R
Add micromips to P5600.
Cherry-picked d7bf2c2f7f2e03b55c6e9c57eec5c3e6207005a0
from https://github.com/MIPS/gnutools-qemu
Signed-off-by: Faraz Shahbazker
Signed-off-by: Matthew Fortune
Signed-off-by: Aleksandar Rakic
---
target/mips/cpu-defs.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 del
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