The ordering in ACPI specification [1] has bus number in the lowest byte.
As ACPI tables are little endian this is the reverse of the ordering
used by PCI_BUILD_BDF(). As a minimal fix split the QEMU BDF up
into bus and devfn and write them as single bytes in the correct
order.
[1] ACPI Spec 6.3,
Before making additional modification, tidy up this misleading indentation.
Reviewed-by: Ankit Agrawal
Reviewed-by: Igor Mammedov
Tested-by: "Huang, Ying"
Signed-off-by: Jonathan Cameron
---
hw/acpi/acpi_generic_initiator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/h
Rather than attempting to create a generic function with mess of the two
different device handle types, use a PCI handle specific variant. If the
ACPI handle form is needed then that can be introduced alongside this
with little duplicated code.
Drop the PCIDeviceHandle in favor of just passing th
Igor noted that this function only builds one instance, so was rather
misleadingly named. Fix that.
Suggested-by: Igor Mammedov
Reviewed-by: Igor Mammedov
Tested-by: "Huang, Ying"
Signed-off-by: Jonathan Cameron
---
hw/acpi/acpi_generic_initiator.c | 4 ++--
1 file changed, 2 insertions(+), 2
Using a property allows us to hide the internal details of the PCI device
from the code to build a SRAT Generic Initiator Affinity Structure with
PCI Device Handle.
Suggested-by: Igor Mammedov
Reviewed-by: Igor Mammedov
Signed-off-by: Jonathan Cameron
---
hw/acpi/acpi_generic_initiator.c | 14
Whilst ACPI SRAT Generic Initiator Afinity Structures are able to refer to
both PCI and ACPI Device Handles, the QEMU implementation only implements
the PCI Device Handle case. For now move the code into the existing
hw/acpi/pci.c file and header. If support for ACPI Device Handles is
added in th
Enable ACPI table creation for PCI Expander Bridges to be independent
of PCI internals. Note that the UID is currently the PCI bus number.
This is motivated by the forthcoming ACPI Generic Port SRAT entries
which can be made completely independent of PCI internals.
Suggested-by: Igor Mammedov
Te
Rather than relying on PCI internals, use the new acpi_property
to obtain the ACPI _UID values. These are still the same
as the PCI Bus numbers so no functional change.
Suggested-by: Igor Mammedov
Tested-by: "Huang, Ying"
Reviewed-by: Igor Mammedov
Signed-off-by: Jonathan Cameron
---
hw/i386
Reduce the direct use of PCI internals inside ACPI table creation.
Suggested-by: Igor Mammedov
Tested-by: "Huang, Ying"
Reviewed-by: Igor Mammedov
Signed-off-by: Jonathan Cameron
---
hw/pci-host/gpex-acpi.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/pci-host/gp
On Thu, Sep 12, 2024 at 04:53:31PM +0200, Albert Esteve wrote:
> Add SHMEM_MAP/UNMAP requests to vhost-user to
> handle VIRTIO Shared Memory mappings.
>
> This request allows backends to dynamically map
> fds into a VIRTIO Shared Memory Region indentified
> by its `shmid`. Then, the fd memory is a
On Thu, Sep 12, 2024 at 04:53:32PM +0200, Albert Esteve wrote:
> Update shmem_list to be able to track
> active mappings on VIRTIO shared memory
> regions. This allows to verify that new
> mapping request received from backends
> do not overlap. If they do, the request
> shall fail in order to adhe
Changes since RFC:
- rebase
Question:
- I could enable this for all PCIe device (including ports).
Does that makes sense, or is it better to limit this to my cases?
It is quite easy to build broken setups (downstream device reports
faster link than the port etc) because QEMU 'link' training'
Approach copied from gen_pcie_root_port.c
Previously the link defaulted to a maximum of 2.5GT/s and 1x. Enable setting
it's maximum values. The actual value after 'training' will depend on the
downstream device configuration.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c |
Copied from gen_pcie_root_port.c
Drop the previous code that ensured a valid value in s->width, s->speed
as now a default is provided so this will always be set.
Note this changes the default settings but it is unlikely to have a negative
effect on software as will only affect ports with now downs
Whilst not all link related registers are common between RP / Switch DSP
and EP / Switch USP many of them are. Factor that group out to save
on duplication when adding EP / Swtich USP configurability.
Signed-off-by: Jonathan Cameron
---
hw/pci/pcie.c | 87 ---
Whilst similar to existing PCIESlot link configuration a few registers
need to be set differently so that the downstream device presents
a 'configured' state that is then used to 'train' the upstream port
on the link. Basically that means setting the status register to
reflect it succeeding in tra
To establish performance characteristics of a CXL device when used via a
particular CXL topology (root ports, switches, end points) it is necessary
to set the appropriate link speed and width in the PCI Express capability
structure. Provide x-speed and x-link properties for this.
Signed-off-by: J
To establish performance characteristics of a CXL device when used via a
particular CXL topology (root ports, switches, end points) it is necessary
to set the appropriate link speed and width in the PCI Express capability
structure. Provide x-speed and x-link properties for this.
Signed-off-by: J
These are very similar to the recently added Generic Initiators
but instead of representing an initiator of memory traffic they
represent an edge point beyond which may lie either targets or
initiators. Here we add these ports such that they may
be targets of hmat_lb records to describe the latenc
>From review of generic port introduction.
The value is handled as a uint32_t so store it in that type.
The value cannot in reality exceed MAX_NODES which is currently
128 but if the types are matched there is no need to rely on that
restriction.
Signed-off-by: Jonathan Cameron
---
v6: New patch
>From review of the Generic Ports support.
These properties had no description set so add one.
Signed-off-by: Jonathan Cameron
---
v6: New patch based on Igor's review of Generic Ports patch.
---
hw/acpi/pci.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/acpi/pci.c b/hw/acpi/pci.c
The test to be added exercises many corner cases of the SRAT and HMAT table
generation.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tables-test-allowed-diff.h | 5 +
tests/data/acpi/x86/q35/APIC.acpihmat-generic-x | 0
tests/data/acpi/x86/q35/CEDT.acpihmat-generic-x | 0
tests/d
Add a test with 6 nodes to exercise most interesting corner cases of SRAT
and HMAT generation including the new Generic Initiator and Generic Port
Affinity structures. More details of the set up in the following patch
adding the table data.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-t
Given this is a new configuration, there are affects on APIC, CEDT
and DSDT, but the key elements are in SRAT (plus related data in
HMAT). The configuration has node to exercise many different combinations.
0) CPUs + Memory
1) GI only
2) GP only
3) CPUS only
4) Memory only
5) CPUs + HP memory
GI
Peter Xu writes:
> Zhiyi reported an infinite loop issue in VFIO use case. The cause of that
> was a separate discussion, however during that I found a regression of
> dirty sync slowness when profiling.
>
> Each KVMMemoryListerner maintains an array of kvm memslots. Currently it's
> statically
On Mon, Sep 16, 2024 at 3:06 PM Cédric Le Goater wrote:
>
> On 9/16/24 14:41, Mattias Nissler wrote:
> > Thanks Cédric, I can reproduce now, and my proposed patch fixes avoids
> > the crash as expected.
> disk images for macos9 and macosx10 all boot.
Thanks for testing, happy to hear!
I will go
Fabiano Rosas writes:
> Peter Xu writes:
>
>> Zhiyi reported an infinite loop issue in VFIO use case. The cause of that
>> was a separate discussion, however during that I found a regression of
>> dirty sync slowness when profiling.
>>
>> Each KVMMemoryListerner maintains an array of kvm memslo
These were passing a NULL buffer pointer unconditionally, which happens
to behave in a mostly benign way (except for the chance of an excess
memory region unref and a bounce buffer leak). Per the function comment,
this was never meant to be accepted though, and triggers an assertion
with the "softm
This patch series could use tests. The first two patches seem broken and
testing would have revealed that the memory allocation and pointers are
not quite right.
One testing approach is to write a test device using libvhost-user that
exposes VIRTIO Shared Memory Regions, launch QEMU in qtest mode
On 9/16/24 12:51 PM, Ajeet Singh wrote:
Key Changes Compared to Version 6:
Included "signal-common.h" in target_arch_cpu.h
Thanks. This version is successfully compiling in a FreeBSD x86 host.
Daniel
Mark Corbin (15):
bsd-user: Implement RISC-V CPU initialization and main loop
bsd
OpenSBI enables the floating point in mstatus. For consistency QEMU/KVM
should do the same.
Without this patch EDK II with TLS enabled crashes when hitting the first
floating point instruction while running QEMU with --accel kvm and runs
fine with --accel tcg.
Additionally to this patch EDK II sh
From: Frederic Barrat
These XIVE tests include:
- General interrupt IRQ tests that:
- enable and trigger an interrupt
- acknowledge the interrupt
- end of interrupt processing
- Test the Pull Thread Context to Odd Thread Reporting Line
- Test the different cache flush inject and queue sync
From: Jamin Lin
Introduce a new ast2700 class to support AST2700.
The I2C bus register memory regions and
I2C bus pool buffer memory regions are discontinuous
and they do not back compatible AST2600.
Add a new ast2700 i2c class init function to match the
address of I2C bus register and pool buff
The following changes since commit ea9cdbcf3a0b8d5497cddf87990f1b39d8f3bb0a:
Merge tag 'hw-misc-20240913' of https://github.com/philmd/qemu into staging
(2024-09-15 18:27:40 +0100)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-aspeed-2024091
From: Jamin Lin
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
and the base address of dram is "0x4 " which
is 64bits address.
The AST2700 support the maximum DRAM size is 8 GB.
The DRAM physical address range is from "0x4__" to
"0x5__".
The DRAM offset rang
From: Jamin Lin
Update test case to test lm75 temperature sensor.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/avocado/machine_aspeed.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
From: Jamin Lin
It only support continuous pool buffer memory region for all I2C bus.
However, the pool buffer address of all I2c bus are discontinuous
for AST2700.
Ex: the pool buffer address of I2C bus for ast2700 as following.
0x1A0 - 0x1BF: Device 0 buffer
0x2A0 - 0x2BF: Device 1 buffer
0x3A
From: Jamin Lin
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
and the base address of dram is "0x4 " which
is 64bits address.
It has "Master DMA Mode Tx Buffer Base Address[39:32](0x60)"
and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)"
registers to save the high pa
From: Jamin Lin
The "Current DMA Operating Address Status(0x50)" register of
I2C new mode has been removed in AST2700.
This register is used for debugging and it is a read only register.
To support AST2700 DMA mode, introduce a new
dma_dram_offset class attribute in AspeedI2Cbus to save the
curr
From: Jamin Lin
It only support continuous register memory region for all I2C bus.
However, the register address of all I2c bus are discontinuous
for AST2700.
Ex: the register address of I2C bus for ast2700 as following.
0x100 - 0x17F: Device 0
0x200 - 0x27F: Device 1
0x300 - 0x37F: Device 2
0x4
From: Peter Maydell
In aspeed_gpio_update() we calculate "mask = 1 << gpio", where
gpio can be between 0 and 31. Coverity complains about this
because 1 << 31 won't fit in a signed integer.
For QEMU this isn't an error because we enable -fwrapv,
but we can keep Coverity happy by doing the shift
From: Jamin Lin
According to the datasheet of ASPEED SOCs,
each I2C bus has their own pool buffer since AST2500.
Only AST2400 utilized a pool buffer share to all I2C bus.
Besides, using a share pool buffer only support
pool buffer memory regions are continuous for all I2C bus.
To make this model
From: Jamin Lin
Currently, users can set the INTC mapping table with
enumerated device id and device irq to get the INTC orgate
input pins. However, some devices use the continuous source numbers in the
same INTC orgate. To reduce the enumerated device id definition,
create a new API to get the I
From: Jamin Lin
ASPEED SDK add lm75 in i2c bus 0 for AST2700.
LM75 is compatible with TMP105 driver.
Introduce a new i2c init function and
add tmp105 device model in i2c bus 0.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 10 ++
1 file changed, 10 inse
From: Jamin Lin
Add I2C model for AST2700 I2C support.
The I2C controller registers base address is start at
0x14C0_F000 and its address space is 0x2000.
The AST2700 I2C controller has one source INTC per bus.
I2C buses interrupt are connected to GICINT130_INTC
from bit 0 to bit 15.
I2C bus 0 is
On 9/13/24 16:48, Thomas Huth wrote:
The pci-bridge device is not usable on s390x, so introduce a Kconfig
switch that allows to disable it.
Signed-off-by: Thomas Huth
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/pci-bridge/Kconfig | 5 +
hw/pci-bridge/meson.build | 2 +-
Hyman Huang writes:
> The original migration information dirty-sync-count could
> no longer reflect iteration count due to the introduction
> of background synchronization in the next commit;
> add the iteration count to compensate.
I agree with the overall idea, but I feel we're lacking some in
Hyman Huang writes:
> When VM is configured with huge memory, the current throttle logic
> doesn't look like to scale, because migration_trigger_throttle()
> is only called for each iteration, so it won't be invoked for a long
> time if one iteration can take a long time.
>
> The background sync
Hyman Huang writes:
> To enable the responsive throttle that will be implemented
> in the next commit, introduce the cpu-responsive-throttle
> parameter.
>
> Signed-off-by: Hyman Huang
> ---
> migration/migration-hmp-cmds.c | 8
> migration/options.c| 20 ++
On 16/09/2024 18:57, Mattias Nissler wrote:
These were passing a NULL buffer pointer unconditionally, which happens
to behave in a mostly benign way (except for the chance of an excess
memory region unref and a bounce buffer leak). Per the function comment,
this was never meant to be accepted th
Hyman Huang writes:
> shadow_bmap, iter_bmap and iter_dirty_pages are introduced
> to satisfy the need for background sync.
>
> Meanwhile, introduce enumeration of sync method.
>
> Signed-off-by: Hyman Huang
> ---
> include/exec/ramblock.h | 45 +
> migra
On Mon, 16 Sep 2024, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Expose handle_bufioreq in xen_register_ioreq().
> This is to allow machines to enable or disable buffered ioreqs.
>
> No functional change since all callers still set it to
> HVM_IOREQSRV_BUFIOREQ_ATOMIC.
>
> Signed-o
On Mon, 16 Sep 2024, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add a way to enable/disable buffered IOREQs for PVH machines
> and disable them for ARM. ARM does not support buffered
> IOREQ's nor the legacy way to map IOREQ info pages.
>
> See the following for more details:
> htt
On Mon, 16 Sep 2024, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
Acked-by: Stefano Stabellini
> ---
> hw/xen/xen-pvh-common.c | 36
> 1 file changed, 36 insertions(+)
>
> diff --git a/hw/xen/xen-pvh-common.c
On Mon, 16 Sep 2024, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Enable PCI support for the ARM Xen PVH machine.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Stefano Stabellini
> ---
> hw/arm/xen-pvh.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --gi
From: "Dr. David Alan Gilbert"
aio_task_pool_empty has been unused since it was added in
6e9b225f73 ("block: introduce aio task pool")
Remove it.
Signed-off-by: Dr. David Alan Gilbert
---
block/aio_task.c | 5 -
include/block/aio_task.h | 2 --
2 files changed, 7 deletions(-)
d
From: "Dr. David Alan Gilbert"
blk_by_public last use was removed in 2017 by
c61791fc23 ("block: add aio_context field in ThrottleGroupMember")
blk_activate last use was removed earlier this year by
eef0bae3a7 ("migration: Remove block migration")
blk_add_insert_bs_notifier, blk_op_block_al
From: "Dr. David Alan Gilbert"
xen_be_copy_grant_refs is unused since 2019's
19f87870ba ("xen: remove the legacy 'xen_disk' backend")
xen_config_dev_console is unused since 2018's
6d7c06c213 ("Remove broken Xen PV domain builder")
Remove them.
Signed-off-by: Dr. David Alan Gilbert
---
hw
From: "Dr. David Alan Gilbert"
cursor_get_mono_image has been unused since 2018's
0015ca5cba ("ui: remove support for SDL1.2 in favour of SDL2")
Remove it.
Signed-off-by: Dr. David Alan Gilbert
---
include/ui/console.h | 1 -
ui/cursor.c | 24
2 files chan
Hi Cedric,
On 9/16/24 18:44, Cédric Le Goater wrote:
Hello Harsh,
On 2/19/24 09:29, Nicholas Piggin wrote:
From: Cédric Le Goater
pseries machines before version 2.11 have undergone many changes to
correct issues, mostly regarding migration compatibility. This is
obfuscating the code useless
On 9/13/24 18:20, BALATON Zoltan wrote:
On Fri, 13 Sep 2024, Harsh Prateek Bora wrote:
As previously done for arch specific handlers, simplify var usage in
ppc_next_unmasked_interrupt by caching the env->pending_interrupts and
env->spr[SPR_LPCR] in local vars and using it later at multiple pl
Hi Fabiano,
On 9/13/24 17:02, Fabiano Rosas wrote:
Harsh Prateek Bora writes:
This fix was earlier introduced for do_lstxv_D form with 2cc0e449d173
however got missed for _X form. This patch fixes the same.
Cc: qemu-sta...@nongnu.org
Suggested-by: Fabiano Rosas
Fixes: 70426b5bb738 ("target/
On 16/09/2024 15.49, Peter Maydell wrote:
In commit 1374ed49e1453c300 we forced the cross-i686-tci job to -j1 to
see if this helped with test timeouts. It seems to help with that but
on the other hand we now sometimes run into the overall 60 minute
job timeout. Try -j2 instead.
Signed-off-by: Pe
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing the arch specific code for the now deprecated machine types.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
---
hw/ppc/spapr.c | 235 ---
Mark, thanks for testing and confirming that this doesn't cause any
obvious breakage.
For my curiosity, which path should this patch take to get into
master? Peter, are you going to respin your pull request with this
included?
On Mon, Sep 16, 2024 at 11:06 PM Mark Cave-Ayland
wrote:
>
> On 16/09
On Tue, Sep 17, 2024 at 5:11 AM Fabiano Rosas wrote:
> Hyman Huang writes:
>
> > shadow_bmap, iter_bmap and iter_dirty_pages are introduced
> > to satisfy the need for background sync.
> >
> > Meanwhile, introduce enumeration of sync method.
> >
> > Signed-off-by: Hyman Huang
> > ---
> > inclu
On Tue, Sep 17, 2024 at 4:35 AM Fabiano Rosas wrote:
> Hyman Huang writes:
>
> > The original migration information dirty-sync-count could
> > no longer reflect iteration count due to the introduction
> > of background synchronization in the next commit;
> > add the iteration count to compensate
On Tue, Sep 17, 2024 at 4:55 AM Fabiano Rosas wrote:
> Hyman Huang writes:
>
> > To enable the responsive throttle that will be implemented
> > in the next commit, introduce the cpu-responsive-throttle
> > parameter.
> >
> > Signed-off-by: Hyman Huang
> > ---
> > migration/migration-hmp-cmds.c
Fix a typo to run the pbkdf crypto cipher tests on macOS.
$ make check-unit
...
87/102 qemu:unit / test-crypto-pbkdf OK 2.35s 17 subtests passed
Fixes: ebe0302ac8 ("tests/unit: build pbkdf test on macOS")
Signed-off-by: Philippe Mathieu-Daudé
---
tests/unit/test-crypto-pbkdf.
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