Hi Rob,
Sorry, I haven't had much time to sit down and work on this mail in the last two
weeks but wanted to get somethign back to you. Here it goes.
On Wed, Sep 11, 2024 at 12:42:58AM -0500, Rob Landley wrote:
> Grab this tarball, extract it, and ./run-qemu.sh. It's a simple
> linux+initramfs i
On Fri, Sep 13, 2024 at 6:47 PM Peter Maydell wrote:
>
> On Fri, 13 Sept 2024 at 16:55, Peter Xu wrote:
> >
> > On Thu, Sep 12, 2024 at 03:27:55PM +0100, Peter Maydell wrote:
> > > Coverity is pretty unhappy about this trick, because it isn't able
> > > to recognise that we can figure out the add
Thanks for the report, and my apologies for the breakage.
On Fri, Sep 13, 2024 at 4:47 PM Peter Xu wrote:
>
> On Fri, Sep 13, 2024 at 04:35:32PM +0200, Cédric Le Goater wrote:
> > Hello,
> >
> > +Mark (for the Mac devices)
> >
> > On 9/9/24 22:11, Peter Xu wrote:
> > > From: Mattias Nissler
> >
Thomas Huth writes:
> On 13/09/2024 19.26, Alex Bennée wrote:
>> The multiarch system tests output serial data which should be
>> redirected to the "output" chardev rather than echoed to the console.
>> Remove the unused EXTFLAGS variable while we are at it.
>> Signed-off-by: Alex Bennée
>> ---
Philippe Mathieu-Daudé writes:
> On 13/9/24 19:26, Alex Bennée wrote:
>> While the compilers will generally happily synthesise a 64 bit value
>> for you on 32 bit systems it doesn't exercise anything on QEMU. It
>> also makes it hard to accurately compare the accesses to test_data
>> when instrum
From: Pierrick Bouvier
By using "print-accesses=true" option, mem plugin will now print every
value accessed, with associated size, type (store vs load), symbol,
instruction address and phys/virt address accessed.
Reviewed-by: Richard Henderson
Reviewed-by: Xingtao Yao
Signed-off-by: Pierrick
The existing plugins already liberally use host pointer stuffing for
passing user data which will fail when doing 64 bit guests on 32 bit
hosts. We should discourage this by officially deprecating support and
adding another nail to the 32 bit host coffin.
Message-Id: <20240910140733.4007719-12-ale
I think all these are ready to go having been mostly reviewed in previous
series. The following still need review:
util/timer: avoid deadlock when shutting down
tests/tcg: add a system test to check memory instrumentation
tests/tcg: ensure s390x-softmmu output redirected
tests/tcg/multiarc
This is a simple control flow tracking plugin that uses the latest
inline and conditional operations to detect and track control flow
changes. It is currently an exercise at seeing how useful the changes
are.
Reviewed-by: Pierrick Bouvier
Message-Id: <20240910140733.4007719-14-alex.ben...@linaro.
From: Pierrick Bouvier
A specific plugin test can now read and check a plugin output, to ensure
it contains expected values.
Tested-by: Xingtao Yao
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
Message-Id: <20240724194708.1843704-5-pierrick.bouv...@linaro.org>
Signed-off-by:
From: Pierrick Bouvier
This value can be accessed only during a memory callback, using
new qemu_plugin_mem_get_value function.
Returned value can be extended when QEMU will support accesses wider
than 128 bits.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1719
Resolves: https://gitla
The softmmu memory instrumentation test sees so many more accesses
than a normal translated host and its really not worth fixing up. Lets
deprecate this odd configuration and save on the CI cycles.
Message-Id: <20240910140733.4007719-13-alex.ben...@linaro.org>
Reviewed-by: Pierrick Bouvier
Signed
From: Pierrick Bouvier
Only multiarch tests are run with plugins, and we want to be able to run
per-arch test with plugins too.
Tested-by: Xingtao Yao
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
Message-Id: <20240724194708.1843704-4-pierrick.bouv...@linaro.org>
Signed-off-b
From: Pierrick Bouvier
Different code paths handle memory accesses:
- tcg generated code
- load/store helpers
- atomic helpers
This value is saved in cpu->neg.plugin_mem_value_{high,low}. Values are
written only for accessed word size (upper bits are not set).
Atomic operations are doing read/w
While the compilers will generally happily synthesise a 64 bit value
for you on 32 bit systems it doesn't exercise anything on QEMU. It
also makes it hard to accurately compare the accesses to test_data
when instrumenting.
Message-Id: <20240910140733.4007719-21-alex.ben...@linaro.org>
Reviewed-by:
At first I thought I could compile the user-mode test for system mode
however we already have a fairly comprehensive test case for system
mode in "memory" so lets use that.
As tracking every access will quickly build up with "print-access" we
add a new mode to track groups of reads and writes to r
The multiarch system tests output serial data which should be
redirected to the "output" chardev rather than echoed to the console.
Comment the use of EXTFLAGS variable while we are at it.
Signed-off-by: Alex Bennée
---
v2
- don't remove EXTFLAGS, add comment
---
tests/tcg/s390x/Makefile.sof
This is useful information when debugging memory issues so lets
improve by:
- include the ptr address for u8 fills (like the others)
- indicate the number of operations for reads and writes
- explicitly note when we are flushing
- move the fill printf to after the reset
Message-Id: <20240
When we shut down a guest we disable the timers. However this can
cause deadlock if the guest has queued some async work that is trying
to advance system time and spins forever trying to wind time forward.
Pay attention to the return code and bail early if we can't wind time
forward.
Signed-off-by
From: Pierrick Bouvier
Add an explicit test to check expected memory values are read/written.
8,16,32 load/store are tested for all arch.
64,128 load/store are tested for aarch64/x64.
atomic operations (8,16,32,64) are tested for x64 only.
By default, atomic accesses are non atomic if a single c
Although we asks for instructions per second we work in quanta and
that cannot be 0. Fail to load the plugin instead and report the
minimum IPS we can handle.
Signed-off-by: Alex Bennée
Reported-by: Elisha Hollander
Reviewed-by: Richard Henderson
---
contrib/plugins/ips.c | 5 +
1 file cha
From: Akihiko Odaki
SimPoint is a widely used tool to find the ideal microarchitecture
simulation points so Valgrind[2] and Pin[3] support generating basic
block vectors for use with them. Let's add a corresponding plugin to
QEMU too.
Note that this plugin has a different goal with tests/plugin/
From: Rowan Hart
Signed-off-by: Rowan Hart
Reviewed-by: Pierrick Bouvier
Tested-by: Pierrick Bouvier
Message-Id: <20240827215329.248434-3-rowanbh...@gmail.com>
[AJB: tweak fmt string for vaddr]
Signed-off-by: Alex Bennée
---
vAJB
- tweak fmt string for PRIu64
v2
- add static to arch_sysc
From: Rowan Hart
Signed-off-by: Rowan Hart
Reviewed-by: Pierrick Bouvier
Message-Id: <20240827215329.248434-2-rowanbh...@gmail.com>
[AJB: tweaked cpu_memory_rw_debug call]
Signed-off-by: Alex Bennée
---
vAJB:
- explicit bool for cpu_memory_rw_debug
v2
- fix alignment
---
include/qemu/qem
On Mon, 16 Sept 2024 at 08:35, Mattias Nissler wrote:
>
> On Fri, Sep 13, 2024 at 6:47 PM Peter Maydell
> wrote:
> >
> > On Fri, 13 Sept 2024 at 16:55, Peter Xu wrote:
> > >
> > > On Thu, Sep 12, 2024 at 03:27:55PM +0100, Peter Maydell wrote:
> > > > Coverity is pretty unhappy about this trick,
On Mon, Sep 16, 2024 at 11:05 AM Peter Maydell wrote:
>
> On Mon, 16 Sept 2024 at 08:35, Mattias Nissler wrote:
> >
> > On Fri, Sep 13, 2024 at 6:47 PM Peter Maydell
> > wrote:
> > >
> > > On Fri, 13 Sept 2024 at 16:55, Peter Xu wrote:
> > > >
> > > > On Thu, Sep 12, 2024 at 03:27:55PM +0100,
On 13-09-2024 19:07, Cédric Le Goater wrote:
Hello,
On 9/13/24 15:24, Chalapathi V wrote:
On 12-09-2024 22:25, Cédric Le Goater wrote:
Chalapthi,
On 8/7/24 22:28, Philippe Mathieu-Daudé wrote:
v2:
- Cover PowerNV SSI in MAINTAINERS
- Use GLib API in pnv_spi_xfer_buffer_free()
- Simplify r
On Fri, 13 Sept 2024 at 21:33, Philippe Mathieu-Daudé wrote:
>
> v3: Fixed TMP105 tests
>
> The following changes since commit 28ae3179fc52d2e4d870b635c4a412aab99759e7:
>
> Merge tag 'pull-target-arm-20240913' of
> https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-09-13
> 16:1
On Tue, 3 Sept 2024 at 17:07, Peter Maydell wrote:
>
> This patchset removes the various Arm machines which we deprecated
> for the 9.0 release and are therefore allowed to remove for the 9.2
> release:
> akita, borzoi, cheetah, connex, mainstone, n800, n810,
> spitz, terrier, tosa, verdex, z2
>
Am 14.09.2024 um 10:42 hat Markus Armbruster geschrieben:
> Peter Krempa writes:
>
> > This is a little off-topic:
> >
> > So I wanted to make libvirt use the new parameter to stay ahead
> > deprecation. I've applied this patch to qemu, dumped capabilities and
> > pretty much expected a bunch of
On Mon, 2024-09-16 at 09:53 +0100, Alex Bennée wrote:
> The multiarch system tests output serial data which should be
> redirected to the "output" chardev rather than echoed to the console.
>
> Comment the use of EXTFLAGS variable while we are at it.
>
> Signed-off-by: Alex Bennée
Acked-by: Ily
Hello Michael,
On 9/13/24 18:16, Michael Kowal wrote:
In XIVE Gen 2 there are many operations that were not modeled and are
needed for PowerVM. These changes are associated with the following Thread
Interrupt Management Area subjects:
- OS context
- Thread context
- Pulling contexts to 'c
Hello Saif,
On 3/21/24 11:04, Saif Abrar wrote:
Hello,
This series updates the existing PHB4 model to the latest spec:
"Power Systems Host Bridge 5 (PHB5) Functional Specification Version 0.5_00".
Updates include the following:
- implemented sticky reset logic
- implemented read-only, write-on
On 9/16/24 3:12 AM, Thomas Huth wrote:
On 15/09/2024 21.58, Daniel Henrique Barboza wrote:
Hi Peter, Alistair,
On 9/14/24 6:15 AM, Alistair Francis wrote:
On Fri, Sep 13, 2024 at 8:37 PM Peter Maydell wrote:
On Thu, 12 Sept 2024 at 06:30, Alistair Francis wrote:
The following changes
On Sat, 14 Sep 2024 07:33:14 +0200
Mauro Carvalho Chehab wrote:
> Hi Igor,
>
> Em Fri, 13 Sep 2024 15:25:18 +0200
> Igor Mammedov escreveu:
>
> > > > in addition to this, it needs a patch on top to make sure
> > > > that we migrate hest_addr_le.
> > > > See a08a64627b6b 'ACPI: Record the Gener
Thomas Huth writes:
> The System Control and Management Interface is specific to arm
> machines, so don't include this device in non-arm targets.
>
> Signed-off-by: Thomas Huth
Reviewed-by: Milan Zamazal
Thank you,
Milan
> ---
> hw/virtio/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1
On 16/09/2024 09:23, Mattias Nissler wrote:
Thanks for the report, and my apologies for the breakage.
On Fri, Sep 13, 2024 at 4:47 PM Peter Xu wrote:
On Fri, Sep 13, 2024 at 04:35:32PM +0200, Cédric Le Goater wrote:
Hello,
+Mark (for the Mac devices)
On 9/9/24 22:11, Peter Xu wrote:
From
On Mon, 16 Sept 2024 at 12:29, Mark Cave-Ayland
wrote:
>
> On 16/09/2024 09:23, Mattias Nissler wrote:
> > Looking at the code, the dma_memory_unmap calls in hw/ide/macio.c seem
> > to be passing buffer=NULL unconditionally, since the dma_mem field in
> > struct DBDMA_io is never set to anything n
Hi,
Please CC the RISC-V maintainer (Alistair, that I just CCed in this reply) in
all RISC-V
related patches. It would be nice to also CC qemu-ri...@nongnu.org to get more
visibility
from the RISC-V developers too.
This series won't build in a FreeBSD x86_64 host:
In file included from ../bs
On 9/16/24 10:23, Mattias Nissler wrote:
Thanks for the report, and my apologies for the breakage.
On Fri, Sep 13, 2024 at 4:47 PM Peter Xu wrote:
On Fri, Sep 13, 2024 at 04:35:32PM +0200, Cédric Le Goater wrote:
Hello,
+Mark (for the Mac devices)
On 9/9/24 22:11, Peter Xu wrote:
From: Ma
On 16/09/2024 12:44, Peter Maydell wrote:
On Mon, 16 Sept 2024 at 12:29, Mark Cave-Ayland
wrote:
On 16/09/2024 09:23, Mattias Nissler wrote:
Looking at the code, the dma_memory_unmap calls in hw/ide/macio.c seem
to be passing buffer=NULL unconditionally, since the dma_mem field in
struct DBD
[PATCH] hostmem: Apply merge property after the memory region is initialized
Test on 4k and 64k basic page size aarch64
The patches work well on my Ampere host.
The test results are as expected.
# /home/test/qemu.main/build/qemu-system-aarch64 \
-accel kvm -machine virt -cpu host
The following changes since commit ea9cdbcf3a0b8d5497cddf87990f1b39d8f3bb0a:
Merge tag 'hw-misc-20240913' of https://github.com/philmd/qemu into staging
(2024-09-15 18:27:40 +0100)
are available in the Git repository at:
https://gitlab.com/kraxel/qemu.git
tags/edk2-stable20240
From: Xianglai Li
Added loongarch UEFI BIOS support to compiled scripts.
UEFI code images require 16M alignment, flash images require
16M alignment, under the loongarch architecture.This is agreed
upon when the firmware is loaded in QEMU under Loongarch.
The naming of UEFI under loongarch r
On Mon, 16 Sept 2024 at 13:14, Mark Cave-Ayland
wrote:
>
> On 16/09/2024 12:44, Peter Maydell wrote:
>
> > On Mon, 16 Sept 2024 at 12:29, Mark Cave-Ayland
> > wrote:
> >> I'm fairly sure that this patch would break MacOS 9 which was the reason
> >> that
> >> dma_memory_unmap() was added here in
Signed-off-by: Gerd Hoffmann
---
roms/edk2 | 2 +-
roms/edk2-version | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/roms/edk2 b/roms/edk2
index edc6681206c1..b158dad150bf 16
--- a/roms/edk2
+++ b/roms/edk2
@@ -1 +1 @@
-Subproject commit edc6681206c1a8791981a2
Mattias,
Cédric, can you try with the above patch and/or
crash seems gone.
share more details of your setup so I can verify
You will need a Linnux powerpc or powerpc64 image for mac machines,
which are not common now days, or MacOS images. My debian images
are big. I will try to build you
Thanks Cédric, I can reproduce now, and my proposed patch fixes avoids
the crash as expected.
On Mon, Sep 16, 2024 at 2:28 PM Cédric Le Goater wrote:
>
> Mattias,
>
>
> > Cédric, can you try with the above patch and/or
> >
> > crash seems gone.
> >
> >> share more details of your setup so I can v
On 9/13/2024 9:30 PM, Brad Smith wrote:
On 2024-09-10 10:06 p.m., Brian Cain wrote:
On 9/10/2024 5:26 PM, Brad Smith wrote:
On 2024-09-10 4:17 p.m., Thomas Huth wrote:
Some systems (like OpenBSD) do not have the sha256sum or sha512sum
programs
installed by default. Use the Python hashlib in
On Mon, Sep 16, 2024 at 2:28 PM Peter Maydell wrote:
>
> On Mon, 16 Sept 2024 at 13:14, Mark Cave-Ayland
> wrote:
> >
> > On 16/09/2024 12:44, Peter Maydell wrote:
> >
> > > On Mon, 16 Sept 2024 at 12:29, Mark Cave-Ayland
> > > wrote:
> > >> I'm fairly sure that this patch would break MacOS 9 wh
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there's a warning for implicit function
declarations and it rejects linux-test.c.
glibc/musl's readdir64() declaration in dirent is guarded by
_LARGEFILE64_SOURCE, so we'll define it to fix the warning.
BUILD hexa
On 9/16/24 14:41, Mattias Nissler wrote:
Thanks Cédric, I can reproduce now, and my proposed patch fixes avoids
the crash as expected.
disk images for macos9 and macosx10 all boot.
C.
Brian Cain writes:
> On 9/6/2024 9:39 PM, Brian Cain wrote:
>> With newer clang builds (19.x), there's a warning for implicit function
>> declarations and it rejects linux-test.c.
>>
>> glibc/musl's readdir64() declaration in dirent is guarded by
>> _LARGEFILE64_SOURCE, so we'll define it to fix
Brian Cain writes:
> On 9/6/2024 9:39 PM, Brian Cain wrote:
>> With newer clang builds (19.x), there's a warning for implicit function
>> declarations and it rejects linux-test.c.
>>
>> glibc/musl's readdir64() declaration in dirent is guarded by
>> _LARGEFILE64_SOURCE, so we'll define it to fix
Hello Harsh,
On 2/19/24 09:29, Nicholas Piggin wrote:
From: Cédric Le Goater
pseries machines before version 2.11 have undergone many changes to
correct issues, mostly regarding migration compatibility. This is
obfuscating the code uselessly and makes maintenance more difficult.
Remove them an
On Tue, 2024-09-10 at 19:58 +0200, David Hildenbrand wrote:
> Let's add s390_get_memory_limit(), to query what has been successfully
> set via s390_set_memory_limit(). Allow setting the limit only once.
>
> Signed-off-by: David Hildenbrand
Reviewed-by: Nina Schoetterl-Glausch
Comment below.
>
In commit 1374ed49e1453c300 we forced the cross-i686-tci job to -j1 to
see if this helped with test timeouts. It seems to help with that but
on the other hand we now sometimes run into the overall 60 minute
job timeout. Try -j2 instead.
Signed-off-by: Peter Maydell
---
.gitlab-ci.d/crossbuilds.y
On 9/16/2024 8:12 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there's a warning for implicit function
declarations and it rejects linux-test.c.
glibc/musl's readdir64() declaration in dirent is guarded by
_LARGEFILE64_SOU
On Thu, 12 Sept 2024 at 03:43, Richard Henderson
wrote:
>
> Changes for v3:
> - Zero-extend results in Widen NeonGenNarrowEnvFn return to 64 bits
>
> Only patch 26 needs review.
>
Applied to target-arm.next, thanks.
-- PMM
From: Suravee Suthikulpanit
Rename the MMIO memory region variable 'mmio' to 'mr_mmio'
so to correctly name align with struct AMDVIState::variable type.
No functional change intended.
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Santosh Shukla
---
hw/i386/acpi-build.c | 4 ++--
hw/i38
From: Suravee Suthikulpanit
Introduce 'nodma' shared memory region to support PT mode
so that for each device, we only create an alias to shared memory
region when DMA-remapping is disabled.
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Santosh Shukla
---
hw/i386/amd_iommu.c | 49 ++
From: Suravee Suthikulpanit
The XTSup mode enables x2APIC support for AMD IOMMU, which is needed
to support vcpu w/ APIC ID > 255.
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Santosh Shukla
---
v2:
- Fixed non-kvm build issue by adding a check for kvm_irqchip_is_split()
hw/i386/amd_i
From: Suravee Suthikulpanit
In order to support AMD IOMMU interrupt remapping emulation with PCI
pass-through devices, QEMU needs to notify VFIO when guest IOMMU driver
updates and invalidate the guest interrupt remapping table (IRT), and
communicate information so that the host IOMMU driver can
From: Suravee Suthikulpanit
Use shared memory region for interrupt remapping which can be
aliased by all devices.
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Santosh Shukla
---
hw/i386/amd_iommu.c | 22 ++
hw/i386/amd_iommu.h | 1 +
2 files changed, 15 insertions(
On 9/13/24 15:20, Niek Linnenbank wrote:
Hello Guenter, Gerd,
Thanks for bringing up the question. To be honest I do not know a lot about USB
internals.
When adding the orangepi-pc board emulation, it seemed fairly easy to add it,
but apart from a few basic tests, I did not use the USB functio
Series adds following feature support for emulated amd vIOMMU
1) Pass Through(PT) mode
2) Interrupt Remapping(IR) mode
1) PT mode
Introducing the shared 'nodma' memory region that can be aliased
by all the devices in the PT mode. Shared memory with aliasing
approach will help run VM faster when lo
On 11.09.2024 12:14, gert.wol...@collabora.com wrote:
From: Gert Wollny
Before 176e3783f2ab (ui/sdl2: OpenGL window context)
SDL_CreateRenderer was called unconditionally setting
the swap interval to 0. Since SDL_CreateRenderer is now no
longer called when OpenGL is enabled, the swap interval i
ilable in the Git repository at:
>
> https://gitlab.com/kraxel/qemu.git
> tags/edk2-stable202408-20240916-pull-request
>
> for you to fetch changes up to 2b759fbc9a70258a244f98da3415947dccc2702e:
>
> add loongarch binar
From: "Edgar E. Iglesias"
Expose handle_bufioreq in xen_register_ioreq().
This is to allow machines to enable or disable buffered ioreqs.
No functional change since all callers still set it to
HVM_IOREQSRV_BUFIOREQ_ATOMIC.
Signed-off-by: Edgar E. Iglesias
---
hw/i386/xen/xen-hvm.c |
From: "Edgar E. Iglesias"
Add a way to enable/disable buffered IOREQs for PVH machines
and disable them for ARM. ARM does not support buffered
IOREQ's nor the legacy way to map IOREQ info pages.
See the following for more details:
https://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=2fbd7e60
From: "Edgar E. Iglesias"
Enable PCI on the ARM PVH machine. First we add a way to control the use
of buffered IOREQ's since those are not supported on Xen/ARM.
Finally we enable the PCI support.
I've published some instructions on how to try this including the work in
progress Xen side of the P
From: "Edgar E. Iglesias"
Enable PCI support for the ARM Xen PVH machine.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xen-pvh.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/arm/xen-pvh.c b/hw/arm/xen-pvh.c
index 28af3910ea..33f0dd5982 100644
--- a/hw/arm/xen-pvh.c
+++
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-pvh-common.c | 36
1 file changed, 36 insertions(+)
diff --git a/hw/xen/xen-pvh-common.c b/hw/xen/xen-pvh-common.c
index 76a9b2b945..218ac851cf 100644
--- a/hw/xen/xen-pvh-common.c
++
Yichen Wang writes:
> On Wed, Jul 24, 2024 at 7:50 AM Markus Armbruster wrote:
>>
>> Fabiano Rosas writes:
>>
>> > Yichen Wang writes:
>> >
>> >> On Thu, Jul 11, 2024 at 2:53 PM Yichen Wang
>> >> wrote:
>> >>
>> >>> diff --git a/migration/options.c b/migration/options.c
>> >>> index 645f5500
Brian Cain writes:
> On 9/16/2024 8:12 AM, Alex Bennée wrote:
>> Brian Cain writes:
>>
>>> On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there's a warning for implicit function
declarations and it rejects linux-test.c.
glibc/musl's readdir64() declara
From: Mark Corbin
Introduced RISC-V specific ELF definitions and hardware capability
detection.
Additionally, a function to retrieve hardware capabilities
('get_elf_hwcap') is implemented, which returns the common bits set in
each CPU's ISA strings.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
From: Mark Corbin
Implemented the RISC-V CPU execution loop, including handling various
exceptions and system calls. The loop continuously executes CPU
instructions,processes exceptions, and handles system calls by invoking
FreeBSD syscall handlers.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
From: Mark Corbin
Added definitions for RISC-V register structures, including
general-purpose registers and floating-point registers, in
'target_arch_reg.h'. Implemented the 'target_copy_regs' function to
copy register values from the CPU state to the target register
structure, ensuring proper en
From: Mark Corbin
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
---
bsd-user/riscv/target_arch_cpu.h | 14 ++
1 file changed, 14 insertions(+)
di
From: Mark Corbin
Implemented functions for setting up and initializing threads in the
RISC-V architecture.
The 'target_thread_set_upcall' function sets up the stack pointer,
program counter, and function argument for new threads.
The 'target_thread_init' function initializes thread registers bas
From: Mark Corbin
Added the 'get_mcontext' function to extract and populate
the RISC-V machine context from the CPU state.
This function is used to gather the current state of the
general-purpose registers and store it in a 'target_mcontext_'
structure.
Signed-off-by: Mark Corbin
Signed-off-by:
From: Mark Corbin
Included the prototype for the 'target_cpu_set_tls' function in the
'target_arch.h' header file. This function is responsible for setting
the Thread Local Storage (TLS) register for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richar
From: Mark Corbin
Introduced definitions for the RISC-V system call interface, including
the 'target_pt_regs' structure that outlines the register storage
layout during a system call.
Added constants for hardware machine identifiers.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-aut
From: Mark Corbin
Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch'
system call for the RISC-V architecture.
Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that
the operation is not supported.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed
From: Mark Corbin
Added functions for setting up the RISC-V signal trampoline and signal
frame:
'set_sigtramp_args()': Configures the RISC-V CPU state with arguments
for the signal handler. It sets up the registers with the signal
number,pointers to the signal info and user context, the signal h
From: Mark Corbin
Implemented the 'setup_sigtramp' function for setting up the signal
trampoline code in the RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
---
bsd-user/riscv/target_arch_sigtramp.h | 41 +++
1
From: Mark Corbin
Added definitions for RISC-V signal handling, including structures
and constants for managing signal frames and context
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/riscv/target_arch_signal.h
From: Warner Losh
Added a generic definition for RISC-V64 target-specific details.
Implemented the 'regpairs_aligned' function,which returns 'false'
to indicate that register pairs are not aligned in the RISC-V64 ABI.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard H
From: Warner Losh
Added configuration for RISC-V 64-bit target to the build system.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
---
configs/targets/riscv64-bsd-user.mak | 4
1 file changed, 4 insertions(+)
create mode 100644 configs/targets/risc
From: Mark Corbin
Added definitions for RISC-V VM parameters, including maximum and
default sizes for text, data, and stack, as well as address space
limits.
Implemented helper functions for retrieving and setting specific
values in the CPU state, such as stack pointer and return values.
Signed-
Key Changes Compared to Version 6:
Included "signal-common.h" in target_arch_cpu.h
Mark Corbin (15):
bsd-user: Implement RISC-V CPU initialization and main loop
bsd-user: Add RISC-V CPU execution loop and syscall handling
bsd-user: Implement RISC-V CPU register cloning and reset functions
From: Mark Corbin
Added the initial implementation for RISC-V CPU initialization and main
loop. This includes setting up the general-purpose registers and
program counter based on the provided target architecture definitions.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by
From: Mark Corbin
Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn'
functions for RISC-V architecture,
Both functions ensure that the CPU state and user context are properly
managed.
Signed-off-by: Mark Corbin
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Co-author
On 9/16/2024 10:47 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/16/2024 8:12 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there's a warning for implicit function
declarations and it rejects linux-test.c.
glibc/musl's
On Thu, Sep 12, 2024 at 04:44:30PM +0200, Albert Esteve wrote:
> Add SHMEM_MAP/_UNMAP request to the vhost-user
> spec documentation.
>
> Signed-off-by: Albert Esteve
> ---
> docs/interop/vhost-user.rst | 31 +++
> 1 file changed, 31 insertions(+)
>
> diff --git a/do
On 9/16/2024 11:05 AM, Brian Cain wrote:
On 9/16/2024 10:47 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/16/2024 8:12 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there's a warning for implicit
function
declaration
On Thu, Sep 12, 2024 at 04:44:32PM +0200, Albert Esteve wrote:
> Add GET_SHMEM_CONFIG vhost-user frontend
> message to the spec documentation.
>
> Signed-off-by: Albert Esteve
> ---
> docs/interop/vhost-user.rst | 39 +
> 1 file changed, 39 insertions(+)
>
>
On Thu, Sep 12, 2024 at 04:44:30PM +0200, Albert Esteve wrote:
> Add SHMEM_MAP/_UNMAP request to the vhost-user
> spec documentation.
>
> Signed-off-by: Albert Esteve
> ---
> docs/interop/vhost-user.rst | 31 +++
> 1 file changed, 31 insertions(+)
>
> diff --git a/do
On Thu, Sep 12, 2024 at 04:44:29PM +0200, Albert Esteve wrote:
> As a continuation of the
> "Add SHMEM_MAP/UNMAP requests" patch [1],
> I wanted to split vhost-user spec
> parts into a separate patch, so that
> it could be reviewed and integrated
> separately. Having the specs upstreamed
> would he
v6 changes:
- 2 new patches (11 and 12) to improve things in existing code after
Igor pointed them out in the new code.
- More detailed example provided for docs for control of Generic Ports.
This has proved a difficult concept to convey.
Note there is one question Igor raised for Markus:
-
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